CC_2_CC.elf: file format elf32-msp430 SYMBOL TABLE: 00008000 l d .text 00000000 .text 00009de6 l d .rodata 00000000 .rodata 00000200 l d .bss 00000000 .bss 00000214 l d .noinit 00000000 .noinit 0000ffe0 l d .vectors 00000000 .vectors 00000000 l d .debug_aranges 00000000 .debug_aranges 00000000 l d .debug_info 00000000 .debug_info 00000000 l d .debug_abbrev 00000000 .debug_abbrev 00000000 l d .debug_line 00000000 .debug_line 00000000 l d .debug_frame 00000000 .debug_frame 00000000 l d .debug_str 00000000 .debug_str 00000000 l d .debug_loc 00000000 .debug_loc 00000000 l d .debug_ranges 00000000 .debug_ranges 00000000 l df *ABS* 00000000 main.c 00008644 l .text 00000000 __br_unexpected_ 00000000 l df *ABS* 00000000 spi_hardware.c 00000000 l df *ABS* 00000000 strchr.c 00000000 l df *ABS* 00000000 memcmp.c 00000000 l df *ABS* 00000000 memset.c 00000000 l df *ABS* 00000000 strstr.c 00000000 l df *ABS* 00000000 atoi.c 00000000 l df *ABS* 00000000 sprintf.c 000093da l F .text 00000022 append 00000202 l O .bss 00000002 available_ 00000200 l O .bss 00000002 destination_ 000093fc l F .text 0000003c call_vuprintf 00000000 l df *ABS* 00000000 vuprintf.c 00009496 l F .text 00000198 print_field 00000000 l df *ABS* 00000000 strncmp.c 00000057 g *ABS* 00000000 __BCSCTL1 00000174 g *ABS* 00000000 __TACCR1 00000000 g *ABS* 00000000 __data_size 00008644 w .text 00000000 __isr_14 00000128 g *ABS* 00000000 __FCTL1 00000024 g *ABS* 00000000 __P1IES 0000004b g *ABS* 00000000 __ADC10AE1 00000069 g *ABS* 00000000 __UCB0CTL1 0000946e g F .text 00000016 vsprintf 00000204 g O .bss 00000001 RSSI_DBM_2500 00008644 w .text 00000000 __isr_4 00000002 g *ABS* 00000000 __IFG1 00000060 g *ABS* 00000000 __UCA0CTL0 00008822 g F .text 0000003a sample_adc_chan 00000205 g O .bss 00000001 status_1100 0000012e g *ABS* 00000000 __TAIV 00009454 g F .text 0000001a snprintf 00000000 g .vectors 00000000 _efartext 000091fc g F .text 00000000 __udivhi3 00000001 g *ABS* 00000000 __IE2 00000206 g O .bss 00000001 LQI_1100 0000002b g *ABS* 00000000 __P2IFG 00008d70 g F .text 0000010a RX_STRING_1100 0000001a g *ABS* 00000000 __P3DIR 00009ed8 g *ABS* 00000000 _etext 00000190 g *ABS* 00000000 __TBR 000010f8 g *ABS* 00000000 __CALDCO_16MHZ 00000207 g O .bss 00000001 RSSI_2500 0000001d g *ABS* 00000000 __P4OUT 00008810 g F .text 00000012 sample_adc 000090d8 g F .text 00000050 CC1100_SPI_WRREG 00000014 g *ABS* 00000000 __bss_size 00008c82 g F .text 000000ee RX_STRING_2500 000010fd g *ABS* 00000000 __CALBC1_8MHZ 00008000 w .text 00000000 __watchdog_support 0000863e w .text 00000000 __stop_progExec__ 0000908a g F .text 0000004e CC2500_SPI_WRREG 000088d6 g F .text 00000020 init_B_UART_SPI 0000002d g *ABS* 00000000 __P2IE 0000879a g F .text 00000062 sys_init 00000192 g *ABS* 00000000 __TBCCR0 00008644 w .text 00000000 __isr_11 00000186 g *ABS* 00000000 __TBCCTL2 0000921e g F .text 00000000 __udivsi3 00000025 g *ABS* 00000000 __P1IE 0000006b g *ABS* 00000000 __UCB0BR1 000086e2 g F .text 0000008a tinit 00009484 g F .text 00000012 vsnprintf 00000049 g *ABS* 00000000 __ADC10DTC1 00000066 g *ABS* 00000000 __UCA0RXBUF 00000061 g *ABS* 00000000 __UCA0CTL1 00009da6 g .text 00000000 __udivmoddi4 00008648 g F .text 00000022 P2_VEC 0000889a g F .text 0000001c init_B_UART_232 00000208 g O .bss 00000001 LQI_2500 00000182 g *ABS* 00000000 __TBCCTL0 0000006d g *ABS* 00000000 __UCB0STAT 0000868c g .text 00000000 __isr_5 00000063 g *ABS* 00000000 __UCA0BR1 00009d78 g F .text 00000000 __umoddi3 00009ed8 g *ABS* 00000000 __data_load_start 00008644 g .text 00000000 __dtors_end 00008ec6 g F .text 00000094 TX_1100_STRING 00000053 g *ABS* 00000000 __BCSCTL3 000001bc g *ABS* 00000000 __ADC10SA 00000166 g *ABS* 00000000 __TACCTL2 00009d52 g F .text 00000000 __udivdi3 00000065 g *ABS* 00000000 __UCA0STAT 0000866a g .text 00000000 __isr_2 00000209 g O .bss 00000001 RSSI_1100 00000160 g *ABS* 00000000 __TACTL 0000012c g *ABS* 00000000 __FCTL3 00008644 w .text 00000000 __isr_10 0000002e g *ABS* 00000000 __P2SEL 00000180 g *ABS* 00000000 __TBCTL 000010f9 g *ABS* 00000000 __CALBC1_16MHZ 000000c3 g *ABS* 00000000 __OA1CTL1 00000023 g *ABS* 00000000 __P1IFG 000010fb g *ABS* 00000000 __CALBC1_12MHZ 0000004a g *ABS* 00000000 __ADC10AE0 0000011a g *ABS* 00000000 __UCB0I2CSA 0000885c g F .text 0000001e TX232_A_String 00000172 g *ABS* 00000000 __TACCR0 00000056 g *ABS* 00000000 __DCOCTL 00000003 g *ABS* 00000000 __IFG2 00000214 g O .noinit 00000002 __wdt_clear_value 00008e7a g F .text 0000004c TX_2500_STRING 0000001b g *ABS* 00000000 __P3SEL 000086c4 g .text 00000000 __isr_7 0000ffe0 g O .vectors 00000020 __ivtbl_16 0000006c g *ABS* 00000000 __UCB0I2CIE 0000006a g *ABS* 00000000 __UCB0BR0 00009254 g F .text 00000000 __umodsi3 00000028 g *ABS* 00000000 __P2IN 00008c36 g F .text 0000002a RX_MODE_2500 000088f6 g F .text 0000019e CC2500_WRITE_SPI_RF_SETTINGS 00000118 g *ABS* 00000000 __UCB0I2COA 00000184 g *ABS* 00000000 __TBCCTL1 000001b4 g *ABS* 00000000 __ADC10MEM 00009216 g F .text 00000000 __umodhi3 00008644 w .text 00000000 __isr_0 00000029 g *ABS* 00000000 __P2OUT 0000012a g *ABS* 00000000 __FCTL2 00000064 g *ABS* 00000000 __UCA0MCTL 00008028 w .text 00000000 __do_clear_bss 00000021 g *ABS* 00000000 __P1OUT 0000002c g *ABS* 00000000 __P2IES 00000026 g *ABS* 00000000 __P1SEL 000092fa g F .text 00000056 strstr 00008694 g F .text 00000030 TA1_VEC 00009ccc g F .text 00000028 strncmp 0000921e g .text 00000000 __ext_udivmod32 00000027 g *ABS* 00000000 __P1REN 000088b6 g F .text 00000020 init_A_UART_SPI 000000c0 g *ABS* 00000000 __OA0CTL0 00009de4 w .text 00000000 _unexpected_ 00008694 g .text 00000000 __isr_8 0000020a g O .bss 00000001 PKTSTATUS_1100 00008648 g .text 00000000 __isr_3 0000962e g F .text 0000069e vuprintf 00009270 g F .text 00000020 memcmp 000087fc g F .text 00000014 init_adc 0000919c g F .text 00000060 CC1100_SPI_BURST_WRREG 000010fc g *ABS* 00000000 __CALDCO_8MHZ 0000866a g F .text 00000022 P1_VEC 000091fc g .text 00000000 __ext_udivmod16 00008000 w .text 00000000 _reset_vector__ 00008644 g .text 00000000 __ctors_start 00009cf4 g .text 00000000 __xabi_udivmod64 00008644 w .text 00000000 __isr_12 000010fa g *ABS* 00000000 __CALDCO_12MHZ 0000902a g F .text 00000060 CC1100_SPI_RDREG 00000018 g *ABS* 00000000 __P3IN 00008010 w .text 00000000 __do_copy_data 0000868c g F .text 00000008 ADC_VEC 00000200 g .bss 00000000 __bss_start 00009290 g F .text 0000006a memset 0000803e g F .text 00000600 main 00000176 g *ABS* 00000000 __TACCR2 000000c2 g *ABS* 00000000 __OA1CTL0 00008644 w .text 00000000 __isr_13 00000170 g *ABS* 00000000 __TAR 0000001e g *ABS* 00000000 __P4DIR 0000020c g O .bss 00000002 seconds 00000162 g *ABS* 00000000 __TACCTL0 00010000 g .vectors 00000000 _vectors_end 0000002a g *ABS* 00000000 __P2DIR 0000020e g O .bss 00000001 RSSI_DBM_1100 0000876c g F .text 0000002e delay 00000068 g *ABS* 00000000 __UCB0CTL0 0000002f g *ABS* 00000000 __P2REN 00009438 g F .text 0000001c sprintf 000086c4 g F .text 0000001e RX_VEC 00008fcc g F .text 0000005e CC2500_SPI_RDREG 0000006e g *ABS* 00000000 __UCB0RXBUF 000001b0 g *ABS* 00000000 __ADC10CTL0 00008644 w .text 00000000 __isr_9 0000005e g *ABS* 00000000 __UCA0IRTCTL 00008a94 g F .text 000001a2 CC1100_WRITE_SPI_RF_SETTINGS 000010fe g *ABS* 00000000 __CALDCO_1MHZ 00000067 g *ABS* 00000000 __UCA0TXBUF 0000800c w .text 00000000 __init_stack 0000005d g *ABS* 00000000 __UCA0ABCTL 00000019 g *ABS* 00000000 __P3OUT 000000c1 g *ABS* 00000000 __OA0CTL1 00008f5a g F .text 00000038 CC2500_SPI_STROBE 00008644 g .text 00000000 __dtors_start 00008644 w .text 00000000 __isr_6 00008644 g .text 00000000 __ctors_end 00000062 g *ABS* 00000000 __UCA0BR0 00000600 g *ABS* 00000000 __stack 00008644 w .text 00000000 __isr_1 00000200 g .rodata 00000000 _edata 00000216 g *ABS* 00000000 _end 00000194 g *ABS* 00000000 __TBCCR1 00000048 g *ABS* 00000000 __ADC10DTC0 0000011e g *ABS* 00000000 __TBIV 0000020f g O .bss 00000001 PKTSTATUS_2500 000001b2 g *ABS* 00000000 __ADC10CTL1 00008c60 g F .text 00000022 RX_MODE_1100 00000210 g O .bss 00000002 flags 00000058 g *ABS* 00000000 __BCSCTL2 0000863e w .text 00000000 _endless_loop__ 0000001f g *ABS* 00000000 __P4SEL 00000196 g *ABS* 00000000 __TBCCR2 00009350 g F .text 0000008a atoi 00000022 g *ABS* 00000000 __P1DIR 00000212 g O .bss 00000001 status_2500 0000887a g F .text 00000020 init_A_UART_232 0000005f g *ABS* 00000000 __UCA0IRRCTL 00000010 g *ABS* 00000000 __P3REN 00000164 g *ABS* 00000000 __TACCTL1 0000006f g *ABS* 00000000 __UCB0TXBUF 000010ff g *ABS* 00000000 __CALBC1_1MHZ 00008010 w .text 00000000 __low_level_init 00009128 g F .text 00000074 CC2500_SPI_BURST_WRREG 0000925e g F .text 00000012 strchr 00000011 g *ABS* 00000000 __P4REN 00000200 g .rodata 00000000 __data_start 00000120 g *ABS* 00000000 __WDTCTL 00000000 g *ABS* 00000000 __IE1 00000020 g *ABS* 00000000 __P1IN 0000001c g *ABS* 00000000 __P4IN 00000213 g O .bss 00000001 rx_char 00008f92 g F .text 0000003a CC1100_SPI_STROBE Disassembly of section .text: 00008000 <__watchdog_support>: 8000: 55 42 20 01 mov.b &0x0120,r5 8004: 35 d0 08 5a bis #23048, r5 ;#0x5a08 8008: 82 45 14 02 mov r5, &0x0214 0000800c <__init_stack>: 800c: 31 40 00 06 mov #1536, r1 ;#0x0600 00008010 <__do_copy_data>: 8010: 3f 40 00 00 mov #0, r15 ;#0x0000 8014: 0f 93 tst r15 8016: 08 24 jz $+18 ;abs 0x8028 8018: 92 42 14 02 mov &0x0214,&0x0120 801c: 20 01 801e: 2f 83 decd r15 8020: 9f 4f d8 9e mov -24872(r15),512(r15);0x9ed8(r15), 0x0200(r15) 8024: 00 02 8026: f8 23 jnz $-14 ;abs 0x8018 00008028 <__do_clear_bss>: 8028: 3f 40 14 00 mov #20, r15 ;#0x0014 802c: 0f 93 tst r15 802e: 07 24 jz $+16 ;abs 0x803e 8030: 92 42 14 02 mov &0x0214,&0x0120 8034: 20 01 8036: 1f 83 dec r15 8038: cf 43 00 02 mov.b #0, 512(r15);r3 As==00, 0x0200(r15) 803c: f9 23 jnz $-12 ;abs 0x8030 0000803e
: /** Main function. */ int main(void) { 803e: 31 50 7c ff add #-132, r1 ;#0xff7c int degC, volt, ibat, vbat; volatile long vbatraw, ibatraw, traw,vraw; int interval=10; //set report interval to every other interrupt (5hz) sys_init(); //initialize system parameters 8042: b0 12 9a 87 call #0x879a IE2 |= UCB0RXIE; } void init_A_UART_SPI() { UCA0CTL1 = UCSWRST; 8046: d2 43 61 00 mov.b #1, &0x0061 ;r3 As==01 UCA0CTL1 = UCSWRST | UCSSEL1; 804a: f2 40 81 ff mov.b #-127, &0x0061 ;#0xff81 804e: 61 00 UCA0CTL0 = UCCKPH | UCMSB | UCMST | UCSYNC; 8050: f2 40 a9 ff mov.b #-87, &0x0060 ;#0xffa9 8054: 60 00 UCA0BR0 = 2; 8056: e2 43 62 00 mov.b #2, &0x0062 ;r3 As==10 UCA0BR1 = 0; 805a: c2 43 63 00 mov.b #0, &0x0063 ;r3 As==00 UCA0CTL1 &= ~UCSWRST; 805e: f2 f0 fe ff and.b #-2, &0x0061 ;#0xfffe 8062: 61 00 } void init_B_UART_SPI() { UCB0CTL1 = UCSWRST; 8064: d2 43 69 00 mov.b #1, &0x0069 ;r3 As==01 UCB0CTL1 = UCSWRST | UCSSEL1; 8068: f2 40 81 ff mov.b #-127, &0x0069 ;#0xff81 806c: 69 00 UCB0CTL0 = UCCKPH | UCMSB | UCMST | UCSYNC; 806e: f2 40 a9 ff mov.b #-87, &0x0068 ;#0xffa9 8072: 68 00 UCB0BR0 = 2; 8074: e2 43 6a 00 mov.b #2, &0x006a ;r3 As==10 UCB0BR1 = 0; 8078: c2 43 6b 00 mov.b #0, &0x006b ;r3 As==00 UCB0CTL1 &= ~UCSWRST; 807c: f2 f0 fe ff and.b #-2, &0x0069 ;#0xfffe 8080: 69 00 /**init the ADC10 */ void init_adc() { ADC10AE0 = ADC_0_IN | ADC_1_IN; 8082: f2 40 0c 00 mov.b #12, &0x004a ;#0x000c 8086: 4a 00 ADC10CTL0 = ADC10SR | ADC10ON | ADC10SHT_DIV64; //50kbps reduced power mode, ADC on, 16 clocks per sample window 8088: b2 40 10 1c mov #7184, &0x01b0 ;#0x1c10 808c: b0 01 ADC10CTL1 = ADC10SSEL_ACLK | INCH_2; //ACLK sourced, A2 input 808e: b2 40 08 20 mov #8200, &0x01b2 ;#0x2008 8092: b2 01 P1OUT ^= LED_GRN; delay(0xFFFF); //lil bit O delay P1OUT ^= LED_GRN; */ memset(CC2500_buffer, '\0', 64); //clear the buffer 8094: 3d 40 40 00 mov #64, r13 ;#0x0040 8098: 0e 43 clr r14 809a: 0f 41 mov r1, r15 809c: 3f 50 44 00 add #68, r15 ;#0x0044 80a0: b0 12 90 92 call #0x9290 memset(CC1100_buffer, '\0', 64); //clear the buffer 80a4: 3d 40 40 00 mov #64, r13 ;#0x0040 80a8: 0e 43 clr r14 80aa: 0f 41 mov r1, r15 80ac: 2f 52 add #4, r15 ;r2 As==10 80ae: b0 12 90 92 call #0x9290 //power on reset for 2500 P4OUT &= ~CSn_2500; //power on reset for radio, strobe CSn 80b2: f2 f0 fe ff and.b #-2, &0x001d ;#0xfffe 80b6: 1d 00 delay(0xFF); 80b8: 3f 40 ff 00 mov #255, r15 ;#0x00ff 80bc: b0 12 6c 87 call #0x876c P4OUT |= CSn_2500; 80c0: d2 d3 1d 00 bis.b #1, &0x001d ;r3 As==01 //power on reset for 1100 P1OUT &= ~CSn_1100; //strobe CSn 80c4: f2 f0 fb ff and.b #-5, &0x0021 ;#0xfffb 80c8: 21 00 delay(0xFF); 80ca: 3f 40 ff 00 mov #255, r15 ;#0x00ff 80ce: b0 12 6c 87 call #0x876c P1OUT |= CSn_1100; 80d2: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 delay(0xFFFF); //Give chips time to reset 80d6: 3f 43 mov #-1, r15 ;r3 As==11 80d8: b0 12 6c 87 call #0x876c //init CC2500 CC2500_SPI_STROBE(CCxxx0_SRES); //reset chip 80dc: 7f 40 30 00 mov.b #48, r15 ;#0x0030 80e0: b0 12 5a 8f call #0x8f5a CC2500_WRITE_SPI_RF_SETTINGS(); //init chip 80e4: b0 12 f6 88 call #0x88f6 CC2500_SPI_STROBE(CCxxx0_SIDLE); //put into idle state 80e8: 7f 40 36 00 mov.b #54, r15 ;#0x0036 80ec: b0 12 5a 8f call #0x8f5a do{ CC2500_SPI_STROBE(CCxxx0_SIDLE);//Idle 80f0: 7f 40 36 00 mov.b #54, r15 ;#0x0036 80f4: b0 12 5a 8f call #0x8f5a }while((status_2500 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle 80f8: 5f 42 12 02 mov.b &0x0212,r15 80fc: 3f b0 70 00 bit #112, r15 ;#0x0070 8100: f7 23 jnz $-16 ;abs 0x80f0 TX_2500_STRING("GND:XLT 2500 Startup", 20); 8102: 7e 40 14 00 mov.b #20, r14 ;#0x0014 8106: 3f 40 e6 9d mov #-25114,r15 ;#0x9de6 810a: b0 12 7a 8e call #0x8e7a //length = sprintf(CC2500_buffer,"GND:XLT 2500 Startup"); //TX_2500_STRING(CC2500_buffer, length); //init CC1100 CC1100_SPI_STROBE(CCxxx0_SRES); //reset chip 810e: 7f 40 30 00 mov.b #48, r15 ;#0x0030 8112: b0 12 92 8f call #0x8f92 CC1100_WRITE_SPI_RF_SETTINGS(); //init chip 8116: b0 12 94 8a call #0x8a94 CC1100_SPI_STROBE(CCxxx0_SIDLE); //put into idle state 811a: 7f 40 36 00 mov.b #54, r15 ;#0x0036 811e: b0 12 92 8f call #0x8f92 do{ CC1100_SPI_STROBE(CCxxx0_SIDLE);//Idle 8122: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8126: b0 12 92 8f call #0x8f92 }while((status_1100 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle 812a: 5f 42 05 02 mov.b &0x0205,r15 812e: 3f b0 70 00 bit #112, r15 ;#0x0070 8132: f7 23 jnz $-16 ;abs 0x8122 TX_1100_STRING("GND:XLT 1100 Startup", 20); 8134: 7e 40 14 00 mov.b #20, r14 ;#0x0014 8138: 3f 40 fb 9d mov #-25093,r15 ;#0x9dfb 813c: b0 12 c6 8e call #0x8ec6 P1OUT ^= LED_RED; delay(0xFF); //lil bit O delay P1OUT ^= LED_RED; */ flags = 0; 8140: 82 43 10 02 mov #0, &0x0210 ;r3 As==00 //Verify proper interrupt operation for the CC2500 radio, reboot if wonk P2IFG = 0x00; 8144: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 WDTCTL = WDTPW; while(1); }*/ //Verify proper interrupt operation for the CC1100 radio, reboot if wonk P1IFG = 0x00; 8148: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 /** Setup the timer to generate an interrupt at an interval of milliseconds */ void tinit(unsigned int milliseconds) { TACCTL0 = CCIE; // TACCR0 interrupt enabled 814c: b2 40 10 00 mov #16, &0x0162 ;#0x0010 8150: 62 01 TACTL = TASSEL_1; // ACLK, upmode 8152: b2 40 00 01 mov #256, &0x0160 ;#0x0100 8156: 60 01 TACTL &= ~TAIFG; //clear interrupt 8158: b2 f0 fe ff and #-2, &0x0160 ;#0xfffe 815c: 60 01 TACCR0 = (milliseconds * (unsigned long)12000)/1000; //one second intervals 815e: b2 40 e0 2e mov #12000, &0x0172 ;#0x2ee0 8162: 72 01 //TACCR0 = 12000; // ~1 second TAR = 0; 8164: 82 43 70 01 mov #0, &0x0170 ;r3 As==00 TACTL |= MC_UPTO_CCR0 | TAIE; //enable interrupts, start counting! 8168: b2 d0 12 00 bis #18, &0x0160 ;#0x0012 816c: 60 01 WDTCTL = WDTPW; while(1); }*/ tinit(1000); //start generating an interrupts every 1000mS seconds = 0; 816e: 82 43 0c 02 mov #0, &0x020c ;r3 As==00 eint(); //enable interrupts 8172: 32 d2 eint RX_MODE_2500(); //put CC2500 into listen mode. 8174: b0 12 36 8c call #0x8c36 RX_MODE_1100(); //put CC1100 into listen mode. 8178: b0 12 60 8c call #0x8c60 unsigned char loop; int degC, volt, ibat, vbat; volatile long vbatraw, ibatraw, traw,vraw; int interval=10; //set report interval to every other interrupt (5hz) 817c: 35 40 0a 00 mov #10, r5 ;#0x000a flags &= ~RXCHAR_2500_RDY; //do stuff here //P1OUT &= ~LED_RED; eint(); }*/ if(flags & CC1100_RDY) //Incoming packet on the CC1100 8180: a2 b2 10 02 bit #4, &0x0210 ;r2 As==10 8184: ce 24 jz $+414 ;abs 0x8322 { dint(); 8186: 32 c2 dint 8188: 03 43 nop loop = 1; flags &= ~CC1100_RDY; 818a: b2 f0 fb ff and #-5, &0x0210 ;#0xfffb 818e: 10 02 length = RX_STRING_1100(CC1100_buffer, 64); 8190: 7e 40 40 00 mov.b #64, r14 ;#0x0040 8194: 0f 41 mov r1, r15 8196: 2f 52 add #4, r15 ;r2 As==10 8198: b0 12 70 8d call #0x8d70 819c: 48 4f mov.b r15, r8 P1IFG &= ~GDO0_1100; //reset trashed interrupt state 819e: f2 f0 fe ff and.b #-2, &0x0023 ;#0xfffe 81a2: 23 00 RX_MODE_1100(); //set the radio back to RX mode so we don't miss any packets and TX_IF_CCA can work correctly 81a4: b0 12 60 8c call #0x8c60 TX_2500_STRING(CC2500_buffer,length); //forward it on P2IFG &= ~GDO0_2500; //reset trashed interrupt state RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets*/ //Code to protocol repeat if(LQI_1100 & bit7) //CRC ok 81a8: 5a 42 06 02 mov.b &0x0206,r10 81ac: 4a 93 tst.b r10 81ae: af 34 jge $+352 ;abs 0x830e { if(!memcmp(CALLSIGN,CC1100_buffer,3)) //packet addressed to us 81b0: 3d 40 03 00 mov #3, r13 ;#0x0003 81b4: 0e 41 mov r1, r14 81b6: 2e 52 add #4, r14 ;r2 As==10 81b8: 3f 40 10 9e mov #-25072,r15 ;#0x9e10 81bc: b0 12 70 92 call #0x9270 81c0: 0f 93 tst r15 81c2: 7d 20 jnz $+252 ;abs 0x82be { if(strstr( CC1100_buffer, "interval" ) != NULL) //its an interval query 81c4: 3e 40 14 9e mov #-25068,r14 ;#0x9e14 81c8: 0f 41 mov r1, r15 81ca: 2f 52 add #4, r15 ;r2 As==10 81cc: b0 12 fa 92 call #0x92fa 81d0: 0f 93 tst r15 81d2: 2c 24 jz $+90 ;abs 0x822c { length = atoi(strchr(CC1100_buffer, '=' )+1); //The new interval should follow the equals sign 81d4: 3e 40 3d 00 mov #61, r14 ;#0x003d 81d8: 0f 41 mov r1, r15 81da: 2f 52 add #4, r15 ;r2 As==10 81dc: b0 12 5e 92 call #0x925e 81e0: 1f 53 inc r15 81e2: b0 12 50 93 call #0x9350 81e6: 0a 4f mov r15, r10 if(length > 0) 81e8: 0f 93 tst r15 81ea: 0e 24 jz $+30 ;abs 0x8208 { interval = length; length = snprintf(CC1100_buffer,64,"\e[32mGND:XLT Interval is now %d\e[30m",interval); 81ec: 0f 12 push r15 81ee: 30 12 1d 9e push #-25059 ;#0x9e1d 81f2: 30 12 40 00 push #64 ;#0x0040 81f6: 3f 40 0a 00 mov #10, r15 ;#0x000a 81fa: 0f 51 add r1, r15 81fc: 0f 12 push r15 81fe: b0 12 54 94 call #0x9454 8202: 31 52 add #8, r1 ;r2 As==11 8204: 05 4a mov r10, r5 8206: 0c 3c jmp $+26 ;abs 0x8220 } else length = snprintf(CC1100_buffer,64,"\e[32mGND:XLT Reporting every %d seconds\e[30m",interval); 8208: 05 12 push r5 820a: 30 12 42 9e push #-25022 ;#0x9e42 820e: 30 12 40 00 push #64 ;#0x0040 8212: 3f 40 0a 00 mov #10, r15 ;#0x000a 8216: 0f 51 add r1, r15 8218: 0f 12 push r15 821a: b0 12 54 94 call #0x9454 821e: 31 52 add #8, r1 ;r2 As==11 TX_1100_STRING(CC1100_buffer,length); 8220: 4e 4f mov.b r15, r14 8222: 0f 41 mov r1, r15 8224: 2f 52 add #4, r15 ;r2 As==10 8226: b0 12 c6 8e call #0x8ec6 822a: 43 3c jmp $+136 ;abs 0x82b2 } else if(strstr( CC1100_buffer, "status" ) != NULL) //its a status inquiery 822c: 3e 40 6f 9e mov #-24977,r14 ;#0x9e6f 8230: 0f 41 mov r1, r15 8232: 2f 52 add #4, r15 ;r2 As==10 8234: b0 12 fa 92 call #0x92fa 8238: 0f 93 tst r15 823a: 1f 24 jz $+64 ;abs 0x827a { length = snprintf(CC1100_buffer,64,"GND:XLT 25-R:%ddBm L:%u 11-R:%ddBm L:%u", RSSI_DBM_2500, LQI_2500, RSSI_DBM_1100, LQI_1100); 823c: 4a 4a mov.b r10, r10 823e: 0a 12 push r10 8240: 5f 42 0e 02 mov.b &0x020e,r15 8244: 8f 11 sxt r15 8246: 0f 12 push r15 8248: 5f 42 08 02 mov.b &0x0208,r15 824c: 0f 12 push r15 824e: 5f 42 04 02 mov.b &0x0204,r15 8252: 8f 11 sxt r15 8254: 0f 12 push r15 8256: 30 12 76 9e push #-24970 ;#0x9e76 825a: 30 12 40 00 push #64 ;#0x0040 825e: 3f 40 10 00 mov #16, r15 ;#0x0010 8262: 0f 51 add r1, r15 8264: 0f 12 push r15 8266: b0 12 54 94 call #0x9454 826a: 31 50 0e 00 add #14, r1 ;#0x000e TX_1100_STRING(CC1100_buffer,length); 826e: 4e 4f mov.b r15, r14 8270: 0f 41 mov r1, r15 8272: 2f 52 add #4, r15 ;r2 As==10 8274: b0 12 c6 8e call #0x8ec6 8278: 1c 3c jmp $+58 ;abs 0x82b2 } else if(strstr( CC1100_buffer, "now" ) != NULL) //report now 827a: 3e 40 9e 9e mov #-24930,r14 ;#0x9e9e 827e: 0f 41 mov r1, r15 8280: 2f 52 add #4, r15 ;r2 As==10 8282: b0 12 fa 92 call #0x92fa 8286: 0f 93 tst r15 8288: 04 24 jz $+10 ;abs 0x8292 { flags |= GO_NOW | TIMER_UP; ///set event flags to trigger the reporting 828a: b2 d0 09 00 bis #9, &0x0210 ;#0x0009 828e: 10 02 8290: 10 3c jmp $+34 ;abs 0x82b2 } else //command not recognized, give a pong to ack reception { length = snprintf(CC1100_buffer,64,"\e[34mGND:XLT Pong!\e[30m"); 8292: 30 12 a2 9e push #-24926 ;#0x9ea2 8296: 30 12 40 00 push #64 ;#0x0040 829a: 3f 42 mov #8, r15 ;r2 As==11 829c: 0f 51 add r1, r15 829e: 0f 12 push r15 82a0: b0 12 54 94 call #0x9454 82a4: 31 50 06 00 add #6, r1 ;#0x0006 TX_1100_STRING(CC1100_buffer, length); 82a8: 4e 4f mov.b r15, r14 82aa: 0f 41 mov r1, r15 82ac: 2f 52 add #4, r15 ;r2 As==10 82ae: b0 12 c6 8e call #0x8ec6 } P1IFG &= ~GDO0_1100; //reset trashed interrupt state 82b2: f2 f0 fe ff and.b #-2, &0x0023 ;#0xfffe 82b6: 23 00 RX_MODE_1100(); //set the radio back to RX mode so we don't miss any packets 82b8: b0 12 60 8c call #0x8c60 82bc: 28 3c jmp $+82 ;abs 0x830e dint(); loop = 1; flags &= ~CC1100_RDY; length = RX_STRING_1100(CC1100_buffer, 64); 82be: 4e 48 mov.b r8, r14 82c0: 8e 11 sxt r14 P1IFG &= ~GDO0_1100; //reset trashed interrupt state RX_MODE_1100(); //set the radio back to RX mode so we don't miss any packets } else //packet not for us, repeat this packet to the other radio { if(CC1100_buffer[3] == ':') //If the packet isn't marked, give it a max number of hops 82c2: 5f 41 07 00 mov.b 7(r1), r15 ;0x0007(r1) 82c6: 7f 90 3a 00 cmp.b #58, r15 ;#0x003a 82ca: 0e 20 jnz $+30 ;abs 0x82e8 { CC1100_buffer[3] = DEFAULT_HOPS; 82cc: f1 40 32 00 mov.b #50, 7(r1) ;#0x0032, 0x0007(r1) 82d0: 07 00 TX_2500_STRING(CC1100_buffer,length); 82d2: 4e 4e mov.b r14, r14 82d4: 0f 41 mov r1, r15 82d6: 2f 52 add #4, r15 ;r2 As==10 82d8: b0 12 7a 8e call #0x8e7a P2IFG &= ~GDO0_2500; //reset trashed interrupt state 82dc: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 82e0: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets 82e2: b0 12 36 8c call #0x8c36 82e6: 13 3c jmp $+40 ;abs 0x830e } else if(CC1100_buffer[3] >= '1' && CC1100_buffer[3] <= '9') //dec hop counter if its a number 82e8: 4d 4f mov.b r15, r13 82ea: 7d 50 cf ff add.b #-49, r13 ;#0xffcf 82ee: 7d 90 09 00 cmp.b #9, r13 ;#0x0009 82f2: 0d 2c jc $+28 ;abs 0x830e { CC1100_buffer[3]--; 82f4: 7f 53 add.b #-1, r15 ;r3 As==11 82f6: c1 4f 07 00 mov.b r15, 7(r1) ;0x0007(r1) TX_2500_STRING(CC1100_buffer,length); 82fa: 4e 4e mov.b r14, r14 82fc: 0f 41 mov r1, r15 82fe: 2f 52 add #4, r15 ;r2 As==10 8300: b0 12 7a 8e call #0x8e7a P2IFG &= ~GDO0_2500; //reset trashed interrupt state 8304: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 8308: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets 830a: b0 12 36 8c call #0x8c36 //else if(CC1100_buffer[3] == '0'); //Dead packets don't get repeated } } memset(CC1100_buffer, 0, 64); 830e: 3d 40 40 00 mov #64, r13 ;#0x0040 8312: 0e 43 clr r14 8314: 0f 41 mov r1, r15 8316: 2f 52 add #4, r15 ;r2 As==10 8318: b0 12 90 92 call #0x9290 eint(); 831c: 32 d2 eint eint(); }*/ if(flags & CC1100_RDY) //Incoming packet on the CC1100 { dint(); loop = 1; 831e: 5d 43 mov.b #1, r13 ;r3 As==01 8320: 01 3c jmp $+4 ;abs 0x8324 RX_MODE_2500(); //put CC2500 into listen mode. RX_MODE_1100(); //put CC1100 into listen mode. while (1) //main loop, never ends... { loop = 0; 8322: 4d 43 clr.b r13 } memset(CC1100_buffer, 0, 64); eint(); } if(flags & CC2500_RDY) //Incoming packet on the CC2500 8324: a2 b3 10 02 bit #2, &0x0210 ;r3 As==10 8328: 02 20 jnz $+6 ;abs 0x832e 832a: 30 40 fc 84 br #0x84fc { dint(); 832e: 32 c2 dint 8330: 03 43 nop loop = 1; flags &= ~CC2500_RDY; 8332: b2 f0 fd ff and #-3, &0x0210 ;#0xfffd 8336: 10 02 length = RX_STRING_2500(CC2500_buffer, 64); 8338: 7e 40 40 00 mov.b #64, r14 ;#0x0040 833c: 0f 41 mov r1, r15 833e: 3f 50 44 00 add #68, r15 ;#0x0044 8342: b0 12 82 8c call #0x8c82 8346: 48 4f mov.b r15, r8 P2IFG &= ~GDO0_2500; //reset trashed interrupt state 8348: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 834c: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets and TX_IF_CCA can work correctly 834e: b0 12 36 8c call #0x8c36 if(LQI_2500 & bit7) //CRC ok 8352: 5a 42 08 02 mov.b &0x0208,r10 8356: 4a 93 tst.b r10 8358: c7 34 jge $+400 ;abs 0x84e8 { if(!memcmp(CALLSIGN,CC2500_buffer,3)) //packet addressed to us 835a: 3d 40 03 00 mov #3, r13 ;#0x0003 835e: 0e 41 mov r1, r14 8360: 3e 50 44 00 add #68, r14 ;#0x0044 8364: 3f 40 10 9e mov #-25072,r15 ;#0x9e10 8368: b0 12 70 92 call #0x9270 836c: 0f 93 tst r15 836e: 92 20 jnz $+294 ;abs 0x8494 { if(strstr( CC2500_buffer, "reset" ) != NULL) //its an interval query 8370: 3e 40 ba 9e mov #-24902,r14 ;#0x9eba 8374: 0f 41 mov r1, r15 8376: 3f 50 44 00 add #68, r15 ;#0x0044 837a: b0 12 fa 92 call #0x92fa 837e: 0f 93 tst r15 8380: 04 24 jz $+10 ;abs 0x838a { WDTCTL = WDTPW; 8382: b2 40 00 5a mov #23040, &0x0120 ;#0x5a00 8386: 20 01 8388: ff 3f jmp $+0 ;abs 0x8388 while(1); } if(strstr( CC2500_buffer, "interval" ) != NULL) //its an interval query 838a: 3e 40 14 9e mov #-25068,r14 ;#0x9e14 838e: 0f 41 mov r1, r15 8390: 3f 50 44 00 add #68, r15 ;#0x0044 8394: b0 12 fa 92 call #0x92fa 8398: 0f 93 tst r15 839a: 2e 24 jz $+94 ;abs 0x83f8 { length = atoi(strchr(CC2500_buffer, '=' )+1); //The new interval should follow the equals sign 839c: 3e 40 3d 00 mov #61, r14 ;#0x003d 83a0: 0f 41 mov r1, r15 83a2: 3f 50 44 00 add #68, r15 ;#0x0044 83a6: b0 12 5e 92 call #0x925e 83aa: 1f 53 inc r15 83ac: b0 12 50 93 call #0x9350 83b0: 0a 4f mov r15, r10 if(length > 0) 83b2: 0f 93 tst r15 83b4: 0e 24 jz $+30 ;abs 0x83d2 { interval = length; length = snprintf(CC2500_buffer,64,"\e[32mGND:XLT Interval is now %d\e[30m",interval); 83b6: 0f 12 push r15 83b8: 30 12 1d 9e push #-25059 ;#0x9e1d 83bc: 30 12 40 00 push #64 ;#0x0040 83c0: 3f 40 4a 00 mov #74, r15 ;#0x004a 83c4: 0f 51 add r1, r15 83c6: 0f 12 push r15 83c8: b0 12 54 94 call #0x9454 83cc: 31 52 add #8, r1 ;r2 As==11 83ce: 05 4a mov r10, r5 83d0: 0c 3c jmp $+26 ;abs 0x83ea } else length = snprintf(CC2500_buffer,64,"\e[32mGND:XLT Reporting every %d seconds\e[30m",interval); 83d2: 05 12 push r5 83d4: 30 12 42 9e push #-25022 ;#0x9e42 83d8: 30 12 40 00 push #64 ;#0x0040 83dc: 3f 40 4a 00 mov #74, r15 ;#0x004a 83e0: 0f 51 add r1, r15 83e2: 0f 12 push r15 83e4: b0 12 54 94 call #0x9454 83e8: 31 52 add #8, r1 ;r2 As==11 TX_2500_STRING(CC2500_buffer,length); 83ea: 4e 4f mov.b r15, r14 83ec: 0f 41 mov r1, r15 83ee: 3f 50 44 00 add #68, r15 ;#0x0044 83f2: b0 12 7a 8e call #0x8e7a 83f6: 48 3c jmp $+146 ;abs 0x8488 } else if(strstr( CC2500_buffer, "status" ) != NULL) //its a status inquiery 83f8: 3e 40 6f 9e mov #-24977,r14 ;#0x9e6f 83fc: 0f 41 mov r1, r15 83fe: 3f 50 44 00 add #68, r15 ;#0x0044 8402: b0 12 fa 92 call #0x92fa 8406: 0f 93 tst r15 8408: 20 24 jz $+66 ;abs 0x844a { length = snprintf(CC2500_buffer,64,"GND:XLT 25-R:%ddBm L:%u 11-R:%ddBm L:%u", RSSI_DBM_2500, LQI_2500, RSSI_DBM_1100, LQI_1100); 840a: 5f 42 06 02 mov.b &0x0206,r15 840e: 0f 12 push r15 8410: 5f 42 0e 02 mov.b &0x020e,r15 8414: 8f 11 sxt r15 8416: 0f 12 push r15 8418: 4a 4a mov.b r10, r10 841a: 0a 12 push r10 841c: 5f 42 04 02 mov.b &0x0204,r15 8420: 8f 11 sxt r15 8422: 0f 12 push r15 8424: 30 12 76 9e push #-24970 ;#0x9e76 8428: 30 12 40 00 push #64 ;#0x0040 842c: 3f 40 50 00 mov #80, r15 ;#0x0050 8430: 0f 51 add r1, r15 8432: 0f 12 push r15 8434: b0 12 54 94 call #0x9454 8438: 31 50 0e 00 add #14, r1 ;#0x000e TX_2500_STRING(CC2500_buffer,length); 843c: 4e 4f mov.b r15, r14 843e: 0f 41 mov r1, r15 8440: 3f 50 44 00 add #68, r15 ;#0x0044 8444: b0 12 7a 8e call #0x8e7a 8448: 1f 3c jmp $+64 ;abs 0x8488 } else if(strstr( CC2500_buffer, "now" ) != NULL) //report now 844a: 3e 40 9e 9e mov #-24930,r14 ;#0x9e9e 844e: 0f 41 mov r1, r15 8450: 3f 50 44 00 add #68, r15 ;#0x0044 8454: b0 12 fa 92 call #0x92fa 8458: 0f 93 tst r15 845a: 04 24 jz $+10 ;abs 0x8464 { flags |= GO_NOW | TIMER_UP; ///set event flags to trigger the reporting 845c: b2 d0 09 00 bis #9, &0x0210 ;#0x0009 8460: 10 02 8462: 12 3c jmp $+38 ;abs 0x8488 } else //command not recognized, give a pong to ack reception { length = snprintf(CC2500_buffer,64,"\e[34mGND:XLT Pong!\e[30m"); 8464: 30 12 a2 9e push #-24926 ;#0x9ea2 8468: 30 12 40 00 push #64 ;#0x0040 846c: 3f 40 48 00 mov #72, r15 ;#0x0048 8470: 0f 51 add r1, r15 8472: 0f 12 push r15 8474: b0 12 54 94 call #0x9454 8478: 31 50 06 00 add #6, r1 ;#0x0006 TX_2500_STRING(CC2500_buffer, length); 847c: 4e 4f mov.b r15, r14 847e: 0f 41 mov r1, r15 8480: 3f 50 44 00 add #68, r15 ;#0x0044 8484: b0 12 7a 8e call #0x8e7a } P2IFG &= ~GDO0_2500; //reset trashed interrupt state 8488: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 848c: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets 848e: b0 12 36 8c call #0x8c36 8492: 2a 3c jmp $+86 ;abs 0x84e8 dint(); loop = 1; flags &= ~CC2500_RDY; length = RX_STRING_2500(CC2500_buffer, 64); 8494: 4e 48 mov.b r8, r14 8496: 8e 11 sxt r14 P2IFG &= ~GDO0_2500; //reset trashed interrupt state RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets } else //packet not for us, repeat this packet to the other radio { if(CC2500_buffer[3] == ':') //If the packet isn't marked, give it a max number of hops 8498: 5f 41 47 00 mov.b 71(r1), r15 ;0x0047(r1) 849c: 7f 90 3a 00 cmp.b #58, r15 ;#0x003a 84a0: 0f 20 jnz $+32 ;abs 0x84c0 { CC2500_buffer[3] = DEFAULT_HOPS; 84a2: f1 40 32 00 mov.b #50, 71(r1) ;#0x0032, 0x0047(r1) 84a6: 47 00 TX_1100_STRING(CC2500_buffer,length); 84a8: 4e 4e mov.b r14, r14 84aa: 0f 41 mov r1, r15 84ac: 3f 50 44 00 add #68, r15 ;#0x0044 84b0: b0 12 c6 8e call #0x8ec6 P1IFG &= ~GDO0_1100; //reset trashed interrupt state 84b4: f2 f0 fe ff and.b #-2, &0x0023 ;#0xfffe 84b8: 23 00 RX_MODE_1100(); //set the radio back to RX mode so we don't miss any packets 84ba: b0 12 60 8c call #0x8c60 84be: 14 3c jmp $+42 ;abs 0x84e8 } else if(CC2500_buffer[3] >= '1' && CC2500_buffer[3] <= '9') //dec hop counter if its a number 84c0: 4d 4f mov.b r15, r13 84c2: 7d 50 cf ff add.b #-49, r13 ;#0xffcf 84c6: 7d 90 09 00 cmp.b #9, r13 ;#0x0009 84ca: 0e 2c jc $+30 ;abs 0x84e8 { CC2500_buffer[3]--; 84cc: 7f 53 add.b #-1, r15 ;r3 As==11 84ce: c1 4f 47 00 mov.b r15, 71(r1) ;0x0047(r1) TX_1100_STRING(CC2500_buffer,length); 84d2: 4e 4e mov.b r14, r14 84d4: 0f 41 mov r1, r15 84d6: 3f 50 44 00 add #68, r15 ;#0x0044 84da: b0 12 c6 8e call #0x8ec6 P1IFG &= ~GDO0_1100; //reset trashed interrupt state 84de: f2 f0 fe ff and.b #-2, &0x0023 ;#0xfffe 84e2: 23 00 RX_MODE_1100(); //set the radio back to RX mode so we don't miss any packets 84e4: b0 12 60 8c call #0x8c60 } //else if(CC2500_buffer[3] == '0'); //Dead packets don't get repeated } } memset(CC2500_buffer, 0, 64); 84e8: 3d 40 40 00 mov #64, r13 ;#0x0040 84ec: 0e 43 clr r14 84ee: 0f 41 mov r1, r15 84f0: 3f 50 44 00 add #68, r15 ;#0x0044 84f4: b0 12 90 92 call #0x9290 eint(); 84f8: 32 d2 eint eint(); } if(flags & CC2500_RDY) //Incoming packet on the CC2500 { dint(); loop = 1; 84fa: 5d 43 mov.b #1, r13 ;r3 As==01 } } memset(CC2500_buffer, 0, 64); eint(); } if(flags & TIMER_UP) //Did the timer expire? report your findings! 84fc: 92 b3 10 02 bit #1, &0x0210 ;r3 As==01 8500: 96 24 jz $+302 ;abs 0x862e { loop = 1; if(((seconds) % interval) == 0 || (flags & GO_NOW)) //report every 20 second by default 8502: 1f 42 0c 02 mov &0x020c,r15 8506: 0e 45 mov r5, r14 8508: b0 12 16 92 call #0x9216 850c: 0f 93 tst r15 850e: 05 24 jz $+12 ;abs 0x851a 8510: b2 b2 10 02 bit #8, &0x0210 ;r2 As==11 8514: 02 20 jnz $+6 ;abs 0x851a 8516: 30 40 80 81 br #0x8180 { flags &= ~(TIMER_UP|GO_NOW); //clear the flag 851a: b2 f0 f6 ff and #-10, &0x0210 ;#0xfff6 851e: 10 02 ADC10CTL1 = INCH_10 + ADC10DIV_4; // Temp Sensor ADC10CLK/5 8520: b2 40 80 a0 mov #-24448,&0x01b2 ;#0xa080 8524: b2 01 ADC10CTL0 = SREF_1 + ADC10SHT_3 + REFON + ADC10ON + ADC10IE + ADC10SR; 8526: b2 40 38 3c mov #15416, &0x01b0 ;#0x3c38 852a: b0 01 for( degC = 240; degC > 0; degC-- ); // delay to allow reference to settle ADC10CTL0 |= ENC + ADC10SC; // Sampling and conversion start 852c: b2 d0 03 00 bis #3, &0x01b0 ;#0x0003 8530: b0 01 LPM3; 8532: 32 d0 d0 00 bis #208, r2 ;#0x00d0 traw = ADC10MEM; 8536: 16 42 b4 01 mov &0x01b4,r6 853a: 07 43 clr r7 853c: 81 46 00 00 mov r6, 0(r1) ;0x0000(r1) 8540: 81 47 02 00 mov r7, 2(r1) ;0x0002(r1) ADC10CTL0 &= ~(REFON + ADC10ON); // turn off A/D to save power 8544: b2 f0 cf ff and #-49, &0x01b0 ;#0xffcf 8548: b0 01 dint(); 854a: 32 c2 dint 854c: 03 43 nop degC = (((traw - 673) * 4230) / 1024); 854e: 28 41 mov @r1, r8 8550: 19 41 02 00 mov 2(r1), r9 ;0x0002(r1) memset(CC1100_buffer, 0, 64); 8554: 3d 40 40 00 mov #64, r13 ;#0x0040 8558: 0e 43 clr r14 855a: 0f 41 mov r1, r15 855c: 2f 52 add #4, r15 ;r2 As==10 855e: b0 12 90 92 call #0x9290 length=snprintf(CC1100_buffer,64, "GND:%s S:%u T:%d", CALLSIGN, seconds, degC); //send the temperature to the ground 8562: 1f 42 0c 02 mov &0x020c,r15 LPM3; traw = ADC10MEM; ADC10CTL0 &= ~(REFON + ADC10ON); // turn off A/D to save power dint(); degC = (((traw - 673) * 4230) / 1024); 8566: 0a 48 mov r8, r10 8568: 0b 49 mov r9, r11 856a: 0a 5a rla r10 856c: 0b 6b rlc r11 856e: 0a 5a rla r10 8570: 0b 6b rlc r11 8572: 0a 5a rla r10 8574: 0b 6b rlc r11 8576: 0a 5a rla r10 8578: 0b 6b rlc r11 857a: 0c 4a mov r10, r12 857c: 0d 4b mov r11, r13 857e: 0c 5c rla r12 8580: 0d 6d rlc r13 8582: 0c 5c rla r12 8584: 0d 6d rlc r13 8586: 0c 5c rla r12 8588: 0d 6d rlc r13 858a: 0c 5c rla r12 858c: 0d 6d rlc r13 858e: 0c 5c rla r12 8590: 0d 6d rlc r13 8592: 0c 5a add r10, r12 8594: 0d 6b addc r11, r13 8596: 0c 58 add r8, r12 8598: 0d 69 addc r9, r13 859a: 0c 5c rla r12 859c: 0d 6d rlc r13 859e: 0c 5c rla r12 85a0: 0d 6d rlc r13 85a2: 0c 88 sub r8, r12 85a4: 0d 79 subc r9, r13 85a6: 0c 5c rla r12 85a8: 0d 6d rlc r13 85aa: 0a 4c mov r12, r10 85ac: 0b 4d mov r13, r11 85ae: 3a 50 ba 8f add #-28742,r10 ;#0x8fba 85b2: 3b 60 d4 ff addc #-44, r11 ;#0xffd4 85b6: 0b 93 tst r11 85b8: 06 34 jge $+14 ;abs 0x85c6 85ba: 0a 4c mov r12, r10 85bc: 0b 4d mov r13, r11 85be: 3a 50 b9 93 add #-27719,r10 ;#0x93b9 85c2: 3b 60 d4 ff addc #-44, r11 ;#0xffd4 85c6: 0c 4a mov r10, r12 85c8: 0d 4b mov r11, r13 85ca: 0c 4a mov r10, r12 85cc: 8c 10 swpb r12 85ce: 8d 10 swpb r13 85d0: 4c ed xor.b r13, r12 85d2: 0c ed xor r13, r12 85d4: 8d 11 sxt r13 85d6: 0d 11 rra r13 85d8: 0c 10 rrc r12 85da: 0d 11 rra r13 85dc: 0c 10 rrc r12 memset(CC1100_buffer, 0, 64); length=snprintf(CC1100_buffer,64, "GND:%s S:%u T:%d", CALLSIGN, seconds, degC); //send the temperature to the ground 85de: 0c 12 push r12 85e0: 0f 12 push r15 85e2: 30 12 10 9e push #-25072 ;#0x9e10 85e6: 30 12 c0 9e push #-24896 ;#0x9ec0 85ea: 30 12 40 00 push #64 ;#0x0040 85ee: 3f 40 0e 00 mov #14, r15 ;#0x000e 85f2: 0f 51 add r1, r15 85f4: 0f 12 push r15 85f6: b0 12 54 94 call #0x9454 85fa: 31 50 0c 00 add #12, r1 ;#0x000c 85fe: 0a 4f mov r15, r10 TX_2500_STRING(CC1100_buffer,length); 8600: 4e 4f mov.b r15, r14 8602: 0f 41 mov r1, r15 8604: 2f 52 add #4, r15 ;r2 As==10 8606: b0 12 7a 8e call #0x8e7a P2IFG &= ~GDO0_2500; //reset trashed interrupt state 860a: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 860e: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets 8610: b0 12 36 8c call #0x8c36 TX_1100_STRING(CC1100_buffer,length); 8614: 4e 4a mov.b r10, r14 8616: 0f 41 mov r1, r15 8618: 2f 52 add #4, r15 ;r2 As==10 861a: b0 12 c6 8e call #0x8ec6 P1IFG &= ~GDO0_1100; //reset trashed interrupt state 861e: f2 f0 fe ff and.b #-2, &0x0023 ;#0xfffe 8622: 23 00 RX_MODE_1100(); //set the radio back to RX mode so we don't miss any packets 8624: b0 12 60 8c call #0x8c60 eint(); 8628: 32 d2 eint 862a: 30 40 80 81 br #0x8180 } } if(loop == 0) 862e: 4d 93 tst.b r13 8630: 02 24 jz $+6 ;abs 0x8636 8632: 30 40 80 81 br #0x8180 LPM3; //when we wake up it'll be because of an event 8636: 32 d0 d0 00 bis #208, r2 ;#0x00d0 863a: 30 40 80 81 br #0x8180 0000863e <__stop_progExec__>: 863e: 32 d0 f0 00 bis #240, r2 ;#0x00f0 8642: fd 3f jmp $-4 ;abs 0x863e 00008644 <__ctors_end>: 8644: 30 40 e4 9d br #0x9de4 00008648 : This interrupt is trigger when a packet arrives on the CC2500 */ // Port 2 interripts : the allspice controller is talking to us interrupt (PORT2_VECTOR) P2_VEC(void) { 8648: 0f 12 push r15 dint(); //no nesting! 864a: 32 c2 dint 864c: 03 43 nop if((P2IFG & GDO0_2500) == GDO0_2500) 864e: 5f 42 2b 00 mov.b &0x002b,r15 8652: 1f f3 and #1, r15 ;r3 As==01 8654: 05 24 jz $+12 ;abs 0x8660 { flags |= CC2500_RDY; 8656: a2 d3 10 02 bis #2, &0x0210 ;r3 As==10 LPM3_EXIT; 865a: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) 865e: 02 00 //We need to grab that byte! } P2IFG=0x00; 8660: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 eint(); 8664: 32 d2 eint } 8666: 3f 41 pop r15 8668: 00 13 reti 0000866a : This interrupt is trigger when a packet arrives on the CC1100 */ // Port 2 interripts : the allspice controller is talking to us interrupt (PORT1_VECTOR) P1_VEC(void) { 866a: 0f 12 push r15 dint(); //no nesting! 866c: 32 c2 dint 866e: 03 43 nop if((P1IFG & GDO0_1100) == GDO0_1100) 8670: 5f 42 23 00 mov.b &0x0023,r15 8674: 1f f3 and #1, r15 ;r3 As==01 8676: 05 24 jz $+12 ;abs 0x8682 { flags |= CC1100_RDY; 8678: a2 d2 10 02 bis #4, &0x0210 ;r2 As==10 LPM3_EXIT; 867c: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) 8680: 02 00 //We need to grab that byte! } P1IFG=0x00; 8682: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 eint(); 8686: 32 d2 eint } 8688: 3f 41 pop r15 868a: 00 13 reti 0000868c : */ // Port 2 interripts : the allspice controller is talking to us interrupt (ADC10_VECTOR) ADC_VEC(void) { LPM3_EXIT; 868c: b1 c0 d0 00 bic #208, 0(r1) ;#0x00d0, 0x0000(r1) 8690: 00 00 } 8692: 00 13 reti 00008694 : /** This is called once every overflow */ interrupt (TIMERA1_VECTOR) TA1_VEC(void) { 8694: 0f 12 push r15 dint(); //no nesting! 8696: 32 c2 dint 8698: 03 43 nop if(TAIV == 0x0A) //reading this bit will clear the interrupt flags 869a: 1f 42 2e 01 mov &0x012e,r15 869e: 3f 90 0a 00 cmp #10, r15 ;#0x000a 86a2: 03 24 jz $+8 ;abs 0x86aa flags |= TIMER_UP; seconds++; TACTL &= ~TAIFG; //clear the flag LPM3_EXIT; } eint(); 86a4: 32 d2 eint } 86a6: 3f 41 pop r15 86a8: 00 13 reti dint(); //no nesting! if(TAIV == 0x0A) //reading this bit will clear the interrupt flags { //P1OUT ^= LED_RED; flags |= TIMER_UP; 86aa: 92 d3 10 02 bis #1, &0x0210 ;r3 As==01 seconds++; 86ae: 92 53 0c 02 inc &0x020c TACTL &= ~TAIFG; //clear the flag 86b2: b2 f0 fe ff and #-2, &0x0160 ;#0xfffe 86b6: 60 01 LPM3_EXIT; 86b8: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) 86bc: 02 00 } eint(); 86be: 32 d2 eint } 86c0: 3f 41 pop r15 86c2: 00 13 reti 000086c4 : /** This is called once for every RS232 character that comes in */ //function is broken interrupt (USCIAB0RX_VECTOR) RX_VEC(void) { 86c4: 0f 12 push r15 dint(); //no nesting! 86c6: 32 c2 dint 86c8: 03 43 nop rx_char = UCA0RXBUF; 86ca: d2 42 66 00 mov.b &0x0066,&0x0213 86ce: 13 02 flags |= RXCHAR_RDY; 86d0: b2 d0 10 00 bis #16, &0x0210 ;#0x0010 86d4: 10 02 LPM3_EXIT; 86d6: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) 86da: 02 00 eint(); 86dc: 32 d2 eint } 86de: 3f 41 pop r15 86e0: 00 13 reti 000086e2 : /** Setup the timer to generate an interrupt at an interval of milliseconds */ void tinit(unsigned int milliseconds) { 86e2: 0b 12 push r11 86e4: 0a 12 push r10 TACCTL0 = CCIE; // TACCR0 interrupt enabled 86e6: b2 40 10 00 mov #16, &0x0162 ;#0x0010 86ea: 62 01 TACTL = TASSEL_1; // ACLK, upmode 86ec: b2 40 00 01 mov #256, &0x0160 ;#0x0100 86f0: 60 01 TACTL &= ~TAIFG; //clear interrupt 86f2: b2 f0 fe ff and #-2, &0x0160 ;#0xfffe 86f6: 60 01 TACCR0 = (milliseconds * (unsigned long)12000)/1000; //one second intervals 86f8: 0c 43 clr r12 86fa: 0e 4f mov r15, r14 86fc: 0f 4c mov r12, r15 86fe: 0e 5e rla r14 8700: 0f 6f rlc r15 8702: 0e 5e rla r14 8704: 0f 6f rlc r15 8706: 0e 5e rla r14 8708: 0f 6f rlc r15 870a: 0e 5e rla r14 870c: 0f 6f rlc r15 870e: 0e 5e rla r14 8710: 0f 6f rlc r15 8712: 0c 4e mov r14, r12 8714: 0d 4f mov r15, r13 8716: 0c 5c rla r12 8718: 0d 6d rlc r13 871a: 0c 5c rla r12 871c: 0d 6d rlc r13 871e: 0e 5c add r12, r14 8720: 0f 6d addc r13, r15 8722: 0c 4e mov r14, r12 8724: 0d 4f mov r15, r13 8726: 0c 5c rla r12 8728: 0d 6d rlc r13 872a: 0c 5c rla r12 872c: 0d 6d rlc r13 872e: 0a 4e mov r14, r10 8730: 0b 4f mov r15, r11 8732: 0a 5c add r12, r10 8734: 0b 6d addc r13, r11 8736: 0e 4a mov r10, r14 8738: 0f 4b mov r11, r15 873a: 0e 5e rla r14 873c: 0f 6f rlc r15 873e: 0e 5e rla r14 8740: 0f 6f rlc r15 8742: 0e 5e rla r14 8744: 0f 6f rlc r15 8746: 0e 5e rla r14 8748: 0f 6f rlc r15 874a: 3c 40 e8 03 mov #1000, r12 ;#0x03e8 874e: 0d 43 clr r13 8750: 0e 8a sub r10, r14 8752: 0f 7b subc r11, r15 8754: b0 12 1e 92 call #0x921e 8758: 82 4e 72 01 mov r14, &0x0172 //TACCR0 = 12000; // ~1 second TAR = 0; 875c: 82 43 70 01 mov #0, &0x0170 ;r3 As==00 TACTL |= MC_UPTO_CCR0 | TAIE; //enable interrupts, start counting! 8760: b2 d0 12 00 bis #18, &0x0160 ;#0x0012 8764: 60 01 } 8766: 3a 41 pop r10 8768: 3b 41 pop r11 876a: 30 41 ret 0000876c : Delay function. */ void delay(unsigned int d) { int i; for (i = 0; i: Set up the system */ void sys_init() { WDTCTL = WDTCTL_INIT; //Init watchdog timer 879a: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 879e: 20 01 P1OUT = P1OUT_INIT; //Init output data of port1 87a0: e2 42 21 00 mov.b #4, &0x0021 ;r2 As==10 P2OUT = P2OUT_INIT; //Init output data of port2 87a4: c2 43 29 00 mov.b #0, &0x0029 ;r3 As==00 P3OUT = P3OUT_INIT; 87a8: c2 43 19 00 mov.b #0, &0x0019 ;r3 As==00 P4OUT = P4OUT_INIT; 87ac: d2 43 1d 00 mov.b #1, &0x001d ;r3 As==01 P1SEL = P1SEL_INIT; //Select port or module -function on port1 87b0: c2 43 26 00 mov.b #0, &0x0026 ;r3 As==00 P2SEL = P2SEL_INIT; //Select port or module -function on port2 87b4: f2 40 0c 00 mov.b #12, &0x002e ;#0x000c 87b8: 2e 00 P3SEL = P3SEL_INIT; 87ba: c2 43 1b 00 mov.b #0, &0x001b ;r3 As==00 P4SEL = P4SEL_INIT; 87be: c2 43 1f 00 mov.b #0, &0x001f ;r3 As==00 P1DIR = P1DIR_INIT; //Init port direction register of port1 87c2: f2 40 fc ff mov.b #-4, &0x0022 ;#0xfffc 87c6: 22 00 P2DIR = P2DIR_INIT; //Init port direction register of port2 87c8: f2 40 f0 ff mov.b #-16, &0x002a ;#0xfff0 87cc: 2a 00 P3DIR = P3DIR_INIT; 87ce: f2 40 db ff mov.b #-37, &0x001a ;#0xffdb 87d2: 1a 00 P4DIR = P4DIR_INIT; 87d4: f2 43 1e 00 mov.b #-1, &0x001e ;r3 As==11 P1IES = P1IES_INIT; //init port interrupts 87d8: d2 43 24 00 mov.b #1, &0x0024 ;r3 As==01 P2IES = P2IES_INIT; 87dc: d2 43 2c 00 mov.b #1, &0x002c ;r3 As==01 P1IE = P1IE_INIT; 87e0: d2 43 25 00 mov.b #1, &0x0025 ;r3 As==01 P2IE = P2IE_INIT; 87e4: d2 43 2d 00 mov.b #1, &0x002d ;r3 As==01 BCSCTL1 = CALBC1_8MHZ; // Set DCO 87e8: d2 42 fd 10 mov.b &0x10fd,&0x0057 87ec: 57 00 DCOCTL = CALDCO_8MHZ; 87ee: d2 42 fc 10 mov.b &0x10fc,&0x0056 87f2: 56 00 BCSCTL3 = LFXT1S_2; //use the ultra low oscilator for wakeup intervals, not very accurate/ 87f4: f2 40 20 00 mov.b #32, &0x0053 ;#0x0020 87f8: 53 00 } 87fa: 30 41 ret 000087fc : /**init the ADC10 */ void init_adc() { ADC10AE0 = ADC_0_IN | ADC_1_IN; 87fc: f2 40 0c 00 mov.b #12, &0x004a ;#0x000c 8800: 4a 00 ADC10CTL0 = ADC10SR | ADC10ON | ADC10SHT_DIV64; //50kbps reduced power mode, ADC on, 16 clocks per sample window 8802: b2 40 10 1c mov #7184, &0x01b0 ;#0x1c10 8806: b0 01 ADC10CTL1 = ADC10SSEL_ACLK | INCH_2; //ACLK sourced, A2 input 8808: b2 40 08 20 mov #8200, &0x01b2 ;#0x2008 880c: b2 01 } 880e: 30 41 ret 00008810 : //get a reading from the ADC10MEM int sample_adc() { ADC10CTL0 |= ENC | ADC10SC; // Sampling and conversion start 8810: b2 d0 03 00 bis #3, &0x01b0 ;#0x0003 8814: b0 01 while(ADC10CTL1 & ADC10BUSY); 8816: 92 b3 b2 01 bit #1, &0x01b2 ;r3 As==01 881a: fd 23 jnz $-4 ;abs 0x8816 return ADC10MEM; 881c: 1f 42 b4 01 mov &0x01b4,r15 } 8820: 30 41 ret 00008822 : int sample_adc_chan(int chan) { ADC10CTL0 &= ~ENC; // have to disable ADC10 to change channel 8822: b2 f0 fd ff and #-3, &0x01b0 ;#0xfffd 8826: b0 01 if(chan == INCH_TEMP) ADC10CTL0 |= SREF_VREF_AVSS; //set the ref to 1.5V for the temp sensor 8828: 1e 42 b0 01 mov &0x01b0,r14 } int sample_adc_chan(int chan) { ADC10CTL0 &= ~ENC; // have to disable ADC10 to change channel if(chan == INCH_TEMP) 882c: 3f 90 00 a0 cmp #-24576,r15 ;#0xa000 8830: 10 24 jz $+34 ;abs 0x8852 ADC10CTL0 |= SREF_VREF_AVSS; //set the ref to 1.5V for the temp sensor else ADC10CTL0 &= ~SREF_VREF_AVSS; //set the ref to VCC for the external sensors 8832: 3e f0 ff df and #-8193, r14 ;#0xdfff 8836: 82 4e b0 01 mov r14, &0x01b0 ADC10CTL1 = ADC10SSEL_ACLK | chan; //ACLK sourced, A2 input 883a: 3f d2 bis #8, r15 ;r2 As==11 883c: 82 4f b2 01 mov r15, &0x01b2 ADC10CTL0 |= ENC | ADC10SC; // Sampling and conversion start 8840: b2 d0 03 00 bis #3, &0x01b0 ;#0x0003 8844: b0 01 while(ADC10CTL1 & ADC10BUSY); 8846: 92 b3 b2 01 bit #1, &0x01b2 ;r3 As==01 884a: fd 23 jnz $-4 ;abs 0x8846 return ADC10MEM; 884c: 1f 42 b4 01 mov &0x01b4,r15 } 8850: 30 41 ret int sample_adc_chan(int chan) { ADC10CTL0 &= ~ENC; // have to disable ADC10 to change channel if(chan == INCH_TEMP) ADC10CTL0 |= SREF_VREF_AVSS; //set the ref to 1.5V for the temp sensor 8852: 3e d0 00 20 bis #8192, r14 ;#0x2000 8856: 82 4e b0 01 mov r14, &0x01b0 885a: ef 3f jmp $-32 ;abs 0x883a 0000885c : //function is broken void TX232_A_String( char* string, int length ) { int pointer; for( pointer = 0; pointer < length; pointer++) 885c: 1e 93 cmp #1, r14 ;r3 As==01 885e: 0c 38 jl $+26 ;abs 0x8878 8860: 0c 43 clr r12 while(ADC10CTL1 & ADC10BUSY); return ADC10MEM; } //function is broken void TX232_A_String( char* string, int length ) 8862: 0d 4f mov r15, r13 8864: 0d 5c add r12, r13 { int pointer; for( pointer = 0; pointer < length; pointer++) { //volatile int i; UCA0TXBUF = string[pointer]; 8866: e2 4d 67 00 mov.b @r13, &0x0067 while (!(IFG2&UCA0TXIFG)); // USCI_A0 TX buffer ready? 886a: 5d 42 03 00 mov.b &0x0003,r13 886e: 2d f3 and #2, r13 ;r3 As==10 8870: fc 27 jz $-6 ;abs 0x886a //function is broken void TX232_A_String( char* string, int length ) { int pointer; for( pointer = 0; pointer < length; pointer++) 8872: 1c 53 inc r12 8874: 0c 9e cmp r14, r12 8876: f5 23 jnz $-20 ;abs 0x8862 8878: 30 41 ret 0000887a : } } void init_A_UART_232() { UCA0CTL1 = UCSSEL_2; // SMCLK 887a: f2 40 80 ff mov.b #-128, &0x0061 ;#0xff80 887e: 61 00 //UCA0BR1 = 0x3; //UCA0BR0 = 0x82; // 9600 from 16Mhz //UCA0BR1 = 0x6; UCA0BR0=0xE2; UCA0BR1=0x04; //9600 from 12 8880: f2 40 e2 ff mov.b #-30, &0x0062 ;#0xffe2 8884: 62 00 8886: e2 42 63 00 mov.b #4, &0x0063 ;r2 As==10 UCA0MCTL = UCBRS_2; 888a: e2 42 64 00 mov.b #4, &0x0064 ;r2 As==10 UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** 888e: f2 f0 fe ff and.b #-2, &0x0061 ;#0xfffe 8892: 61 00 IE2 |= UCA0RXIE; 8894: d2 d3 01 00 bis.b #1, &0x0001 ;r3 As==01 } 8898: 30 41 ret 0000889a : //function is broken void init_B_UART_232() { UCB0CTL1 = UCSSEL_2; // SMCLK 889a: f2 40 80 ff mov.b #-128, &0x0069 ;#0xff80 889e: 69 00 UCB0BR0=0xE2; UCA0BR1=0x04; //9600 from 12 88a0: f2 40 e2 ff mov.b #-30, &0x006a ;#0xffe2 88a4: 6a 00 88a6: e2 42 63 00 mov.b #4, &0x0063 ;r2 As==10 //UCB0MCTL = UCBRS_2; UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** 88aa: f2 f0 fe ff and.b #-2, &0x0069 ;#0xfffe 88ae: 69 00 IE2 |= UCB0RXIE; 88b0: e2 d2 01 00 bis.b #4, &0x0001 ;r2 As==10 } 88b4: 30 41 ret 000088b6 : void init_A_UART_SPI() { UCA0CTL1 = UCSWRST; 88b6: d2 43 61 00 mov.b #1, &0x0061 ;r3 As==01 UCA0CTL1 = UCSWRST | UCSSEL1; 88ba: f2 40 81 ff mov.b #-127, &0x0061 ;#0xff81 88be: 61 00 UCA0CTL0 = UCCKPH | UCMSB | UCMST | UCSYNC; 88c0: f2 40 a9 ff mov.b #-87, &0x0060 ;#0xffa9 88c4: 60 00 UCA0BR0 = 2; 88c6: e2 43 62 00 mov.b #2, &0x0062 ;r3 As==10 UCA0BR1 = 0; 88ca: c2 43 63 00 mov.b #0, &0x0063 ;r3 As==00 UCA0CTL1 &= ~UCSWRST; 88ce: f2 f0 fe ff and.b #-2, &0x0061 ;#0xfffe 88d2: 61 00 } 88d4: 30 41 ret 000088d6 : void init_B_UART_SPI() { UCB0CTL1 = UCSWRST; 88d6: d2 43 69 00 mov.b #1, &0x0069 ;r3 As==01 UCB0CTL1 = UCSWRST | UCSSEL1; 88da: f2 40 81 ff mov.b #-127, &0x0069 ;#0xff81 88de: 69 00 UCB0CTL0 = UCCKPH | UCMSB | UCMST | UCSYNC; 88e0: f2 40 a9 ff mov.b #-87, &0x0068 ;#0xffa9 88e4: 68 00 UCB0BR0 = 2; 88e6: e2 43 6a 00 mov.b #2, &0x006a ;r3 As==10 UCB0BR1 = 0; 88ea: c2 43 6b 00 mov.b #0, &0x006b ;r3 As==00 UCB0CTL1 &= ~UCSWRST; 88ee: f2 f0 fe ff and.b #-2, &0x0069 ;#0xfffe 88f2: 69 00 } 88f4: 30 41 ret 000088f6 : Configure the CC2500 chip */ void CC2500_WRITE_SPI_RF_SETTINGS() { // Write register settings CC2500_SPI_WRREG(CCxxx0_IOCFG2, P2_IOCFG2); // GDO2 output pin config. 88f6: 7e 40 0b 00 mov.b #11, r14 ;#0x000b 88fa: 4f 43 clr.b r15 88fc: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_IOCFG0, P2_IOCFG0); // GDO0 output pin config. 8900: 7e 40 06 00 mov.b #6, r14 ;#0x0006 8904: 6f 43 mov.b #2, r15 ;r3 As==10 8906: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_PKTLEN, P2_PKTLEN); // Packet length. 890a: 7e 40 3c 00 mov.b #60, r14 ;#0x003c 890e: 7f 40 06 00 mov.b #6, r15 ;#0x0006 8912: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_PKTCTRL1, P2_PKTCTRL1); // Packet automation control. 8916: 6e 42 mov.b #4, r14 ;r2 As==10 8918: 7f 40 07 00 mov.b #7, r15 ;#0x0007 891c: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_PKTCTRL0, P2_PKTCTRL0); // Packet automation control. 8920: 7e 40 05 00 mov.b #5, r14 ;#0x0005 8924: 7f 42 mov.b #8, r15 ;r2 As==11 8926: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_ADDR, P2_ADDR); // Device address. 892a: 5e 43 mov.b #1, r14 ;r3 As==01 892c: 7f 40 09 00 mov.b #9, r15 ;#0x0009 8930: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_CHANNR, P2_CHANNR); // Channel number. 8934: 7e 40 9a ff mov.b #-102, r14 ;#0xff9a 8938: 7f 40 0a 00 mov.b #10, r15 ;#0x000a 893c: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FSCTRL1, P2_FSCTRL1); // Freq synthesizer control. 8940: 7e 40 0a 00 mov.b #10, r14 ;#0x000a 8944: 7f 40 0b 00 mov.b #11, r15 ;#0x000b 8948: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FSCTRL0, P2_FSCTRL0); // Freq synthesizer control. 894c: 4e 43 clr.b r14 894e: 7f 40 0c 00 mov.b #12, r15 ;#0x000c 8952: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FREQ2, P2_FREQ2); // Freq control word, high byte 8956: 7e 40 5c 00 mov.b #92, r14 ;#0x005c 895a: 7f 40 0d 00 mov.b #13, r15 ;#0x000d 895e: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FREQ1, P2_FREQ1); // Freq control word, mid byte. 8962: 7e 40 4f 00 mov.b #79, r14 ;#0x004f 8966: 7f 40 0e 00 mov.b #14, r15 ;#0x000e 896a: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FREQ0, P2_FREQ0); // Freq control word, low byte. 896e: 7e 40 c0 ff mov.b #-64, r14 ;#0xffc0 8972: 7f 40 0f 00 mov.b #15, r15 ;#0x000f 8976: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_MDMCFG4, P2_MDMCFG4); // Modem configuration. 897a: 7e 40 2d 00 mov.b #45, r14 ;#0x002d 897e: 7f 40 10 00 mov.b #16, r15 ;#0x0010 8982: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_MDMCFG3, P2_MDMCFG3); // Modem configuration. 8986: 7e 40 3b 00 mov.b #59, r14 ;#0x003b 898a: 7f 40 11 00 mov.b #17, r15 ;#0x0011 898e: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_MDMCFG2, P2_MDMCFG2); // Modem configuration. 8992: 7e 40 73 00 mov.b #115, r14 ;#0x0073 8996: 7f 40 12 00 mov.b #18, r15 ;#0x0012 899a: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_MDMCFG1, P2_MDMCFG1); // Modem configuration. 899e: 7e 40 23 00 mov.b #35, r14 ;#0x0023 89a2: 7f 40 13 00 mov.b #19, r15 ;#0x0013 89a6: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_MDMCFG0, P2_MDMCFG0); // Modem configuration. 89aa: 7e 40 b9 ff mov.b #-71, r14 ;#0xffb9 89ae: 7f 40 14 00 mov.b #20, r15 ;#0x0014 89b2: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_DEVIATN, P2_DEVIATN); // Modem dev (when FSK mod en) 89b6: 5e 43 mov.b #1, r14 ;r3 As==01 89b8: 7f 40 15 00 mov.b #21, r15 ;#0x0015 89bc: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_MCSM1 , P2_MCSM1 ); //MainRadio Cntrl State Machine 89c0: 7e 40 33 00 mov.b #51, r14 ;#0x0033 89c4: 7f 40 17 00 mov.b #23, r15 ;#0x0017 89c8: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_MCSM0 , P2_MCSM0 ); //MainRadio Cntrl State Machine 89cc: 7e 40 18 00 mov.b #24, r14 ;#0x0018 89d0: 7f 40 18 00 mov.b #24, r15 ;#0x0018 89d4: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FOCCFG, P2_FOCCFG); // Freq Offset Compens. Config 89d8: 7e 40 1d 00 mov.b #29, r14 ;#0x001d 89dc: 7f 40 19 00 mov.b #25, r15 ;#0x0019 89e0: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_BSCFG, P2_BSCFG); // Bit synchronization config. 89e4: 7e 40 1c 00 mov.b #28, r14 ;#0x001c 89e8: 7f 40 1a 00 mov.b #26, r15 ;#0x001a 89ec: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_AGCCTRL2, P2_AGCCTRL2); // AGC control. 89f0: 7e 40 c7 ff mov.b #-57, r14 ;#0xffc7 89f4: 7f 40 1b 00 mov.b #27, r15 ;#0x001b 89f8: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_AGCCTRL1, P2_AGCCTRL1); // AGC control. 89fc: 4e 43 clr.b r14 89fe: 7f 40 1c 00 mov.b #28, r15 ;#0x001c 8a02: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_AGCCTRL0, P2_AGCCTRL0); // AGC control. 8a06: 7e 40 b0 ff mov.b #-80, r14 ;#0xffb0 8a0a: 7f 40 1d 00 mov.b #29, r15 ;#0x001d 8a0e: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FREND1, P2_FREND1); // Front end RX configuration. 8a12: 7e 40 b6 ff mov.b #-74, r14 ;#0xffb6 8a16: 7f 40 21 00 mov.b #33, r15 ;#0x0021 8a1a: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FREND0, P2_FREND0); // Front end RX configuration. 8a1e: 7e 40 10 00 mov.b #16, r14 ;#0x0010 8a22: 7f 40 22 00 mov.b #34, r15 ;#0x0022 8a26: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FSCAL3, P2_FSCAL3); // Frequency synthesizer cal. 8a2a: 7e 40 ea ff mov.b #-22, r14 ;#0xffea 8a2e: 7f 40 23 00 mov.b #35, r15 ;#0x0023 8a32: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FSCAL2, P2_FSCAL2); // Frequency synthesizer cal. 8a36: 7e 40 0a 00 mov.b #10, r14 ;#0x000a 8a3a: 7f 40 24 00 mov.b #36, r15 ;#0x0024 8a3e: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FSCAL1, P2_FSCAL1); // Frequency synthesizer cal. 8a42: 4e 43 clr.b r14 8a44: 7f 40 25 00 mov.b #37, r15 ;#0x0025 8a48: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FSCAL0, P2_FSCAL0); // Frequency synthesizer cal. 8a4c: 7e 40 11 00 mov.b #17, r14 ;#0x0011 8a50: 7f 40 26 00 mov.b #38, r15 ;#0x0026 8a54: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_FSTEST, P2_FSTEST); // Frequency synthesizer cal. 8a58: 7e 40 59 00 mov.b #89, r14 ;#0x0059 8a5c: 7f 40 29 00 mov.b #41, r15 ;#0x0029 8a60: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_TEST2, P2_TEST2); // Various test settings. 8a64: 7e 40 88 ff mov.b #-120, r14 ;#0xff88 8a68: 7f 40 2c 00 mov.b #44, r15 ;#0x002c 8a6c: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_TEST1, P2_TEST1); // Various test settings. 8a70: 7e 40 31 00 mov.b #49, r14 ;#0x0031 8a74: 7f 40 2d 00 mov.b #45, r15 ;#0x002d 8a78: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_TEST0, P2_TEST0); // Various test settings. 8a7c: 7e 40 0b 00 mov.b #11, r14 ;#0x000b 8a80: 7f 40 2e 00 mov.b #46, r15 ;#0x002e 8a84: b0 12 8a 90 call #0x908a CC2500_SPI_WRREG(CCxxx0_PATABLE, P2_PATABLE); // Output Power 8a88: 7e 43 mov.b #-1, r14 ;r3 As==11 8a8a: 7f 40 3e 00 mov.b #62, r15 ;#0x003e 8a8e: b0 12 8a 90 call #0x908a } 8a92: 30 41 ret 00008a94 : Configure the CC1100 chip */ void CC1100_WRITE_SPI_RF_SETTINGS() { // Write register settings CC1100_SPI_WRREG(CCxxx0_IOCFG2, CC1100_IOCFG2); // GDO2 output pin config. 8a94: 7e 40 0b 00 mov.b #11, r14 ;#0x000b 8a98: 4f 43 clr.b r15 8a9a: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_IOCFG0, CC1100_IOCFG0); // GDO0 output pin config. 8a9e: 7e 40 06 00 mov.b #6, r14 ;#0x0006 8aa2: 6f 43 mov.b #2, r15 ;r3 As==10 8aa4: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_PKTLEN, CC1100_PKTLEN); // Packet length. 8aa8: 7e 40 19 00 mov.b #25, r14 ;#0x0019 8aac: 7f 40 06 00 mov.b #6, r15 ;#0x0006 8ab0: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_PKTCTRL1, CC1100_PKTCTRL1); // Packet automation control. 8ab4: 6e 42 mov.b #4, r14 ;r2 As==10 8ab6: 7f 40 07 00 mov.b #7, r15 ;#0x0007 8aba: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_PKTCTRL0, CC1100_PKTCTRL0); // Packet automation control. 8abe: 6e 42 mov.b #4, r14 ;r2 As==10 8ac0: 7f 42 mov.b #8, r15 ;r2 As==11 8ac2: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_ADDR, CC1100_ADDR); // Device address. 8ac6: 4e 43 clr.b r14 8ac8: 7f 40 09 00 mov.b #9, r15 ;#0x0009 8acc: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_CHANNR, CC1100_CHANNR); // Channel number. 8ad0: 7e 40 0a 00 mov.b #10, r14 ;#0x000a 8ad4: 7f 40 0a 00 mov.b #10, r15 ;#0x000a 8ad8: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FSCTRL1, CC1100_FSCTRL1); // Freq synthesizer control. 8adc: 7e 40 06 00 mov.b #6, r14 ;#0x0006 8ae0: 7f 40 0b 00 mov.b #11, r15 ;#0x000b 8ae4: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FSCTRL0, CC1100_FSCTRL0); // Freq synthesizer control. 8ae8: 4e 43 clr.b r14 8aea: 7f 40 0c 00 mov.b #12, r15 ;#0x000c 8aee: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FREQ2, CC1100_FREQ2); // Freq control word, high byte 8af2: 7e 40 23 00 mov.b #35, r14 ;#0x0023 8af6: 7f 40 0d 00 mov.b #13, r15 ;#0x000d 8afa: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FREQ1, CC1100_FREQ1); // Freq control word, mid byte. 8afe: 7e 40 31 00 mov.b #49, r14 ;#0x0031 8b02: 7f 40 0e 00 mov.b #14, r15 ;#0x000e 8b06: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FREQ0, CC1100_FREQ0); // Freq control word, low byte. 8b0a: 7e 40 3b 00 mov.b #59, r14 ;#0x003b 8b0e: 7f 40 0f 00 mov.b #15, r15 ;#0x000f 8b12: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_MDMCFG4, CC1100_MDMCFG4); // Modem configuration. 8b16: 7e 40 f5 ff mov.b #-11, r14 ;#0xfff5 8b1a: 7f 40 10 00 mov.b #16, r15 ;#0x0010 8b1e: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_MDMCFG3, CC1100_MDMCFG3); // Modem configuration. 8b22: 7e 40 83 ff mov.b #-125, r14 ;#0xff83 8b26: 7f 40 11 00 mov.b #17, r15 ;#0x0011 8b2a: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_MDMCFG2, CC1100_MDMCFG2); // Modem configuration. 8b2e: 7e 40 03 00 mov.b #3, r14 ;#0x0003 8b32: 7f 40 12 00 mov.b #18, r15 ;#0x0012 8b36: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_MDMCFG1, CC1100_MDMCFG1); // Modem configuration. 8b3a: 7e 40 22 00 mov.b #34, r14 ;#0x0022 8b3e: 7f 40 13 00 mov.b #19, r15 ;#0x0013 8b42: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_MDMCFG0, CC1100_MDMCFG0); // Modem configuration. 8b46: 7e 40 f8 ff mov.b #-8, r14 ;#0xfff8 8b4a: 7f 40 14 00 mov.b #20, r15 ;#0x0014 8b4e: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_DEVIATN, CC1100_DEVIATN); // Modem dev (when FSK mod en) 8b52: 7e 40 15 00 mov.b #21, r14 ;#0x0015 8b56: 7f 40 15 00 mov.b #21, r15 ;#0x0015 8b5a: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_MCSM1 , CC1100_MCSM1 ); //MainRadio Cntrl State Machine 8b5e: 7e 40 30 00 mov.b #48, r14 ;#0x0030 8b62: 7f 40 17 00 mov.b #23, r15 ;#0x0017 8b66: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_MCSM0 , CC1100_MCSM0 ); //MainRadio Cntrl State Machine 8b6a: 7e 40 18 00 mov.b #24, r14 ;#0x0018 8b6e: 7f 40 18 00 mov.b #24, r15 ;#0x0018 8b72: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FOCCFG, CC1100_FOCCFG); // Freq Offset Compens. Config 8b76: 7e 40 16 00 mov.b #22, r14 ;#0x0016 8b7a: 7f 40 19 00 mov.b #25, r15 ;#0x0019 8b7e: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_BSCFG, CC1100_BSCFG); // Bit synchronization config. 8b82: 7e 40 6c 00 mov.b #108, r14 ;#0x006c 8b86: 7f 40 1a 00 mov.b #26, r15 ;#0x001a 8b8a: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_AGCCTRL2, CC1100_AGCCTRL2); // AGC control. 8b8e: 7e 40 03 00 mov.b #3, r14 ;#0x0003 8b92: 7f 40 1b 00 mov.b #27, r15 ;#0x001b 8b96: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_AGCCTRL1, CC1100_AGCCTRL1); // AGC control. 8b9a: 7e 40 40 00 mov.b #64, r14 ;#0x0040 8b9e: 7f 40 1c 00 mov.b #28, r15 ;#0x001c 8ba2: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_AGCCTRL0, CC1100_AGCCTRL0); // AGC control. 8ba6: 7e 40 91 ff mov.b #-111, r14 ;#0xff91 8baa: 7f 40 1d 00 mov.b #29, r15 ;#0x001d 8bae: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FREND1, CC1100_FREND1); // Front end RX configuration. 8bb2: 7e 40 56 00 mov.b #86, r14 ;#0x0056 8bb6: 7f 40 21 00 mov.b #33, r15 ;#0x0021 8bba: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FREND0, CC1100_FREND0); // Front end RX configuration. 8bbe: 7e 40 10 00 mov.b #16, r14 ;#0x0010 8bc2: 7f 40 22 00 mov.b #34, r15 ;#0x0022 8bc6: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FSCAL3, CC1100_FSCAL3); // Frequency synthesizer cal. 8bca: 7e 40 e9 ff mov.b #-23, r14 ;#0xffe9 8bce: 7f 40 23 00 mov.b #35, r15 ;#0x0023 8bd2: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FSCAL2, CC1100_FSCAL2); // Frequency synthesizer cal. 8bd6: 7e 40 2a 00 mov.b #42, r14 ;#0x002a 8bda: 7f 40 24 00 mov.b #36, r15 ;#0x0024 8bde: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FSCAL1, CC1100_FSCAL1); // Frequency synthesizer cal. 8be2: 4e 43 clr.b r14 8be4: 7f 40 25 00 mov.b #37, r15 ;#0x0025 8be8: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FSCAL0, CC1100_FSCAL0); // Frequency synthesizer cal. 8bec: 7e 40 1f 00 mov.b #31, r14 ;#0x001f 8bf0: 7f 40 26 00 mov.b #38, r15 ;#0x0026 8bf4: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_FSTEST, CC1100_FSTEST); // Frequency synthesizer cal. 8bf8: 7e 40 59 00 mov.b #89, r14 ;#0x0059 8bfc: 7f 40 29 00 mov.b #41, r15 ;#0x0029 8c00: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_TEST2, CC1100_TEST2); // Various test settings. 8c04: 7e 40 81 ff mov.b #-127, r14 ;#0xff81 8c08: 7f 40 2c 00 mov.b #44, r15 ;#0x002c 8c0c: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_TEST1, CC1100_TEST1); // Various test settings. 8c10: 7e 40 35 00 mov.b #53, r14 ;#0x0035 8c14: 7f 40 2d 00 mov.b #45, r15 ;#0x002d 8c18: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_TEST0, CC1100_TEST0); // Various test settings. 8c1c: 7e 40 09 00 mov.b #9, r14 ;#0x0009 8c20: 7f 40 2e 00 mov.b #46, r15 ;#0x002e 8c24: b0 12 d8 90 call #0x90d8 CC1100_SPI_WRREG(CCxxx0_PATABLE, CC1100_PATABLE); // Output Power 8c28: 7e 40 c0 ff mov.b #-64, r14 ;#0xffc0 8c2c: 7f 40 3e 00 mov.b #62, r15 ;#0x003e 8c30: b0 12 d8 90 call #0x90d8 } 8c34: 30 41 ret 00008c36 : Put the CC2500 chip into listen mode */ void RX_MODE_2500() { CC2500_SPI_STROBE(CCxxx0_SIDLE); 8c36: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8c3a: b0 12 5a 8f call #0x8f5a while(status_2500!=15) //(15)31 for return to TX on complete, see MCSM1 8c3e: f2 90 0f 00 cmp.b #15, &0x0212 ;#0x000f 8c42: 12 02 8c44: 08 24 jz $+18 ;abs 0x8c56 CC2500_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... 8c46: 7f 40 3d 00 mov.b #61, r15 ;#0x003d 8c4a: b0 12 5a 8f call #0x8f5a */ void RX_MODE_2500() { CC2500_SPI_STROBE(CCxxx0_SIDLE); while(status_2500!=15) //(15)31 for return to TX on complete, see MCSM1 8c4e: f2 90 0f 00 cmp.b #15, &0x0212 ;#0x000f 8c52: 12 02 8c54: f8 23 jnz $-14 ;abs 0x8c46 CC2500_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... CC2500_SPI_STROBE(CCxxx0_SRX);//Recieve Mode 8c56: 7f 40 34 00 mov.b #52, r15 ;#0x0034 8c5a: b0 12 5a 8f call #0x8f5a } 8c5e: 30 41 ret 00008c60 : */ void RX_MODE_1100() { //Recieve Mode CC1100_SPI_STROBE(CCxxx0_SRX); 8c60: 7f 40 34 00 mov.b #52, r15 ;#0x0034 8c64: b0 12 92 8f call #0x8f92 while(status_1100!=15) //(15)31 for return to TX on complete, see MCSM1 8c68: f2 90 0f 00 cmp.b #15, &0x0205 ;#0x000f 8c6c: 05 02 8c6e: 08 24 jz $+18 ;abs 0x8c80 CC1100_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... 8c70: 7f 40 3d 00 mov.b #61, r15 ;#0x003d 8c74: b0 12 92 8f call #0x8f92 void RX_MODE_1100() { //Recieve Mode CC1100_SPI_STROBE(CCxxx0_SRX); while(status_1100!=15) //(15)31 for return to TX on complete, see MCSM1 8c78: f2 90 0f 00 cmp.b #15, &0x0205 ;#0x000f 8c7c: 05 02 8c7e: f8 23 jnz $-14 ;abs 0x8c70 8c80: 30 41 ret 00008c82 : /** Grab the waiting packet from the CC2500 */ char RX_STRING_2500(unsigned char *buffer, unsigned char length) { 8c82: 0b 12 push r11 8c84: 0a 12 push r10 8c86: 09 12 push r9 8c88: 08 12 push r8 8c8a: 07 12 push r7 8c8c: 06 12 push r6 8c8e: 07 4f mov r15, r7 8c90: 48 4e mov.b r14, r8 //interrupt driven, GDO0 had better be low! //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet 8c92: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8c96: b0 12 cc 8f call #0x8fcc 8c9a: 49 4f mov.b r15, r9 real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet 8c9c: 7f 40 3b 00 mov.b #59, r15 ;#0x003b 8ca0: b0 12 cc 8f call #0x8fcc 8ca4: 46 4f mov.b r15, r6 for(i=0; i < length && i < pkt_length; i++) 8ca6: 48 93 tst.b r8 8ca8: 59 24 jz $+180 ;abs 0x8d5c 8caa: 49 93 tst.b r9 8cac: 5b 24 jz $+184 ;abs 0x8d64 8cae: 0a 47 mov r7, r10 8cb0: 4b 43 clr.b r11 8cb2: 03 3c jmp $+8 ;abs 0x8cba 8cb4: 1a 53 inc r10 8cb6: 49 9b cmp.b r11, r9 8cb8: 41 24 jz $+132 ;abs 0x8d3c { buffer[i] = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the byte 8cba: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8cbe: b0 12 cc 8f call #0x8fcc 8cc2: ca 4f 00 00 mov.b r15, 0(r10) ;0x0000(r10) //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8cc6: 5b 53 inc.b r11 8cc8: 4b 98 cmp.b r8, r11 8cca: f4 23 jnz $-22 ;abs 0x8cb4 8ccc: 4e 4b mov.b r11, r14 8cce: 4a 49 mov.b r9, r10 { buffer[i] = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the byte //GPSbuf[i] = CC2500_buffer[i]; } buffer[i] = '\0';//set the NULL terminator 8cd0: 0e 57 add r7, r14 8cd2: ce 43 00 00 mov.b #0, 0(r14) ;r3 As==00, 0x0000(r14) RSSI_2500 = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the ESSI 8cd6: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8cda: b0 12 cc 8f call #0x8fcc 8cde: c2 4f 07 02 mov.b r15, &0x0207 LQI_2500 = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the CRC 8ce2: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8ce6: b0 12 cc 8f call #0x8fcc 8cea: c2 4f 08 02 mov.b r15, &0x0208 PKTSTATUS_2500 = CC2500_SPI_RDREG(CCxxx0_PKTSTATUS); 8cee: 7f 40 38 00 mov.b #56, r15 ;#0x0038 8cf2: b0 12 cc 8f call #0x8fcc 8cf6: c2 4f 0f 02 mov.b r15, &0x020f if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported 8cfa: 4e 46 mov.b r6, r14 8cfc: 2a 53 incd r10 8cfe: 0e 9a cmp r10, r14 8d00: 03 24 jz $+8 ;abs 0x8d08 LQI_2500 &= ~bit7; //force it to be INVALID! 8d02: f2 f0 7f 00 and.b #127, &0x0208 ;#0x007f 8d06: 08 02 if (RSSI_2500 >= 128) 8d08: 5e 42 07 02 mov.b &0x0207,r14 8d0c: 4e 93 tst.b r14 8d0e: 1a 38 jl $+54 ;abs 0x8d44 RSSI_DBM_2500 = (int)((int )(RSSI_2500 - 256) / 2) - 72; else RSSI_DBM_2500 = (RSSI_2500 / 2) - 72; 8d10: 12 c3 clrc 8d12: 4e 10 rrc.b r14 8d14: 7e 50 b8 ff add.b #-72, r14 ;#0xffb8 8d18: c2 4e 04 02 mov.b r14, &0x0204 CC2500_SPI_STROBE(CCxxx0_SFRX); //flush the buffer 8d1c: 7f 40 3a 00 mov.b #58, r15 ;#0x003a 8d20: b0 12 5a 8f call #0x8f5a CC2500_SPI_STROBE(CCxxx0_SIDLE); //return to IDLE state 8d24: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8d28: b0 12 5a 8f call #0x8f5a return i; //i = real length } 8d2c: 4f 4b mov.b r11, r15 8d2e: 36 41 pop r6 8d30: 37 41 pop r7 8d32: 38 41 pop r8 8d34: 39 41 pop r9 8d36: 3a 41 pop r10 8d38: 3b 41 pop r11 8d3a: 30 41 ret //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8d3c: 4a 49 mov.b r9, r10 8d3e: 0e 4a mov r10, r14 8d40: 4b 49 mov.b r9, r11 8d42: c6 3f jmp $-114 ;abs 0x8cd0 if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported LQI_2500 &= ~bit7; //force it to be INVALID! if (RSSI_2500 >= 128) RSSI_DBM_2500 = (int)((int )(RSSI_2500 - 256) / 2) - 72; 8d44: 4e 4e mov.b r14, r14 8d46: 0f 4e mov r14, r15 8d48: 3f 50 00 ff add #-256, r15 ;#0xff00 8d4c: 0f 93 tst r15 8d4e: 0e 38 jl $+30 ;abs 0x8d6c 8d50: 0f 11 rra r15 8d52: 7f 50 b8 ff add.b #-72, r15 ;#0xffb8 8d56: c2 4f 04 02 mov.b r15, &0x0204 8d5a: e0 3f jmp $-62 ;abs 0x8d1c //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8d5c: 4b 43 clr.b r11 8d5e: 0e 43 clr r14 8d60: 4a 49 mov.b r9, r10 8d62: b6 3f jmp $-146 ;abs 0x8cd0 8d64: 4b 43 clr.b r11 8d66: 0e 43 clr r14 8d68: 0a 43 clr r10 8d6a: b2 3f jmp $-154 ;abs 0x8cd0 if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported LQI_2500 &= ~bit7; //force it to be INVALID! if (RSSI_2500 >= 128) RSSI_DBM_2500 = (int)((int )(RSSI_2500 - 256) / 2) - 72; 8d6c: 1f 53 inc r15 8d6e: f0 3f jmp $-30 ;abs 0x8d50 00008d70 : /** Grab the waiting packet from the CC1100 */ char RX_STRING_1100(unsigned char *buffer, unsigned char length) { 8d70: 0b 12 push r11 8d72: 0a 12 push r10 8d74: 09 12 push r9 8d76: 08 12 push r8 8d78: 07 12 push r7 8d7a: 06 12 push r6 8d7c: 07 4f mov r15, r7 8d7e: 49 4e mov.b r14, r9 // break; #ifndef FIXED_PACKET_MODE pkt_length = CC1100_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet ASSUMING FIXED PACKET LENGTH #else pkt_length = CC1100_SPI_RDREG(CCxxx0_PKTLEN);//length of the packet ASSUMING VARIABLE PACKET LENGTH 8d80: 7f 40 06 00 mov.b #6, r15 ;#0x0006 8d84: b0 12 2a 90 call #0x902a 8d88: 48 4f mov.b r15, r8 #endif real_length = CC1100_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet 8d8a: 7f 40 3b 00 mov.b #59, r15 ;#0x003b 8d8e: b0 12 2a 90 call #0x902a 8d92: 46 4f mov.b r15, r6 for(i=0; i < length && i < pkt_length; i++) 8d94: 49 93 tst.b r9 8d96: 67 24 jz $+208 ;abs 0x8e66 8d98: 48 93 tst.b r8 8d9a: 69 24 jz $+212 ;abs 0x8e6e 8d9c: 0a 47 mov r7, r10 8d9e: 4b 43 clr.b r11 8da0: 03 3c jmp $+8 ;abs 0x8da8 8da2: 1a 53 inc r10 8da4: 48 9b cmp.b r11, r8 8da6: 5c 24 jz $+186 ;abs 0x8e60 { buffer[i] = CC1100_SPI_RDREG(CCxxx0_RXFIFO);//get the byte 8da8: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8dac: b0 12 2a 90 call #0x902a 8db0: ca 4f 00 00 mov.b r15, 0(r10) ;0x0000(r10) pkt_length = CC1100_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet ASSUMING FIXED PACKET LENGTH #else pkt_length = CC1100_SPI_RDREG(CCxxx0_PKTLEN);//length of the packet ASSUMING VARIABLE PACKET LENGTH #endif real_length = CC1100_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8db4: 5b 53 inc.b r11 8db6: 4b 99 cmp.b r9, r11 8db8: f4 23 jnz $-22 ;abs 0x8da2 8dba: 4e 4b mov.b r11, r14 8dbc: 48 48 mov.b r8, r8 { buffer[i] = CC1100_SPI_RDREG(CCxxx0_RXFIFO);//get the byte } buffer[i] = '\0';//set the NULL terminator 8dbe: 0e 57 add r7, r14 8dc0: ce 43 00 00 mov.b #0, 0(r14) ;r3 As==00, 0x0000(r14) RSSI_1100 = CC1100_SPI_RDREG(CCxxx0_RXFIFO);//get the ESSI 8dc4: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8dc8: b0 12 2a 90 call #0x902a 8dcc: c2 4f 09 02 mov.b r15, &0x0209 LQI_1100 = CC1100_SPI_RDREG(CCxxx0_RXFIFO);//get the CRC 8dd0: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8dd4: b0 12 2a 90 call #0x902a 8dd8: c2 4f 06 02 mov.b r15, &0x0206 PKTSTATUS_1100 = CC1100_SPI_RDREG(CCxxx0_PKTSTATUS); 8ddc: 7f 40 38 00 mov.b #56, r15 ;#0x0038 8de0: b0 12 2a 90 call #0x902a 8de4: c2 4f 0a 02 mov.b r15, &0x020a if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported 8de8: 4f 46 mov.b r6, r15 8dea: 28 53 incd r8 8dec: 0f 98 cmp r8, r15 8dee: 0d 24 jz $+28 ;abs 0x8e0a { LQI_1100 &= ~bit7; //force it to be INVALID! 8df0: f2 f0 7f 00 and.b #127, &0x0206 ;#0x007f 8df4: 06 02 //guess at length i = strlen(buffer); 8df6: 0b 47 mov r7, r11 8df8: 3b 53 add #-1, r11 ;r3 As==11 8dfa: 1b 53 inc r11 8dfc: cb 93 00 00 tst.b 0(r11) ;0x0000(r11) 8e00: fc 23 jnz $-6 ;abs 0x8dfa 8e02: 0b 87 sub r7, r11 if( i > length) 8e04: 49 9b cmp.b r11, r9 8e06: 1b 28 jnc $+56 ;abs 0x8e3e 8e08: 4b 4b mov.b r11, r11 i = 0; } if (RSSI_1100 >= 128) 8e0a: 5e 42 09 02 mov.b &0x0209,r14 8e0e: 4e 93 tst.b r14 8e10: 1b 38 jl $+56 ;abs 0x8e48 RSSI_DBM_1100 = (int)((int )(RSSI_1100 - 256) / 2) - 72; else RSSI_DBM_1100 = (RSSI_1100 / 2) - 72; 8e12: 12 c3 clrc 8e14: 4e 10 rrc.b r14 8e16: 7e 50 b8 ff add.b #-72, r14 ;#0xffb8 8e1a: c2 4e 0e 02 mov.b r14, &0x020e CC1100_SPI_STROBE(CCxxx0_SFRX); //flush the buffer 8e1e: 7f 40 3a 00 mov.b #58, r15 ;#0x003a 8e22: b0 12 92 8f call #0x8f92 CC1100_SPI_STROBE(CCxxx0_SIDLE); //return to IDLE state 8e26: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8e2a: b0 12 92 8f call #0x8f92 return i; //i = real length } 8e2e: 4f 4b mov.b r11, r15 8e30: 36 41 pop r6 8e32: 37 41 pop r7 8e34: 38 41 pop r8 8e36: 39 41 pop r9 8e38: 3a 41 pop r10 8e3a: 3b 41 pop r11 8e3c: 30 41 ret if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported { LQI_1100 &= ~bit7; //force it to be INVALID! //guess at length i = strlen(buffer); if( i > length) 8e3e: 4b 43 clr.b r11 i = 0; } if (RSSI_1100 >= 128) 8e40: 5e 42 09 02 mov.b &0x0209,r14 8e44: 4e 93 tst.b r14 8e46: e5 37 jge $-52 ;abs 0x8e12 RSSI_DBM_1100 = (int)((int )(RSSI_1100 - 256) / 2) - 72; 8e48: 4e 4e mov.b r14, r14 8e4a: 0f 4e mov r14, r15 8e4c: 3f 50 00 ff add #-256, r15 ;#0xff00 8e50: 0f 93 tst r15 8e52: 11 38 jl $+36 ;abs 0x8e76 8e54: 0f 11 rra r15 8e56: 7f 50 b8 ff add.b #-72, r15 ;#0xffb8 8e5a: c2 4f 0e 02 mov.b r15, &0x020e 8e5e: df 3f jmp $-64 ;abs 0x8e1e pkt_length = CC1100_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet ASSUMING FIXED PACKET LENGTH #else pkt_length = CC1100_SPI_RDREG(CCxxx0_PKTLEN);//length of the packet ASSUMING VARIABLE PACKET LENGTH #endif real_length = CC1100_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8e60: 48 4b mov.b r11, r8 8e62: 0e 48 mov r8, r14 8e64: ac 3f jmp $-166 ;abs 0x8dbe 8e66: 0e 43 clr r14 8e68: 4b 43 clr.b r11 8e6a: 48 48 mov.b r8, r8 8e6c: a8 3f jmp $-174 ;abs 0x8dbe 8e6e: 0e 43 clr r14 8e70: 4b 43 clr.b r11 8e72: 08 43 clr r8 8e74: a4 3f jmp $-182 ;abs 0x8dbe if( i > length) i = 0; } if (RSSI_1100 >= 128) RSSI_DBM_1100 = (int)((int )(RSSI_1100 - 256) / 2) - 72; 8e76: 1f 53 inc r15 8e78: ed 3f jmp $-36 ;abs 0x8e54 00008e7a : /** Transmit a string of bytes.on the CC2500 */ void TX_2500_STRING(unsigned char *txstring, unsigned char length) { 8e7a: 0b 12 push r11 8e7c: 0a 12 push r10 8e7e: 0b 4f mov r15, r11 8e80: 4a 4e mov.b r14, r10 //unsigned char i; //length += 3; do{ CC2500_SPI_STROBE(CCxxx0_SIDLE);//Idle 8e82: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8e86: b0 12 5a 8f call #0x8f5a }while((status_2500 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle 8e8a: 5f 42 12 02 mov.b &0x0212,r15 8e8e: 3f b0 70 00 bit #112, r15 ;#0x0070 8e92: f7 23 jnz $-16 ;abs 0x8e82 { if(i < length) CC2500_SPI_WRREG(CCxxx0_TXFIFO, txstring[i]);//Write data to FIFO }*/ CC2500_SPI_BURST_WRREG(CCxxx0_TXFIFO_BURST, txstring, length); 8e94: 4d 4a mov.b r10, r13 8e96: 0e 4b mov r11, r14 8e98: 7f 40 7f 00 mov.b #127, r15 ;#0x007f 8e9c: b0 12 28 91 call #0x9128 CC2500_SPI_STROBE(CCxxx0_STX); // send tx strobe and TX begins, returns to 15 or 31 when complete (depending on MCSM1) 8ea0: 7f 40 35 00 mov.b #53, r15 ;#0x0035 8ea4: b0 12 5a 8f call #0x8f5a do { CC2500_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... 8ea8: 7f 40 3d 00 mov.b #61, r15 ;#0x003d 8eac: b0 12 5a 8f call #0x8f5a if(status_2500 == 31) //fast RX mode yay 8eb0: 5f 42 12 02 mov.b &0x0212,r15 8eb4: 7f 90 1f 00 cmp.b #31, r15 ;#0x001f 8eb8: 03 24 jz $+8 ;abs 0x8ec0 break; }while((status_2500 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //(15)31 for return to TX on complete, see MCSM1 8eba: 3f b0 70 00 bit #112, r15 ;#0x0070 8ebe: f4 23 jnz $-22 ;abs 0x8ea8 } 8ec0: 3a 41 pop r10 8ec2: 3b 41 pop r11 8ec4: 30 41 ret 00008ec6 : /** Transmit a string of bytes.on the CC1100 */ void TX_1100_STRING(unsigned char *txstring, unsigned char length) { 8ec6: 0b 12 push r11 8ec8: 0a 12 push r10 8eca: 09 12 push r9 8ecc: 09 4f mov r15, r9 8ece: 4b 4e mov.b r14, r11 #ifdef FIXED_PACKET_MODE unsigned char i,pktlen = CC1100_SPI_RDREG(CCxxx0_PKTLEN); 8ed0: 7f 40 06 00 mov.b #6, r15 ;#0x0006 8ed4: b0 12 2a 90 call #0x902a 8ed8: 4a 4f mov.b r15, r10 #endif //length += 3; do{ CC1100_SPI_STROBE(CCxxx0_SIDLE);//Idle 8eda: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8ede: b0 12 92 8f call #0x8f92 }while((status_1100 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle 8ee2: 5f 42 05 02 mov.b &0x0205,r15 8ee6: 3f b0 70 00 bit #112, r15 ;#0x0070 8eea: f7 23 jnz $-16 ;abs 0x8eda { if(i < length) CC1100_SPI_WRREG(CCxxx0_TXFIFO, txstring[i]);//Write data to FIFO }*/ #ifdef FIXED_PACKET_MODE if(length > pktlen) //text string is too long for fixed packet length mode 8eec: 4a 9b cmp.b r11, r10 8eee: 17 28 jnc $+48 ;abs 0x8f1e length = pktlen; if (length == pktlen) 8ef0: 17 24 jz $+48 ;abs 0x8f20 CC1100_SPI_BURST_WRREG(CCxxx0_TXFIFO_BURST, txstring, length); else if (length < pktlen) 8ef2: 4b 9a cmp.b r10, r11 8ef4: 1c 28 jnc $+58 ;abs 0x8f2e } #else CC1100_SPI_BURST_WRREG(CCxxx0_TXFIFO_BURST, txstring, length); #endif CC1100_SPI_STROBE(CCxxx0_STX); // send tx strobe and TX begins, returns to 15 or 31 when complete (depending on MCSM1) 8ef6: 7f 40 35 00 mov.b #53, r15 ;#0x0035 8efa: b0 12 92 8f call #0x8f92 do{ CC1100_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... 8efe: 7f 40 3d 00 mov.b #61, r15 ;#0x003d 8f02: b0 12 92 8f call #0x8f92 if(status_1100 == 31) //fast RX mode yay 8f06: 5f 42 05 02 mov.b &0x0205,r15 8f0a: 7f 90 1f 00 cmp.b #31, r15 ;#0x001f 8f0e: 03 24 jz $+8 ;abs 0x8f16 break; }while((status_1100 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //(15)31 for return to TX on complete, see MCSM1 8f10: 3f b0 70 00 bit #112, r15 ;#0x0070 8f14: f4 23 jnz $-22 ;abs 0x8efe } 8f16: 39 41 pop r9 8f18: 3a 41 pop r10 8f1a: 3b 41 pop r11 8f1c: 30 41 ret { if(i < length) CC1100_SPI_WRREG(CCxxx0_TXFIFO, txstring[i]);//Write data to FIFO }*/ #ifdef FIXED_PACKET_MODE if(length > pktlen) //text string is too long for fixed packet length mode 8f1e: 4b 4a mov.b r10, r11 length = pktlen; if (length == pktlen) CC1100_SPI_BURST_WRREG(CCxxx0_TXFIFO_BURST, txstring, length); 8f20: 4d 4b mov.b r11, r13 8f22: 0e 49 mov r9, r14 8f24: 7f 40 7f 00 mov.b #127, r15 ;#0x007f 8f28: b0 12 9c 91 call #0x919c 8f2c: e4 3f jmp $-54 ;abs 0x8ef6 { /*for(i=0; i: Strobe a command to the CC2500 */ void CC2500_SPI_STROBE(char reg) { status_2500=0; P4OUT &= ~CSn_2500; //pull CSn low to activate chip 8f5a: f2 f0 fe ff and.b #-2, &0x001d ;#0xfffe 8f5e: 1d 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 8f60: 5e 42 18 00 mov.b &0x0018,r14 8f64: 2e f2 and #4, r14 ;r2 As==10 8f66: fc 23 jnz $-6 ;abs 0x8f60 P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 8f68: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 8f6c: 1b 00 IFG2 &= ~UCB0RXIFG; 8f6e: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8f72: 03 00 UCB0TXBUF = reg; 8f74: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 8f78: 5f 42 03 00 mov.b &0x0003,r15 8f7c: 2f f2 and #4, r15 ;r2 As==10 8f7e: fc 27 jz $-6 ;abs 0x8f78 status_2500 = UCB0RXBUF; 8f80: d2 42 6e 00 mov.b &0x006e,&0x0212 8f84: 12 02 P4OUT |= CSn_2500; //pull CSn high, we're done with the transfer 8f86: d2 d3 1d 00 bis.b #1, &0x001d ;r3 As==01 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 8f8a: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 8f8e: 1b 00 } 8f90: 30 41 ret 00008f92 : Strobe a command to the CC1100 */ void CC1100_SPI_STROBE(char reg) { status_1100=0; P1OUT &= ~CSn_1100; //pull CSn low to activate chip 8f92: f2 f0 fb ff and.b #-5, &0x0021 ;#0xfffb 8f96: 21 00 while(P3IN & SOMI_1100); //wait for the CCXX good signal, wait for SOMI to drop low 8f98: 5e 42 18 00 mov.b &0x0018,r14 8f9c: 3e f0 20 00 and #32, r14 ;#0x0020 8fa0: fb 23 jnz $-8 ;abs 0x8f98 P3SEL |= UARTA0_SPI_MODULES; //this will bring the clock edge high 8fa2: f2 d0 31 00 bis.b #49, &0x001b ;#0x0031 8fa6: 1b 00 IFG2 &= ~UCA0RXIFG; 8fa8: f2 f0 fe ff and.b #-2, &0x0003 ;#0xfffe 8fac: 03 00 UCA0TXBUF = reg; 8fae: c2 4f 67 00 mov.b r15, &0x0067 while (!(IFG2 & UCA0RXIFG)); 8fb2: 5f 42 03 00 mov.b &0x0003,r15 8fb6: 1f f3 and #1, r15 ;r3 As==01 8fb8: fc 27 jz $-6 ;abs 0x8fb2 status_1100 = UCA0RXBUF; 8fba: d2 42 66 00 mov.b &0x0066,&0x0205 8fbe: 05 02 P1OUT |= CSn_1100; //pull CSn high, we're done with the transfer 8fc0: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 P3SEL &= ~UARTA0_SPI_MODULES; //take the pins back out of SPI mode 8fc4: f2 f0 ce ff and.b #-50, &0x001b ;#0xffce 8fc8: 1b 00 } 8fca: 30 41 ret 00008fcc : Read a register from the CC2500 */ char CC2500_SPI_RDREG(char reg) { unsigned char rx=0; if(reg >= 0x30) 8fcc: 7f 90 30 00 cmp.b #48, r15 ;#0x0030 8fd0: 29 38 jl $+84 ;abs 0x9024 reg |= 0xC0; 8fd2: 7f d0 c0 ff bis.b #-64, r15 ;#0xffc0 else reg |= 0x80; status_2500=0; P4OUT &= ~CSn_2500; //pull CSn low to activate chip 8fd6: f2 f0 fe ff and.b #-2, &0x001d ;#0xfffe 8fda: 1d 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 8fdc: 5e 42 18 00 mov.b &0x0018,r14 8fe0: 2e f2 and #4, r14 ;r2 As==10 8fe2: fc 23 jnz $-6 ;abs 0x8fdc P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 8fe4: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 8fe8: 1b 00 IFG2 &= ~UCB0RXIFG; 8fea: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8fee: 03 00 UCB0TXBUF = reg; 8ff0: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 8ff4: 5f 42 03 00 mov.b &0x0003,r15 8ff8: 2f f2 and #4, r15 ;r2 As==10 8ffa: fc 27 jz $-6 ;abs 0x8ff4 status_2500 = UCB0RXBUF; 8ffc: d2 42 6e 00 mov.b &0x006e,&0x0212 9000: 12 02 IFG2 &= ~UCB0RXIFG; 9002: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 9006: 03 00 UCB0TXBUF = 0; 9008: c2 43 6f 00 mov.b #0, &0x006f ;r3 As==00 while (!(IFG2 & UCB0RXIFG)); 900c: 5f 42 03 00 mov.b &0x0003,r15 9010: 2f f2 and #4, r15 ;r2 As==10 9012: fc 27 jz $-6 ;abs 0x900c rx = UCB0RXBUF; 9014: 5f 42 6e 00 mov.b &0x006e,r15 P4OUT |= CSn_2500; //pull CSn high, we're done with the transfer 9018: d2 d3 1d 00 bis.b #1, &0x001d ;r3 As==01 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 901c: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 9020: 1b 00 return rx; } 9022: 30 41 ret { unsigned char rx=0; if(reg >= 0x30) reg |= 0xC0; else reg |= 0x80; 9024: 7f d0 80 ff bis.b #-128, r15 ;#0xff80 9028: d6 3f jmp $-82 ;abs 0x8fd6 0000902a : Read a register from the CC1100 */ char CC1100_SPI_RDREG(char reg) { unsigned char rx=0; if(reg >= 0x30) 902a: 7f 90 30 00 cmp.b #48, r15 ;#0x0030 902e: 2a 38 jl $+86 ;abs 0x9084 reg |= 0xC0; 9030: 7f d0 c0 ff bis.b #-64, r15 ;#0xffc0 else reg |= 0x80; status_1100=0; P1OUT &= ~CSn_1100; //pull CSn low to activate chip 9034: f2 f0 fb ff and.b #-5, &0x0021 ;#0xfffb 9038: 21 00 while(P3IN & SOMI_1100); //wait for the CCXX good signal, wait for SOMI to drop low 903a: 5e 42 18 00 mov.b &0x0018,r14 903e: 3e f0 20 00 and #32, r14 ;#0x0020 9042: fb 23 jnz $-8 ;abs 0x903a P3SEL |= UARTA0_SPI_MODULES; //this will bring the clock edge high 9044: f2 d0 31 00 bis.b #49, &0x001b ;#0x0031 9048: 1b 00 IFG2 &= ~UCA0RXIFG; 904a: f2 f0 fe ff and.b #-2, &0x0003 ;#0xfffe 904e: 03 00 UCA0TXBUF = reg; 9050: c2 4f 67 00 mov.b r15, &0x0067 while (!(IFG2 & UCA0RXIFG)); 9054: 5f 42 03 00 mov.b &0x0003,r15 9058: 1f f3 and #1, r15 ;r3 As==01 905a: fc 27 jz $-6 ;abs 0x9054 status_1100 = UCA0RXBUF; 905c: d2 42 66 00 mov.b &0x0066,&0x0205 9060: 05 02 IFG2 &= ~UCA0RXIFG; 9062: f2 f0 fe ff and.b #-2, &0x0003 ;#0xfffe 9066: 03 00 UCA0TXBUF = 0; 9068: c2 43 67 00 mov.b #0, &0x0067 ;r3 As==00 while (!(IFG2 & UCA0RXIFG)); 906c: 5f 42 03 00 mov.b &0x0003,r15 9070: 1f f3 and #1, r15 ;r3 As==01 9072: fc 27 jz $-6 ;abs 0x906c rx = UCA0RXBUF; 9074: 5f 42 66 00 mov.b &0x0066,r15 P1OUT |= CSn_1100; //pull CSn high, we're done with the transfer 9078: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 P3SEL &= ~UARTA0_SPI_MODULES; //take the pins back out of SPI mode 907c: f2 f0 ce ff and.b #-50, &0x001b ;#0xffce 9080: 1b 00 return rx; } 9082: 30 41 ret { unsigned char rx=0; if(reg >= 0x30) reg |= 0xC0; else reg |= 0x80; 9084: 7f d0 80 ff bis.b #-128, r15 ;#0xff80 9088: d5 3f jmp $-84 ;abs 0x9034 0000908a : { unsigned char dummy; status_2500=0; P4OUT &= ~CSn_2500; //pull CSn low to activate chip 908a: f2 f0 fe ff and.b #-2, &0x001d ;#0xfffe 908e: 1d 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 9090: 5d 42 18 00 mov.b &0x0018,r13 9094: 2d f2 and #4, r13 ;r2 As==10 9096: fc 23 jnz $-6 ;abs 0x9090 P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 9098: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 909c: 1b 00 IFG2 &= ~UCB0RXIFG; 909e: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 90a2: 03 00 UCB0TXBUF = reg; 90a4: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 90a8: 5f 42 03 00 mov.b &0x0003,r15 90ac: 2f f2 and #4, r15 ;r2 As==10 90ae: fc 27 jz $-6 ;abs 0x90a8 status_2500 = UCB0RXBUF; 90b0: d2 42 6e 00 mov.b &0x006e,&0x0212 90b4: 12 02 //lil delay //delay(1); IFG2 &= ~UCB0RXIFG; 90b6: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 90ba: 03 00 UCB0TXBUF = byte; 90bc: c2 4e 6f 00 mov.b r14, &0x006f while (!(IFG2 & UCB0RXIFG)); 90c0: 5f 42 03 00 mov.b &0x0003,r15 90c4: 2f f2 and #4, r15 ;r2 As==10 90c6: fc 27 jz $-6 ;abs 0x90c0 dummy = UCB0RXBUF; 90c8: 5f 42 6e 00 mov.b &0x006e,r15 P4OUT |= CSn_2500; //pull CSn high, we're done with the transfer 90cc: d2 d3 1d 00 bis.b #1, &0x001d ;r3 As==01 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 90d0: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 90d4: 1b 00 } 90d6: 30 41 ret 000090d8 : { unsigned char dummy; status_1100=0; P1OUT &= ~CSn_1100; //pull CSn low to activate chip 90d8: f2 f0 fb ff and.b #-5, &0x0021 ;#0xfffb 90dc: 21 00 while(P3IN & SOMI_1100); //wait for the CCXX good signal, wait for SOMI to drop low 90de: 5d 42 18 00 mov.b &0x0018,r13 90e2: 3d f0 20 00 and #32, r13 ;#0x0020 90e6: fb 23 jnz $-8 ;abs 0x90de P3SEL |= UARTA0_SPI_MODULES; //this will bring the clock edge high 90e8: f2 d0 31 00 bis.b #49, &0x001b ;#0x0031 90ec: 1b 00 IFG2 &= ~UCA0RXIFG; 90ee: f2 f0 fe ff and.b #-2, &0x0003 ;#0xfffe 90f2: 03 00 UCA0TXBUF = reg; 90f4: c2 4f 67 00 mov.b r15, &0x0067 while (!(IFG2 & UCA0RXIFG)); 90f8: 5f 42 03 00 mov.b &0x0003,r15 90fc: 1f f3 and #1, r15 ;r3 As==01 90fe: fc 27 jz $-6 ;abs 0x90f8 status_1100 = UCA0RXBUF; 9100: d2 42 66 00 mov.b &0x0066,&0x0205 9104: 05 02 //lil delay //delay(1); IFG2 &= ~UCA0RXIFG; 9106: f2 f0 fe ff and.b #-2, &0x0003 ;#0xfffe 910a: 03 00 UCA0TXBUF = byte; 910c: c2 4e 67 00 mov.b r14, &0x0067 while (!(IFG2 & UCA0RXIFG)); 9110: 5f 42 03 00 mov.b &0x0003,r15 9114: 1f f3 and #1, r15 ;r3 As==01 9116: fc 27 jz $-6 ;abs 0x9110 dummy = UCA0RXBUF; 9118: 5f 42 66 00 mov.b &0x0066,r15 P1OUT |= CSn_1100; //pull CSn high, we're done with the transfer 911c: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 P3SEL &= ~UARTA0_SPI_MODULES; //take the pins back out of SPI mode 9120: f2 f0 ce ff and.b #-50, &0x001b ;#0xffce 9124: 1b 00 } 9126: 30 41 ret 00009128 : { unsigned char dummy; unsigned int index; status_2500=0; P4OUT &= ~CSn_2500; //pull CSn low to activate chip 9128: f2 f0 fe ff and.b #-2, &0x001d ;#0xfffe 912c: 1d 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 912e: 5c 42 18 00 mov.b &0x0018,r12 9132: 2c f2 and #4, r12 ;r2 As==10 9134: fc 23 jnz $-6 ;abs 0x912e P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 9136: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 913a: 1b 00 IFG2 &= ~UCB0RXIFG; 913c: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 9140: 03 00 UCB0TXBUF = reg; 9142: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 9146: 5f 42 03 00 mov.b &0x0003,r15 914a: 2f f2 and #4, r15 ;r2 As==10 914c: fc 27 jz $-6 ;abs 0x9146 status_2500 = UCB0RXBUF; 914e: d2 42 6e 00 mov.b &0x006e,&0x0212 9152: 12 02 //write out length IFG2 &= ~UCB0RXIFG; 9154: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 9158: 03 00 UCB0TXBUF = length; 915a: c2 4d 6f 00 mov.b r13, &0x006f while (!(IFG2 & UCB0RXIFG)); 915e: 5f 42 03 00 mov.b &0x0003,r15 9162: 2f f2 and #4, r15 ;r2 As==10 9164: fc 27 jz $-6 ;abs 0x915e dummy = UCB0RXBUF; 9166: 5f 42 6e 00 mov.b &0x006e,r15 for(index = 0; index < length; index++) 916a: 8d 11 sxt r13 916c: 11 24 jz $+36 ;abs 0x9190 916e: 0c 43 clr r12 { IFG2 &= ~UCB0RXIFG; 9170: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 9174: 03 00 } /** Write a register from the CC2500 */ void CC2500_SPI_BURST_WRREG(char reg, char *buf, char length) 9176: 0f 4e mov r14, r15 9178: 0f 5c add r12, r15 for(index = 0; index < length; index++) { IFG2 &= ~UCB0RXIFG; UCB0TXBUF = buf[index]; 917a: e2 4f 6f 00 mov.b @r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 917e: 5f 42 03 00 mov.b &0x0003,r15 9182: 2f f2 and #4, r15 ;r2 As==10 9184: fc 27 jz $-6 ;abs 0x917e dummy = UCB0RXBUF; 9186: 5f 42 6e 00 mov.b &0x006e,r15 UCB0TXBUF = length; while (!(IFG2 & UCB0RXIFG)); dummy = UCB0RXBUF; for(index = 0; index < length; index++) 918a: 1c 53 inc r12 918c: 0c 9d cmp r13, r12 918e: f0 2b jnc $-30 ;abs 0x9170 UCB0TXBUF = buf[index]; while (!(IFG2 & UCB0RXIFG)); dummy = UCB0RXBUF; } P4OUT |= CSn_2500; //pull CSn high, we're done with the transfer 9190: d2 d3 1d 00 bis.b #1, &0x001d ;r3 As==01 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 9194: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 9198: 1b 00 } 919a: 30 41 ret 0000919c : { unsigned char dummy; unsigned int index; status_1100=0; P1OUT &= ~CSn_1100; //pull CSn low to activate chip 919c: f2 f0 fb ff and.b #-5, &0x0021 ;#0xfffb 91a0: 21 00 while(P3IN & SOMI_1100); //wait for the CCXX good signal, wait for SOMI to drop low 91a2: 5c 42 18 00 mov.b &0x0018,r12 91a6: 3c f0 20 00 and #32, r12 ;#0x0020 91aa: fb 23 jnz $-8 ;abs 0x91a2 P3SEL |= UARTA0_SPI_MODULES; //this will bring the clock edge high 91ac: f2 d0 31 00 bis.b #49, &0x001b ;#0x0031 91b0: 1b 00 IFG2 &= ~UCA0RXIFG; 91b2: f2 f0 fe ff and.b #-2, &0x0003 ;#0xfffe 91b6: 03 00 UCA0TXBUF = reg; 91b8: c2 4f 67 00 mov.b r15, &0x0067 while (!(IFG2 & UCA0RXIFG)); 91bc: 5f 42 03 00 mov.b &0x0003,r15 91c0: 1f f3 and #1, r15 ;r3 As==01 91c2: fc 27 jz $-6 ;abs 0x91bc status_1100 = UCA0RXBUF; 91c4: d2 42 66 00 mov.b &0x0066,&0x0205 91c8: 05 02 UCA0TXBUF = length; while (!(IFG2 & UCA0RXIFG)); dummy = UCA0RXBUF; #endif for(index = 0; index < length; index++) 91ca: 8d 11 sxt r13 91cc: 11 24 jz $+36 ;abs 0x91f0 91ce: 0c 43 clr r12 { IFG2 &= ~UCA0RXIFG; 91d0: f2 f0 fe ff and.b #-2, &0x0003 ;#0xfffe 91d4: 03 00 } /** Write a register from the CC1100 */ void CC1100_SPI_BURST_WRREG(char reg, char *buf, char length) 91d6: 0f 4e mov r14, r15 91d8: 0f 5c add r12, r15 #endif for(index = 0; index < length; index++) { IFG2 &= ~UCA0RXIFG; UCA0TXBUF = buf[index]; 91da: e2 4f 67 00 mov.b @r15, &0x0067 while (!(IFG2 & UCA0RXIFG)); 91de: 5f 42 03 00 mov.b &0x0003,r15 91e2: 1f f3 and #1, r15 ;r3 As==01 91e4: fc 27 jz $-6 ;abs 0x91de dummy = UCA0RXBUF; 91e6: 5f 42 66 00 mov.b &0x0066,r15 UCA0TXBUF = length; while (!(IFG2 & UCA0RXIFG)); dummy = UCA0RXBUF; #endif for(index = 0; index < length; index++) 91ea: 1c 53 inc r12 91ec: 0c 9d cmp r13, r12 91ee: f0 2b jnc $-30 ;abs 0x91d0 UCA0TXBUF = buf[index]; while (!(IFG2 & UCA0RXIFG)); dummy = UCA0RXBUF; } P1OUT |= CSn_1100; //pull CSn high, we're done with the transfer 91f0: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 P3SEL &= ~UARTA0_SPI_MODULES; //take the pins back out of SPI mode 91f4: f2 f0 ce ff and.b #-50, &0x001b ;#0xffce 91f8: 1b 00 } 91fa: 30 41 ret 000091fc <__udivhi3>: 91fc: 7c 40 10 00 mov.b #16, r12 ;#0x0010 9200: 0d 4e mov r14, r13 9202: 0e 43 clr r14 9204: 0f 5f rla r15 9206: 0e 6e rlc r14 9208: 0e 9d cmp r13, r14 920a: 02 28 jnc $+6 ;abs 0x9210 920c: 0e 8d sub r13, r14 920e: 1f d3 bis #1, r15 ;r3 As==01 9210: 1c 83 dec r12 9212: f8 23 jnz $-14 ;abs 0x9204 9214: 30 41 ret 00009216 <__umodhi3>: 9216: b0 12 fc 91 call #0x91fc 921a: 0f 4e mov r14, r15 921c: 30 41 ret 0000921e <__udivsi3>: 921e: 0b 12 push r11 9220: 0a 12 push r10 9222: 09 12 push r9 9224: 79 40 20 00 mov.b #32, r9 ;#0x0020 9228: 0a 4c mov r12, r10 922a: 0b 4d mov r13, r11 922c: 0c 43 clr r12 922e: 0d 43 clr r13 9230: 0e 5e rla r14 9232: 0f 6f rlc r15 9234: 0c 6c rlc r12 9236: 0d 6d rlc r13 9238: 0d 9b cmp r11, r13 923a: 06 28 jnc $+14 ;abs 0x9248 923c: 02 20 jnz $+6 ;abs 0x9242 923e: 0c 9a cmp r10, r12 9240: 03 28 jnc $+8 ;abs 0x9248 9242: 0c 8a sub r10, r12 9244: 0d 7b subc r11, r13 9246: 1e d3 bis #1, r14 ;r3 As==01 9248: 19 83 dec r9 924a: f2 23 jnz $-26 ;abs 0x9230 924c: 39 41 pop r9 924e: 3a 41 pop r10 9250: 3b 41 pop r11 9252: 30 41 ret 00009254 <__umodsi3>: 9254: b0 12 1e 92 call #0x921e 9258: 0e 4c mov r12, r14 925a: 0f 4d mov r13, r15 925c: 30 41 ret 0000925e : 925e: 6d 4f mov.b @r15, r13 9260: 4d 9e cmp.b r14, r13 9262: 05 24 jz $+12 ;abs 0x926e 9264: 4d 93 tst.b r13 9266: 02 24 jz $+6 ;abs 0x926c 9268: 1f 53 inc r15 926a: f9 3f jmp $-12 ;abs 0x925e 926c: 0f 43 clr r15 926e: 30 41 ret 00009270 : 9270: 0b 12 push r11 9272: 0d 93 tst r13 9274: 0a 24 jz $+22 ;abs 0x928a 9276: 7b 4f mov.b @r15+, r11 9278: 7c 4e mov.b @r14+, r12 927a: 4b 9c cmp.b r12, r11 927c: 04 24 jz $+10 ;abs 0x9286 927e: 4f 4b mov.b r11, r15 9280: 4e 4c mov.b r12, r14 9282: 0f 8e sub r14, r15 9284: 03 3c jmp $+8 ;abs 0x928c 9286: 3d 53 add #-1, r13 ;r3 As==11 9288: f4 3f jmp $-22 ;abs 0x9272 928a: 0f 43 clr r15 928c: 3b 41 pop r11 928e: 30 41 ret 00009290 : 9290: 0b 12 push r11 9292: 0a 12 push r10 9294: 09 12 push r9 9296: 08 12 push r8 9298: 3d 90 06 00 cmp #6, r13 ;#0x0006 929c: 09 2c jc $+20 ;abs 0x92b0 929e: 0c 4f mov r15, r12 92a0: 04 3c jmp $+10 ;abs 0x92aa 92a2: cc 4e 00 00 mov.b r14, 0(r12) ;0x0000(r12) 92a6: 1c 53 inc r12 92a8: 3d 53 add #-1, r13 ;r3 As==11 92aa: 0d 93 tst r13 92ac: fa 23 jnz $-10 ;abs 0x92a2 92ae: 20 3c jmp $+66 ;abs 0x92f0 92b0: 4e 4e mov.b r14, r14 92b2: 4b 4e mov.b r14, r11 92b4: 0b 93 tst r11 92b6: 03 24 jz $+8 ;abs 0x92be 92b8: 0c 4b mov r11, r12 92ba: 8c 10 swpb r12 92bc: 0b dc bis r12, r11 92be: 1f b3 bit #1, r15 ;r3 As==01 92c0: 06 24 jz $+14 ;abs 0x92ce 92c2: 3d 53 add #-1, r13 ;r3 As==11 92c4: cf 4e 00 00 mov.b r14, 0(r15) ;0x0000(r15) 92c8: 09 4f mov r15, r9 92ca: 19 53 inc r9 92cc: 01 3c jmp $+4 ;abs 0x92d0 92ce: 09 4f mov r15, r9 92d0: 0c 4d mov r13, r12 92d2: 12 c3 clrc 92d4: 0c 10 rrc r12 92d6: 0a 49 mov r9, r10 92d8: 08 4c mov r12, r8 92da: 8a 4b 00 00 mov r11, 0(r10) ;0x0000(r10) 92de: 2a 53 incd r10 92e0: 38 53 add #-1, r8 ;r3 As==11 92e2: fb 23 jnz $-8 ;abs 0x92da 92e4: 0c 5c rla r12 92e6: 0c 59 add r9, r12 92e8: 1d f3 and #1, r13 ;r3 As==01 92ea: 02 24 jz $+6 ;abs 0x92f0 92ec: cc 4e 00 00 mov.b r14, 0(r12) ;0x0000(r12) 92f0: 38 41 pop r8 92f2: 39 41 pop r9 92f4: 3a 41 pop r10 92f6: 3b 41 pop r11 92f8: 30 41 ret 000092fa : 92fa: 0b 12 push r11 92fc: 0a 12 push r10 92fe: 09 12 push r9 9300: 08 12 push r8 9302: 07 12 push r7 9304: 0b 4f mov r15, r11 9306: 69 4e mov.b @r14, r9 9308: 49 93 tst.b r9 930a: 1b 24 jz $+56 ;abs 0x9342 930c: 0a 4e mov r14, r10 930e: 1a 53 inc r10 9310: 0d 4e mov r14, r13 9312: 1d 53 inc r13 9314: cd 93 00 00 tst.b 0(r13) ;0x0000(r13) 9318: fc 23 jnz $-6 ;abs 0x9312 931a: 07 4d mov r13, r7 931c: 07 8a sub r10, r7 931e: 01 3c jmp $+4 ;abs 0x9322 9320: 0b 48 mov r8, r11 9322: 6f 4b mov.b @r11, r15 9324: 4f 93 tst.b r15 9326: 0c 24 jz $+26 ;abs 0x9340 9328: 08 4b mov r11, r8 932a: 18 53 inc r8 932c: 4f 99 cmp.b r9, r15 932e: f8 23 jnz $-14 ;abs 0x9320 9330: 0d 47 mov r7, r13 9332: 0e 4a mov r10, r14 9334: 0f 48 mov r8, r15 9336: b0 12 cc 9c call #0x9ccc 933a: 0f 93 tst r15 933c: f1 23 jnz $-28 ;abs 0x9320 933e: 01 3c jmp $+4 ;abs 0x9342 9340: 0b 43 clr r11 9342: 0f 4b mov r11, r15 9344: 37 41 pop r7 9346: 38 41 pop r8 9348: 39 41 pop r9 934a: 3a 41 pop r10 934c: 3b 41 pop r11 934e: 30 41 ret 00009350 : 9350: 0b 12 push r11 9352: 0e 4f mov r15, r14 9354: 01 3c jmp $+4 ;abs 0x9358 9356: 1e 53 inc r14 9358: 6f 4e mov.b @r14, r15 935a: 7f 90 20 00 cmp.b #32, r15 ;#0x0020 935e: fb 27 jz $-8 ;abs 0x9356 9360: 7f 90 09 00 cmp.b #9, r15 ;#0x0009 9364: f8 27 jz $-14 ;abs 0x9356 9366: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a 936a: f5 27 jz $-20 ;abs 0x9356 936c: 7f 90 0c 00 cmp.b #12, r15 ;#0x000c 9370: f2 27 jz $-26 ;abs 0x9356 9372: 7f 90 0d 00 cmp.b #13, r15 ;#0x000d 9376: ef 27 jz $-32 ;abs 0x9356 9378: 7f 90 0b 00 cmp.b #11, r15 ;#0x000b 937c: ec 27 jz $-38 ;abs 0x9356 937e: 7f 90 2d 00 cmp.b #45, r15 ;#0x002d 9382: 03 20 jnz $+8 ;abs 0x938a 9384: 1e 53 inc r14 9386: 1b 43 mov #1, r11 ;r3 As==01 9388: 05 3c jmp $+12 ;abs 0x9394 938a: 7f 90 2b 00 cmp.b #43, r15 ;#0x002b 938e: 01 20 jnz $+4 ;abs 0x9392 9390: 1e 53 inc r14 9392: 0b 43 clr r11 9394: 6f 4e mov.b @r14, r15 9396: 8f 11 sxt r15 9398: 3f 50 d0 ff add #-48, r15 ;#0xffd0 939c: 3f 90 0a 00 cmp #10, r15 ;#0x000a 93a0: 19 2c jc $+52 ;abs 0x93d4 93a2: 0d 43 clr r13 93a4: 7c 4e mov.b @r14+, r12 93a6: 8c 11 sxt r12 93a8: 0f 4c mov r12, r15 93aa: 3f 50 d0 ff add #-48, r15 ;#0xffd0 93ae: 0f 5d add r13, r15 93b0: 6d 4e mov.b @r14, r13 93b2: 8d 11 sxt r13 93b4: 3d 50 d0 ff add #-48, r13 ;#0xffd0 93b8: 3d 90 0a 00 cmp #10, r13 ;#0x000a 93bc: 06 2c jc $+14 ;abs 0x93ca 93be: 0f 5f rla r15 93c0: 0d 4f mov r15, r13 93c2: 0d 5d rla r13 93c4: 0d 5d rla r13 93c6: 0d 5f add r15, r13 93c8: ed 3f jmp $-36 ;abs 0x93a4 93ca: 0b 93 tst r11 93cc: 04 24 jz $+10 ;abs 0x93d6 93ce: 3f e3 inv r15 93d0: 1f 53 inc r15 93d2: 01 3c jmp $+4 ;abs 0x93d6 93d4: 0f 43 clr r15 93d6: 3b 41 pop r11 93d8: 30 41 ret 000093da : 93da: 1e 42 02 02 mov &0x0202,r14 93de: 1e 93 cmp #1, r14 ;r3 As==01 93e0: 0b 38 jl $+24 ;abs 0x93f8 93e2: 1d 42 00 02 mov &0x0200,r13 93e6: cd 4f 00 00 mov.b r15, 0(r13) ;0x0000(r13) 93ea: 1d 53 inc r13 93ec: 82 4d 00 02 mov r13, &0x0200 93f0: 3e 53 add #-1, r14 ;r3 As==11 93f2: 82 4e 02 02 mov r14, &0x0202 93f6: 30 41 ret 93f8: 3f 43 mov #-1, r15 ;r3 As==11 93fa: 30 41 ret 000093fc : 93fc: 0b 12 push r11 93fe: 0a 12 push r10 9400: 21 83 decd r1 9402: 81 4e 00 00 mov r14, 0(r1) ;0x0000(r1) 9406: 1a 42 00 02 mov &0x0200,r10 940a: 1b 42 02 02 mov &0x0202,r11 940e: 0d 4e mov r14, r13 9410: 0e 4f mov r15, r14 9412: 3f 40 da 93 mov #-27686,r15 ;#0x93da 9416: b0 12 2e 96 call #0x962e 941a: 0f 9b cmp r11, r15 941c: 05 38 jl $+12 ;abs 0x9428 941e: 0e 4a mov r10, r14 9420: 0e 5b add r11, r14 9422: ce 43 ff ff mov.b #0, -1(r14) ;r3 As==00, 0xffff(r14) 9426: 04 3c jmp $+10 ;abs 0x9430 9428: 1e 42 00 02 mov &0x0200,r14 942c: ce 43 00 00 mov.b #0, 0(r14) ;r3 As==00, 0x0000(r14) 9430: 21 53 incd r1 9432: 3a 41 pop r10 9434: 3b 41 pop r11 9436: 30 41 ret 00009438 : 9438: 92 41 02 00 mov 2(r1), &0x0200 ;0x0002(r1) 943c: 00 02 943e: b2 40 ff 7f mov #32767, &0x0202 ;#0x7fff 9442: 02 02 9444: 0e 41 mov r1, r14 9446: 3e 50 06 00 add #6, r14 ;#0x0006 944a: 1f 41 04 00 mov 4(r1), r15 ;0x0004(r1) 944e: b0 12 fc 93 call #0x93fc 9452: 30 41 ret 00009454 : 9454: 92 41 02 00 mov 2(r1), &0x0200 ;0x0002(r1) 9458: 00 02 945a: 92 41 04 00 mov 4(r1), &0x0202 ;0x0004(r1) 945e: 02 02 9460: 0e 41 mov r1, r14 9462: 3e 52 add #8, r14 ;r2 As==11 9464: 1f 41 06 00 mov 6(r1), r15 ;0x0006(r1) 9468: b0 12 fc 93 call #0x93fc 946c: 30 41 ret 0000946e : 946e: 0c 4e mov r14, r12 9470: 82 4f 00 02 mov r15, &0x0200 9474: b2 40 ff 7f mov #32767, &0x0202 ;#0x7fff 9478: 02 02 947a: 0e 4d mov r13, r14 947c: 0f 4c mov r12, r15 947e: b0 12 fc 93 call #0x93fc 9482: 30 41 ret 00009484 : 9484: 82 4f 00 02 mov r15, &0x0200 9488: 82 4e 02 02 mov r14, &0x0202 948c: 0e 4c mov r12, r14 948e: 0f 4d mov r13, r15 9490: b0 12 fc 93 call #0x93fc 9494: 30 41 ret 00009496 : 9496: 0b 12 push r11 9498: 0a 12 push r10 949a: 09 12 push r9 949c: 08 12 push r8 949e: 07 12 push r7 94a0: 06 12 push r6 94a2: 05 12 push r5 94a4: 04 12 push r4 94a6: 31 82 sub #8, r1 ;r2 As==11 94a8: 08 4f mov r15, r8 94aa: 81 4e 04 00 mov r14, 4(r1) ;0x0004(r1) 94ae: 09 4d mov r13, r9 94b0: 1f 41 1a 00 mov 26(r1), r15 ;0x001a(r1) 94b4: 1d 41 1c 00 mov 28(r1), r13 ;0x001c(r1) 94b8: 4c 4d mov.b r13, r12 94ba: 04 4d mov r13, r4 94bc: 84 10 swpb r4 94be: 45 44 mov.b r4, r5 94c0: 4e 4f mov.b r15, r14 94c2: 7e b0 40 00 bit.b #64, r14 ;#0x0040 94c6: 11 24 jz $+36 ;abs 0x94ea 94c8: f1 40 30 00 mov.b #48, 0(r1) ;#0x0030, 0x0000(r1) 94cc: 00 00 94ce: 0e 4f mov r15, r14 94d0: 8e 10 swpb r14 94d2: 5e f3 and.b #1, r14 ;r3 As==01 94d4: 03 24 jz $+8 ;abs 0x94dc 94d6: 7e 40 58 00 mov.b #88, r14 ;#0x0058 94da: 02 3c jmp $+6 ;abs 0x94e0 94dc: 7e 40 78 00 mov.b #120, r14 ;#0x0078 94e0: c1 4e 01 00 mov.b r14, 1(r1) ;0x0001(r1) 94e4: 0c 41 mov r1, r12 94e6: 2c 53 incd r12 94e8: 0f 3c jmp $+32 ;abs 0x9508 94ea: 7e f0 20 00 and.b #32, r14 ;#0x0020 94ee: 04 24 jz $+10 ;abs 0x94f8 94f0: f1 40 30 00 mov.b #48, 0(r1) ;#0x0030, 0x0000(r1) 94f4: 00 00 94f6: 04 3c jmp $+10 ;abs 0x9500 94f8: 4c 93 tst.b r12 94fa: 05 24 jz $+12 ;abs 0x9506 94fc: c1 4d 00 00 mov.b r13, 0(r1) ;0x0000(r1) 9500: 0c 41 mov r1, r12 9502: 1c 53 inc r12 9504: 01 3c jmp $+4 ;abs 0x9508 9506: 0c 41 mov r1, r12 9508: 0a 4c mov r12, r10 950a: 8c 10 swpb r12 950c: 8c 11 sxt r12 950e: 8c 10 swpb r12 9510: 8c 11 sxt r12 9512: 0b 4c mov r12, r11 9514: 06 41 mov r1, r6 9516: 0c 41 mov r1, r12 9518: 8c 10 swpb r12 951a: 8c 11 sxt r12 951c: 8c 10 swpb r12 951e: 8c 11 sxt r12 9520: 07 4c mov r12, r7 9522: 0a 86 sub r6, r10 9524: 0b 77 subc r7, r11 9526: 0e 4f mov r15, r14 9528: 8e 10 swpb r14 952a: c1 4e 02 00 mov.b r14, 2(r1) ;0x0002(r1) 952e: 6e f2 and.b #4, r14 ;r2 As==10 9530: 02 24 jz $+6 ;abs 0x9536 9532: 07 45 mov r5, r7 9534: 01 3c jmp $+4 ;abs 0x9538 9536: 37 43 mov #-1, r7 ;r3 As==11 9538: 4f 4f mov.b r15, r15 953a: 7f b0 10 00 bit.b #16, r15 ;#0x0010 953e: 3c 20 jnz $+122 ;abs 0x95b8 9540: 1d 41 04 00 mov 4(r1), r13 ;0x0004(r1) 9544: 3d 53 add #-1, r13 ;r3 As==11 9546: 1d 53 inc r13 9548: cd 93 00 00 tst.b 0(r13) ;0x0000(r13) 954c: fc 23 jnz $-6 ;abs 0x9546 954e: 1d 81 04 00 sub 4(r1), r13 ;0x0004(r1) 9552: 09 9a cmp r10, r9 9554: 02 28 jnc $+6 ;abs 0x955a 9556: 09 8a sub r10, r9 9558: 01 3c jmp $+4 ;abs 0x955c 955a: 09 43 clr r9 955c: e1 b3 02 00 bit.b #2, 2(r1) ;r3 As==10, 0x0002(r1) 9560: 05 24 jz $+12 ;abs 0x956c 9562: 09 95 cmp r5, r9 9564: 02 28 jnc $+6 ;abs 0x956a 9566: 09 85 sub r5, r9 9568: 01 3c jmp $+4 ;abs 0x956c 956a: 09 43 clr r9 956c: 05 4d mov r13, r5 956e: 07 9d cmp r13, r7 9570: 01 2c jc $+4 ;abs 0x9574 9572: 05 47 mov r7, r5 9574: 4f 93 tst.b r15 9576: 0d 38 jl $+28 ;abs 0x9592 9578: f1 40 20 00 mov.b #32, 6(r1) ;#0x0020, 0x0006(r1) 957c: 06 00 957e: 06 43 clr r6 9580: 0b 43 clr r11 9582: 0e 3c jmp $+30 ;abs 0x95a0 9584: 0f 41 mov r1, r15 9586: 0f 56 add r6, r15 9588: 6f 4f mov.b @r15, r15 958a: 8f 11 sxt r15 958c: 16 53 inc r6 958e: 88 12 call r8 9590: 01 3c jmp $+4 ;abs 0x9594 9592: 06 43 clr r6 9594: 06 9a cmp r10, r6 9596: f6 3b jl $-18 ;abs 0x9584 9598: 0b 4a mov r10, r11 959a: f1 40 30 00 mov.b #48, 6(r1) ;#0x0030, 0x0006(r1) 959e: 06 00 95a0: 05 8b sub r11, r5 95a2: 05 3c jmp $+12 ;abs 0x95ae 95a4: 5f 41 06 00 mov.b 6(r1), r15 ;0x0006(r1) 95a8: 8f 11 sxt r15 95aa: 88 12 call r8 95ac: 1b 53 inc r11 95ae: 0f 45 mov r5, r15 95b0: 0f 5b add r11, r15 95b2: 0f 99 cmp r9, r15 95b4: f7 2b jnc $-16 ;abs 0x95a4 95b6: 0a 3c jmp $+22 ;abs 0x95cc 95b8: 06 43 clr r6 95ba: 0b 43 clr r11 95bc: 07 3c jmp $+16 ;abs 0x95cc 95be: 1b 53 inc r11 95c0: 0f 41 mov r1, r15 95c2: 0f 56 add r6, r15 95c4: 6f 4f mov.b @r15, r15 95c6: 8f 11 sxt r15 95c8: 16 53 inc r6 95ca: 88 12 call r8 95cc: 06 9a cmp r10, r6 95ce: f7 3b jl $-16 ;abs 0x95be 95d0: e1 b3 02 00 bit.b #2, 2(r1) ;r3 As==10, 0x0002(r1) 95d4: 02 24 jz $+6 ;abs 0x95da 95d6: 4a 44 mov.b r4, r10 95d8: 08 3c jmp $+18 ;abs 0x95ea 95da: 1a 41 04 00 mov 4(r1), r10 ;0x0004(r1) 95de: 0a 8b sub r11, r10 95e0: 0d 3c jmp $+28 ;abs 0x95fc 95e2: 3f 40 30 00 mov #48, r15 ;#0x0030 95e6: 88 12 call r8 95e8: 7a 53 add.b #-1, r10 ;r3 As==11 95ea: 4a 93 tst.b r10 95ec: fa 23 jnz $-10 ;abs 0x95e2 95ee: 44 44 mov.b r4, r4 95f0: 0b 54 add r4, r11 95f2: f3 3f jmp $-24 ;abs 0x95da 95f4: 37 53 add #-1, r7 ;r3 As==11 95f6: 8f 11 sxt r15 95f8: 88 12 call r8 95fa: 1b 53 inc r11 95fc: 0f 4a mov r10, r15 95fe: 0f 5b add r11, r15 9600: 6f 4f mov.b @r15, r15 9602: 4f 93 tst.b r15 9604: 07 24 jz $+16 ;abs 0x9614 9606: 07 93 tst r7 9608: f5 23 jnz $-20 ;abs 0x95f4 960a: 04 3c jmp $+10 ;abs 0x9614 960c: 3f 40 20 00 mov #32, r15 ;#0x0020 9610: 88 12 call r8 9612: 1b 53 inc r11 9614: 0b 99 cmp r9, r11 9616: fa 2b jnc $-10 ;abs 0x960c 9618: 0f 4b mov r11, r15 961a: 31 52 add #8, r1 ;r2 As==11 961c: 34 41 pop r4 961e: 35 41 pop r5 9620: 36 41 pop r6 9622: 37 41 pop r7 9624: 38 41 pop r8 9626: 39 41 pop r9 9628: 3a 41 pop r10 962a: 3b 41 pop r11 962c: 30 41 ret 0000962e : 962e: 0b 12 push r11 9630: 0a 12 push r10 9632: 09 12 push r9 9634: 08 12 push r8 9636: 07 12 push r7 9638: 06 12 push r6 963a: 05 12 push r5 963c: 04 12 push r4 963e: 31 50 b6 ff add #-74, r1 ;#0xffb6 9642: 81 4f 3a 00 mov r15, 58(r1) ;0x003a(r1) 9646: 06 4e mov r14, r6 9648: 05 4d mov r13, r5 964a: 81 4e 3e 00 mov r14, 62(r1) ;0x003e(r1) 964e: c1 43 2f 00 mov.b #0, 47(r1) ;r3 As==00, 0x002f(r1) 9652: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 9656: c1 43 2e 00 mov.b #0, 46(r1) ;r3 As==00, 0x002e(r1) 965a: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) 965e: 81 43 30 00 mov #0, 48(r1) ;r3 As==00, 0x0030(r1) 9662: 81 43 26 00 mov #0, 38(r1) ;r3 As==00, 0x0026(r1) 9666: 07 43 clr r7 9668: 81 43 2c 00 mov #0, 44(r1) ;r3 As==00, 0x002c(r1) 966c: 0e 41 mov r1, r14 966e: 3e 50 1c 00 add #28, r14 ;#0x001c 9672: 81 4e 1c 00 mov r14, 28(r1) ;0x001c(r1) 9676: 30 40 a8 9c br #0x9ca8 967a: 0f 46 mov r6, r15 967c: 1f 53 inc r15 967e: 81 4f 40 00 mov r15, 64(r1) ;0x0040(r1) 9682: 07 93 tst r7 9684: 1e 20 jnz $+62 ;abs 0x96c2 9686: 7e 90 25 00 cmp.b #37, r14 ;#0x0025 968a: 13 20 jnz $+40 ;abs 0x96b2 968c: 81 43 00 00 mov #0, 0(r1) ;r3 As==00, 0x0000(r1) 9690: 81 43 02 00 mov #0, 2(r1) ;r3 As==00, 0x0002(r1) 9694: 81 46 3e 00 mov r6, 62(r1) ;0x003e(r1) 9698: c1 43 2f 00 mov.b #0, 47(r1) ;r3 As==00, 0x002f(r1) 969c: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 96a0: c1 43 2e 00 mov.b #0, 46(r1) ;r3 As==00, 0x002e(r1) 96a4: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) 96a8: 81 43 30 00 mov #0, 48(r1) ;r3 As==00, 0x0030(r1) 96ac: 30 40 9e 9c br #0x9c9e 96b0: 05 47 mov r7, r5 96b2: 8e 11 sxt r14 96b4: 0f 4e mov r14, r15 96b6: 91 12 3c 00 call 60(r1) ;0x003c(r1) 96ba: 91 53 2c 00 inc 44(r1) ;0x002c(r1) 96be: 30 40 84 9c br #0x9c84 96c2: 7e 90 63 00 cmp.b #99, r14 ;#0x0063 96c6: c5 24 jz $+396 ;abs 0x9852 96c8: 7e 90 64 00 cmp.b #100, r14 ;#0x0064 96cc: 27 34 jge $+80 ;abs 0x971c 96ce: 7e 90 30 00 cmp.b #48, r14 ;#0x0030 96d2: 94 24 jz $+298 ;abs 0x97fc 96d4: 7e 90 31 00 cmp.b #49, r14 ;#0x0031 96d8: 1a 34 jge $+54 ;abs 0x970e 96da: 7e 90 2a 00 cmp.b #42, r14 ;#0x002a 96de: 77 24 jz $+240 ;abs 0x97ce 96e0: 7e 90 2b 00 cmp.b #43, r14 ;#0x002b 96e4: 0a 34 jge $+22 ;abs 0x96fa 96e6: 7e 90 23 00 cmp.b #35, r14 ;#0x0023 96ea: 42 24 jz $+134 ;abs 0x9770 96ec: 7e 90 25 00 cmp.b #37, r14 ;#0x0025 96f0: e0 27 jz $-62 ;abs 0x96b2 96f2: 7e 90 20 00 cmp.b #32, r14 ;#0x0020 96f6: 32 20 jnz $+102 ;abs 0x975c 96f8: 56 3c jmp $+174 ;abs 0x97a6 96fa: 7e 90 2d 00 cmp.b #45, r14 ;#0x002d 96fe: 49 24 jz $+148 ;abs 0x9792 9700: 7e 90 2e 00 cmp.b #46, r14 ;#0x002e 9704: 5b 24 jz $+184 ;abs 0x97bc 9706: 7e 90 2b 00 cmp.b #43, r14 ;#0x002b 970a: 28 20 jnz $+82 ;abs 0x975c 970c: 47 3c jmp $+144 ;abs 0x979c 970e: 7e 90 3a 00 cmp.b #58, r14 ;#0x003a 9712: 8c 38 jl $+282 ;abs 0x982c 9714: 7e 90 58 00 cmp.b #88, r14 ;#0x0058 9718: 21 20 jnz $+68 ;abs 0x975c 971a: e9 3c jmp $+468 ;abs 0x98ee 971c: 7e 90 6f 00 cmp.b #111, r14 ;#0x006f 9720: 24 24 jz $+74 ;abs 0x976a 9722: 7e 90 70 00 cmp.b #112, r14 ;#0x0070 9726: 0a 34 jge $+22 ;abs 0x973c 9728: 7e 90 69 00 cmp.b #105, r14 ;#0x0069 972c: e3 24 jz $+456 ;abs 0x98f4 972e: 7e 90 6c 00 cmp.b #108, r14 ;#0x006c 9732: 22 24 jz $+70 ;abs 0x9778 9734: 7e 90 64 00 cmp.b #100, r14 ;#0x0064 9738: 11 20 jnz $+36 ;abs 0x975c 973a: dc 3c jmp $+442 ;abs 0x98f4 973c: 7e 90 73 00 cmp.b #115, r14 ;#0x0073 9740: 98 24 jz $+306 ;abs 0x9872 9742: 7e 90 74 00 cmp.b #116, r14 ;#0x0074 9746: 04 34 jge $+10 ;abs 0x9750 9748: 7e 90 70 00 cmp.b #112, r14 ;#0x0070 974c: 07 20 jnz $+16 ;abs 0x975c 974e: b8 3c jmp $+370 ;abs 0x98c0 9750: 7e 90 75 00 cmp.b #117, r14 ;#0x0075 9754: d1 24 jz $+420 ;abs 0x98f8 9756: 7e 90 78 00 cmp.b #120, r14 ;#0x0078 975a: d2 24 jz $+422 ;abs 0x9900 975c: 19 41 3e 00 mov 62(r1), r9 ;0x003e(r1) 9760: 18 41 2c 00 mov 44(r1), r8 ;0x002c(r1) 9764: 08 89 sub r9, r8 9766: 30 40 72 9c br #0x9c72 976a: b1 42 28 00 mov #8, 40(r1) ;r2 As==11, 0x0028(r1) 976e: cb 3c jmp $+408 ;abs 0x9906 9770: f1 d2 00 00 bis.b #8, 0(r1) ;r2 As==11, 0x0000(r1) 9774: 30 40 a2 9c br #0x9ca2 9778: 69 41 mov.b @r1, r9 977a: 59 f3 and.b #1, r9 ;r3 As==01 977c: 6e 41 mov.b @r1, r14 977e: 04 24 jz $+10 ;abs 0x9788 9780: 7e f0 fe ff and.b #-2, r14 ;#0xfffe 9784: 6e d3 bis.b #2, r14 ;r3 As==10 9786: 01 3c jmp $+4 ;abs 0x978a 9788: 5e d3 bis.b #1, r14 ;r3 As==01 978a: c1 4e 00 00 mov.b r14, 0(r1) ;0x0000(r1) 978e: 30 40 a2 9c br #0x9ca2 9792: f1 d0 10 00 bis.b #16, 0(r1) ;#0x0010, 0x0000(r1) 9796: 00 00 9798: 30 40 a2 9c br #0x9ca2 979c: f1 40 2b 00 mov.b #43, 2(r1) ;#0x002b, 0x0002(r1) 97a0: 02 00 97a2: 30 40 a2 9c br #0x9ca2 97a6: f1 90 2b 00 cmp.b #43, 2(r1) ;#0x002b, 0x0002(r1) 97aa: 02 00 97ac: 02 20 jnz $+6 ;abs 0x97b2 97ae: 30 40 a2 9c br #0x9ca2 97b2: f1 40 20 00 mov.b #32, 2(r1) ;#0x0020, 0x0002(r1) 97b6: 02 00 97b8: 30 40 a2 9c br #0x9ca2 97bc: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 97c0: 02 24 jz $+6 ;abs 0x97c6 97c2: 30 40 88 9c br #0x9c88 97c6: d1 43 2e 00 mov.b #1, 46(r1) ;r3 As==01, 0x002e(r1) 97ca: 30 40 a2 9c br #0x9ca2 97ce: 0e 45 mov r5, r14 97d0: 2e 53 incd r14 97d2: 2a 45 mov @r5, r10 97d4: 0a 93 tst r10 97d6: 03 38 jl $+8 ;abs 0x97de 97d8: 81 4a 26 00 mov r10, 38(r1) ;0x0026(r1) 97dc: 0d 3c jmp $+28 ;abs 0x97f8 97de: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 97e2: 02 24 jz $+6 ;abs 0x97e8 97e4: 30 40 98 9c br #0x9c98 97e8: f1 d0 10 00 bis.b #16, 0(r1) ;#0x0010, 0x0000(r1) 97ec: 00 00 97ee: 3a e3 inv r10 97f0: 81 4a 26 00 mov r10, 38(r1) ;0x0026(r1) 97f4: 91 53 26 00 inc 38(r1) ;0x0026(r1) 97f8: 05 4e mov r14, r5 97fa: 27 3c jmp $+80 ;abs 0x984a 97fc: 81 93 26 00 tst 38(r1) ;0x0026(r1) 9800: 15 20 jnz $+44 ;abs 0x982c 9802: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 9806: 12 20 jnz $+38 ;abs 0x982c 9808: 69 41 mov.b @r1, r9 980a: 79 f0 10 00 and.b #16, r9 ;#0x0010 980e: 5e 43 mov.b #1, r14 ;r3 As==01 9810: 01 24 jz $+4 ;abs 0x9814 9812: 4e 43 clr.b r14 9814: 4e 4e mov.b r14, r14 9816: 0e 11 rra r14 9818: 0e 43 clr r14 981a: 4e 10 rrc.b r14 981c: 6a 41 mov.b @r1, r10 981e: 7a f0 7f 00 and.b #127, r10 ;#0x007f 9822: 4a de bis.b r14, r10 9824: c1 4a 00 00 mov.b r10, 0(r1) ;0x0000(r1) 9828: 30 40 a2 9c br #0x9ca2 982c: 1a 41 26 00 mov 38(r1), r10 ;0x0026(r1) 9830: 0a 5a rla r10 9832: 0c 4a mov r10, r12 9834: 0c 5c rla r12 9836: 0c 5c rla r12 9838: 0a 5c add r12, r10 983a: 81 4a 26 00 mov r10, 38(r1) ;0x0026(r1) 983e: b1 50 d0 ff add #-48, 38(r1) ;#0xffd0, 0x0026(r1) 9842: 26 00 9844: 8e 11 sxt r14 9846: 81 5e 26 00 add r14, 38(r1) ;0x0026(r1) 984a: d1 43 2a 00 mov.b #1, 42(r1) ;r3 As==01, 0x002a(r1) 984e: 30 40 a2 9c br #0x9ca2 9852: 07 45 mov r5, r7 9854: 27 53 incd r7 9856: 6e 45 mov.b @r5, r14 9858: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 985c: 03 20 jnz $+8 ;abs 0x9864 985e: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 9862: 26 27 jz $-434 ;abs 0x96b0 9864: c1 4e 04 00 mov.b r14, 4(r1) ;0x0004(r1) 9868: c1 43 05 00 mov.b #0, 5(r1) ;r3 As==00, 0x0005(r1) 986c: 0e 41 mov r1, r14 986e: 2e 52 add #4, r14 ;r2 As==10 9870: 03 3c jmp $+8 ;abs 0x9878 9872: 07 45 mov r5, r7 9874: 27 53 incd r7 9876: 2e 45 mov @r5, r14 9878: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 987c: 07 24 jz $+16 ;abs 0x988c 987e: e1 d2 01 00 bis.b #4, 1(r1) ;r2 As==10, 0x0001(r1) 9882: 1f 41 26 00 mov 38(r1), r15 ;0x0026(r1) 9886: c1 4f 03 00 mov.b r15, 3(r1) ;0x0003(r1) 988a: 06 3c jmp $+14 ;abs 0x9898 988c: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 9890: 03 24 jz $+8 ;abs 0x9898 9892: 91 41 26 00 mov 38(r1), 48(r1) ;0x0026(r1), 0x0030(r1) 9896: 30 00 9898: 0e 93 tst r14 989a: 02 20 jnz $+6 ;abs 0x98a0 989c: 3e 40 d1 9e mov #-24879,r14 ;#0x9ed1 98a0: 11 12 04 00 push 4(r1) ;0x0004(r1) 98a4: 11 12 04 00 push 4(r1) ;0x0004(r1) 98a8: 1d 41 34 00 mov 52(r1), r13 ;0x0034(r1) 98ac: 1f 41 3e 00 mov 62(r1), r15 ;0x003e(r1) 98b0: b0 12 96 94 call #0x9496 98b4: 21 52 add #4, r1 ;r2 As==10 98b6: 81 5f 2c 00 add r15, 44(r1) ;0x002c(r1) 98ba: 05 47 mov r7, r5 98bc: 30 40 84 9c br #0x9c84 98c0: 07 45 mov r5, r7 98c2: 27 53 incd r7 98c4: 29 45 mov @r5, r9 98c6: 81 49 1e 00 mov r9, 30(r1) ;0x001e(r1) 98ca: 5e 43 mov.b #1, r14 ;r3 As==01 98cc: 09 93 tst r9 98ce: 01 20 jnz $+4 ;abs 0x98d2 98d0: 4e 43 clr.b r14 98d2: 4e 5e rla.b r14 98d4: 4e 5e rla.b r14 98d6: 4e 5e rla.b r14 98d8: 6a 41 mov.b @r1, r10 98da: 7a f0 f7 ff and.b #-9, r10 ;#0xfff7 98de: 4a de bis.b r14, r10 98e0: c1 4a 00 00 mov.b r10, 0(r1) ;0x0000(r1) 98e4: 05 47 mov r7, r5 98e6: b1 40 10 00 mov #16, 40(r1) ;#0x0010, 0x0028(r1) 98ea: 28 00 98ec: 53 3c jmp $+168 ;abs 0x9994 98ee: d1 d3 01 00 bis.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 98f2: 06 3c jmp $+14 ;abs 0x9900 98f4: e1 d2 00 00 bis.b #4, 0(r1) ;r2 As==10, 0x0000(r1) 98f8: b1 40 0a 00 mov #10, 40(r1) ;#0x000a, 0x0028(r1) 98fc: 28 00 98fe: 03 3c jmp $+8 ;abs 0x9906 9900: b1 40 10 00 mov #16, 40(r1) ;#0x0010, 0x0028(r1) 9904: 28 00 9906: 6b 41 mov.b @r1, r11 9908: 6b b3 bit.b #2, r11 ;r3 As==10 990a: 24 24 jz $+74 ;abs 0x9954 990c: 0c 45 mov r5, r12 990e: 3c 52 add #8, r12 ;r2 As==11 9910: 28 45 mov @r5, r8 9912: 17 45 02 00 mov 2(r5), r7 ;0x0002(r5) 9916: 16 45 04 00 mov 4(r5), r6 ;0x0004(r5) 991a: 1b 45 06 00 mov 6(r5), r11 ;0x0006(r5) 991e: 81 48 1e 00 mov r8, 30(r1) ;0x001e(r1) 9922: 81 47 20 00 mov r7, 32(r1) ;0x0020(r1) 9926: 81 46 22 00 mov r6, 34(r1) ;0x0022(r1) 992a: 81 4b 24 00 mov r11, 36(r1) ;0x0024(r1) 992e: d1 43 2b 00 mov.b #1, 43(r1) ;r3 As==01, 0x002b(r1) 9932: 08 93 tst r8 9934: 06 20 jnz $+14 ;abs 0x9942 9936: 07 93 tst r7 9938: 04 20 jnz $+10 ;abs 0x9942 993a: 06 93 tst r6 993c: 02 20 jnz $+6 ;abs 0x9942 993e: 0b 93 tst r11 9940: 02 24 jz $+6 ;abs 0x9946 9942: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 9946: 0b 5b rla r11 9948: 0b 43 clr r11 994a: 0b 6b rlc r11 994c: c1 4b 2f 00 mov.b r11, 47(r1) ;0x002f(r1) 9950: 05 4c mov r12, r5 9952: 20 3c jmp $+66 ;abs 0x9994 9954: 5b f3 and.b #1, r11 ;r3 As==01 9956: 07 45 mov r5, r7 9958: 0d 24 jz $+28 ;abs 0x9974 995a: 27 52 add #4, r7 ;r2 As==10 995c: 28 45 mov @r5, r8 995e: 1b 45 02 00 mov 2(r5), r11 ;0x0002(r5) 9962: 81 48 1e 00 mov r8, 30(r1) ;0x001e(r1) 9966: 81 4b 20 00 mov r11, 32(r1) ;0x0020(r1) 996a: d1 43 2b 00 mov.b #1, 43(r1) ;r3 As==01, 0x002b(r1) 996e: 08 93 tst r8 9970: 09 20 jnz $+20 ;abs 0x9984 9972: 06 3c jmp $+14 ;abs 0x9980 9974: 27 53 incd r7 9976: 2b 45 mov @r5, r11 9978: 81 4b 1e 00 mov r11, 30(r1) ;0x001e(r1) 997c: d1 43 2b 00 mov.b #1, 43(r1) ;r3 As==01, 0x002b(r1) 9980: 0b 93 tst r11 9982: 02 24 jz $+6 ;abs 0x9988 9984: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 9988: 0b 5b rla r11 998a: 0b 43 clr r11 998c: 0b 6b rlc r11 998e: c1 4b 2f 00 mov.b r11, 47(r1) ;0x002f(r1) 9992: 05 47 mov r7, r5 9994: f1 b2 00 00 bit.b #8, 0(r1) ;r2 As==11, 0x0000(r1) 9998: 12 24 jz $+38 ;abs 0x99be 999a: c1 93 2b 00 tst.b 43(r1) ;0x002b(r1) 999e: 0f 20 jnz $+32 ;abs 0x99be 99a0: 68 41 mov.b @r1, r8 99a2: b1 90 10 00 cmp #16, 40(r1) ;#0x0010, 0x0028(r1) 99a6: 28 00 99a8: 03 20 jnz $+8 ;abs 0x99b0 99aa: 78 d0 40 00 bis.b #64, r8 ;#0x0040 99ae: 05 3c jmp $+12 ;abs 0x99ba 99b0: b1 92 28 00 cmp #8, 40(r1) ;r2 As==11, 0x0028(r1) 99b4: 04 20 jnz $+10 ;abs 0x99be 99b6: 78 d0 20 00 bis.b #32, r8 ;#0x0020 99ba: c1 48 00 00 mov.b r8, 0(r1) ;0x0000(r1) 99be: 68 41 mov.b @r1, r8 99c0: 68 b2 bit.b #4, r8 ;r2 As==10 99c2: 30 24 jz $+98 ;abs 0x9a24 99c4: c1 93 2f 00 tst.b 47(r1) ;0x002f(r1) 99c8: 2d 24 jz $+92 ;abs 0x9a24 99ca: f1 40 2d 00 mov.b #45, 2(r1) ;#0x002d, 0x0002(r1) 99ce: 02 00 99d0: 68 b3 bit.b #2, r8 ;r3 As==10 99d2: 11 24 jz $+36 ;abs 0x99f6 99d4: b1 e3 1e 00 xor #-1, 30(r1) ;r3 As==11, 0x001e(r1) 99d8: b1 e3 20 00 xor #-1, 32(r1) ;r3 As==11, 0x0020(r1) 99dc: b1 e3 22 00 xor #-1, 34(r1) ;r3 As==11, 0x0022(r1) 99e0: b1 e3 24 00 xor #-1, 36(r1) ;r3 As==11, 0x0024(r1) 99e4: 91 53 1e 00 inc 30(r1) ;0x001e(r1) 99e8: 81 63 20 00 adc 32(r1) ;0x0020(r1) 99ec: 81 63 22 00 adc 34(r1) ;0x0022(r1) 99f0: 81 63 24 00 adc 36(r1) ;0x0024(r1) 99f4: 17 3c jmp $+48 ;abs 0x9a24 99f6: 58 b3 bit.b #1, r8 ;r3 As==01 99f8: 0f 24 jz $+32 ;abs 0x9a18 99fa: 1a 41 1e 00 mov 30(r1), r10 ;0x001e(r1) 99fe: 1b 41 20 00 mov 32(r1), r11 ;0x0020(r1) 9a02: 3a e3 inv r10 9a04: 3b e3 inv r11 9a06: 0e 4a mov r10, r14 9a08: 0f 4b mov r11, r15 9a0a: 1e 53 inc r14 9a0c: 0f 63 adc r15 9a0e: 81 4e 1e 00 mov r14, 30(r1) ;0x001e(r1) 9a12: 81 4f 20 00 mov r15, 32(r1) ;0x0020(r1) 9a16: 06 3c jmp $+14 ;abs 0x9a24 9a18: 1a 41 1e 00 mov 30(r1), r10 ;0x001e(r1) 9a1c: 3a e3 inv r10 9a1e: 1a 53 inc r10 9a20: 81 4a 1e 00 mov r10, 30(r1) ;0x001e(r1) 9a24: c1 43 1b 00 mov.b #0, 27(r1) ;r3 As==00, 0x001b(r1) 9a28: 68 b3 bit.b #2, r8 ;r3 As==10 9a2a: 6a 24 jz $+214 ;abs 0x9b00 9a2c: 16 41 1e 00 mov 30(r1), r6 ;0x001e(r1) 9a30: 91 41 20 00 mov 32(r1), 60(r1) ;0x0020(r1), 0x003c(r1) 9a34: 3c 00 9a36: 18 41 22 00 mov 34(r1), r8 ;0x0022(r1) 9a3a: 14 41 24 00 mov 36(r1), r4 ;0x0024(r1) 9a3e: 07 41 mov r1, r7 9a40: 37 50 1a 00 add #26, r7 ;#0x001a 9a44: 09 46 mov r6, r9 9a46: 91 41 28 00 mov 40(r1), 50(r1) ;0x0028(r1), 0x0032(r1) 9a4a: 32 00 9a4c: 1b 41 28 00 mov 40(r1), r11 ;0x0028(r1) 9a50: 8b 10 swpb r11 9a52: 8b 11 sxt r11 9a54: 8b 10 swpb r11 9a56: 8b 11 sxt r11 9a58: 81 4b 34 00 mov r11, 52(r1) ;0x0034(r1) 9a5c: 81 4b 36 00 mov r11, 54(r1) ;0x0036(r1) 9a60: 81 4b 38 00 mov r11, 56(r1) ;0x0038(r1) 9a64: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9a68: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9a6c: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9a70: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9a74: 0c 49 mov r9, r12 9a76: 1d 41 44 00 mov 68(r1), r13 ;0x0044(r1) 9a7a: 0e 48 mov r8, r14 9a7c: 0f 44 mov r4, r15 9a7e: b0 12 78 9d call #0x9d78 9a82: 31 52 add #8, r1 ;r2 As==11 9a84: 0b 4c mov r12, r11 9a86: 3c 90 0a 00 cmp #10, r12 ;#0x000a 9a8a: 05 34 jge $+12 ;abs 0x9a96 9a8c: 7b 50 30 00 add.b #48, r11 ;#0x0030 9a90: c7 4b 00 00 mov.b r11, 0(r7) ;0x0000(r7) 9a94: 0c 3c jmp $+26 ;abs 0x9aae 9a96: 4b 4c mov.b r12, r11 9a98: d1 b3 01 00 bit.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 9a9c: 03 24 jz $+8 ;abs 0x9aa4 9a9e: 7a 40 37 00 mov.b #55, r10 ;#0x0037 9aa2: 02 3c jmp $+6 ;abs 0x9aa8 9aa4: 7a 40 57 00 mov.b #87, r10 ;#0x0057 9aa8: 4a 5b add.b r11, r10 9aaa: c7 4a 00 00 mov.b r10, 0(r7) ;0x0000(r7) 9aae: 06 47 mov r7, r6 9ab0: 36 53 add #-1, r6 ;r3 As==11 9ab2: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9ab6: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9aba: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9abe: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9ac2: 0c 49 mov r9, r12 9ac4: 1d 41 44 00 mov 68(r1), r13 ;0x0044(r1) 9ac8: 0e 48 mov r8, r14 9aca: 0f 44 mov r4, r15 9acc: b0 12 52 9d call #0x9d52 9ad0: 31 52 add #8, r1 ;r2 As==11 9ad2: 09 4c mov r12, r9 9ad4: 81 4d 3c 00 mov r13, 60(r1) ;0x003c(r1) 9ad8: 08 4e mov r14, r8 9ada: 04 4f mov r15, r4 9adc: 37 53 add #-1, r7 ;r3 As==11 9ade: 0c 93 tst r12 9ae0: b2 23 jnz $-154 ;abs 0x9a46 9ae2: 0d 93 tst r13 9ae4: b0 23 jnz $-158 ;abs 0x9a46 9ae6: 0e 93 tst r14 9ae8: ae 23 jnz $-162 ;abs 0x9a46 9aea: 0f 93 tst r15 9aec: ac 23 jnz $-166 ;abs 0x9a46 9aee: 81 43 1e 00 mov #0, 30(r1) ;r3 As==00, 0x001e(r1) 9af2: 81 43 20 00 mov #0, 32(r1) ;r3 As==00, 0x0020(r1) 9af6: 81 43 22 00 mov #0, 34(r1) ;r3 As==00, 0x0022(r1) 9afa: 81 43 24 00 mov #0, 36(r1) ;r3 As==00, 0x0024(r1) 9afe: 6c 3c jmp $+218 ;abs 0x9bd8 9b00: 58 b3 bit.b #1, r8 ;r3 As==01 9b02: 3e 24 jz $+126 ;abs 0x9b80 9b04: 14 41 1e 00 mov 30(r1), r4 ;0x001e(r1) 9b08: 17 41 20 00 mov 32(r1), r7 ;0x0020(r1) 9b0c: 08 41 mov r1, r8 9b0e: 38 50 1a 00 add #26, r8 ;#0x001a 9b12: 19 41 28 00 mov 40(r1), r9 ;0x0028(r1) 9b16: 89 10 swpb r9 9b18: 89 11 sxt r9 9b1a: 89 10 swpb r9 9b1c: 89 11 sxt r9 9b1e: 1c 41 28 00 mov 40(r1), r12 ;0x0028(r1) 9b22: 0d 49 mov r9, r13 9b24: 0e 44 mov r4, r14 9b26: 0f 47 mov r7, r15 9b28: b0 12 54 92 call #0x9254 9b2c: 0b 4e mov r14, r11 9b2e: 3e 90 0a 00 cmp #10, r14 ;#0x000a 9b32: 05 34 jge $+12 ;abs 0x9b3e 9b34: 7b 50 30 00 add.b #48, r11 ;#0x0030 9b38: c8 4b 00 00 mov.b r11, 0(r8) ;0x0000(r8) 9b3c: 0c 3c jmp $+26 ;abs 0x9b56 9b3e: 4b 4e mov.b r14, r11 9b40: d1 b3 01 00 bit.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 9b44: 03 24 jz $+8 ;abs 0x9b4c 9b46: 7a 40 37 00 mov.b #55, r10 ;#0x0037 9b4a: 02 3c jmp $+6 ;abs 0x9b50 9b4c: 7a 40 57 00 mov.b #87, r10 ;#0x0057 9b50: 4a 5b add.b r11, r10 9b52: c8 4a 00 00 mov.b r10, 0(r8) ;0x0000(r8) 9b56: 06 48 mov r8, r6 9b58: 36 53 add #-1, r6 ;r3 As==11 9b5a: 1c 41 28 00 mov 40(r1), r12 ;0x0028(r1) 9b5e: 0d 49 mov r9, r13 9b60: 0e 44 mov r4, r14 9b62: 0f 47 mov r7, r15 9b64: b0 12 1e 92 call #0x921e 9b68: 04 4e mov r14, r4 9b6a: 07 4f mov r15, r7 9b6c: 38 53 add #-1, r8 ;r3 As==11 9b6e: 0e 93 tst r14 9b70: d0 23 jnz $-94 ;abs 0x9b12 9b72: 0f 93 tst r15 9b74: ce 23 jnz $-98 ;abs 0x9b12 9b76: 81 43 1e 00 mov #0, 30(r1) ;r3 As==00, 0x001e(r1) 9b7a: 81 43 20 00 mov #0, 32(r1) ;r3 As==00, 0x0020(r1) 9b7e: 2c 3c jmp $+90 ;abs 0x9bd8 9b80: 17 41 1e 00 mov 30(r1), r7 ;0x001e(r1) 9b84: 08 41 mov r1, r8 9b86: 38 50 1a 00 add #26, r8 ;#0x001a 9b8a: 1e 41 28 00 mov 40(r1), r14 ;0x0028(r1) 9b8e: 0f 47 mov r7, r15 9b90: b0 12 16 92 call #0x9216 9b94: 0d 4f mov r15, r13 9b96: 3f 90 0a 00 cmp #10, r15 ;#0x000a 9b9a: 05 34 jge $+12 ;abs 0x9ba6 9b9c: 7d 50 30 00 add.b #48, r13 ;#0x0030 9ba0: c8 4d 00 00 mov.b r13, 0(r8) ;0x0000(r8) 9ba4: 0c 3c jmp $+26 ;abs 0x9bbe 9ba6: 4d 4f mov.b r15, r13 9ba8: d1 b3 01 00 bit.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 9bac: 03 24 jz $+8 ;abs 0x9bb4 9bae: 7c 40 37 00 mov.b #55, r12 ;#0x0037 9bb2: 02 3c jmp $+6 ;abs 0x9bb8 9bb4: 7c 40 57 00 mov.b #87, r12 ;#0x0057 9bb8: 4c 5d add.b r13, r12 9bba: c8 4c 00 00 mov.b r12, 0(r8) ;0x0000(r8) 9bbe: 06 48 mov r8, r6 9bc0: 36 53 add #-1, r6 ;r3 As==11 9bc2: 1e 41 28 00 mov 40(r1), r14 ;0x0028(r1) 9bc6: 0f 47 mov r7, r15 9bc8: b0 12 fc 91 call #0x91fc 9bcc: 07 4f mov r15, r7 9bce: 38 53 add #-1, r8 ;r3 As==11 9bd0: 0f 93 tst r15 9bd2: db 23 jnz $-72 ;abs 0x9b8a 9bd4: 81 43 1e 00 mov #0, 30(r1) ;r3 As==00, 0x001e(r1) 9bd8: b1 90 0a 00 cmp #10, 40(r1) ;#0x000a, 0x0028(r1) 9bdc: 28 00 9bde: 02 24 jz $+6 ;abs 0x9be4 9be0: c1 43 02 00 mov.b #0, 2(r1) ;r3 As==00, 0x0002(r1) 9be4: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 9be8: 2a 24 jz $+86 ;abs 0x9c3e 9bea: 0f 41 mov r1, r15 9bec: 3f 50 1c 00 add #28, r15 ;#0x001c 9bf0: 81 4f 42 00 mov r15, 66(r1) ;0x0042(r1) 9bf4: 1a 41 1c 00 mov 28(r1), r10 ;0x001c(r1) 9bf8: 8a 10 swpb r10 9bfa: 8a 11 sxt r10 9bfc: 8a 10 swpb r10 9bfe: 8a 11 sxt r10 9c00: 81 4a 44 00 mov r10, 68(r1) ;0x0044(r1) 9c04: 81 46 46 00 mov r6, 70(r1) ;0x0046(r1) 9c08: 0a 46 mov r6, r10 9c0a: 8a 10 swpb r10 9c0c: 8a 11 sxt r10 9c0e: 8a 10 swpb r10 9c10: 8a 11 sxt r10 9c12: 81 4a 48 00 mov r10, 72(r1) ;0x0048(r1) 9c16: 1c 41 42 00 mov 66(r1), r12 ;0x0042(r1) 9c1a: 1d 41 44 00 mov 68(r1), r13 ;0x0044(r1) 9c1e: 1c 81 46 00 sub 70(r1), r12 ;0x0046(r1) 9c22: 1d 71 48 00 subc 72(r1), r13 ;0x0048(r1) 9c26: 2c 83 decd r12 9c28: 1c 91 26 00 cmp 38(r1), r12 ;0x0026(r1) 9c2c: 0e 2c jc $+30 ;abs 0x9c4a 9c2e: e1 d3 01 00 bis.b #2, 1(r1) ;r3 As==10, 0x0001(r1) 9c32: 5e 41 26 00 mov.b 38(r1), r14 ;0x0026(r1) 9c36: 4e 8c sub.b r12, r14 9c38: c1 4e 03 00 mov.b r14, 3(r1) ;0x0003(r1) 9c3c: 06 3c jmp $+14 ;abs 0x9c4a 9c3e: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 9c42: 03 24 jz $+8 ;abs 0x9c4a 9c44: 91 41 26 00 mov 38(r1), 48(r1) ;0x0026(r1), 0x0030(r1) 9c48: 30 00 9c4a: 11 12 04 00 push 4(r1) ;0x0004(r1) 9c4e: 11 12 04 00 push 4(r1) ;0x0004(r1) 9c52: 1d 41 34 00 mov 52(r1), r13 ;0x0034(r1) 9c56: 0e 46 mov r6, r14 9c58: 1e 53 inc r14 9c5a: 1f 41 3e 00 mov 62(r1), r15 ;0x003e(r1) 9c5e: b0 12 96 94 call #0x9496 9c62: 21 52 add #4, r1 ;r2 As==10 9c64: 81 5f 2c 00 add r15, 44(r1) ;0x002c(r1) 9c68: 0d 3c jmp $+28 ;abs 0x9c84 9c6a: 7f 49 mov.b @r9+, r15 9c6c: 8f 11 sxt r15 9c6e: 91 12 3c 00 call 60(r1) ;0x003c(r1) 9c72: 0e 49 mov r9, r14 9c74: 0e 58 add r8, r14 9c76: 19 91 40 00 cmp 64(r1), r9 ;0x0040(r1) 9c7a: f7 2b jnc $-16 ;abs 0x9c6a 9c7c: 81 49 3e 00 mov r9, 62(r1) ;0x003e(r1) 9c80: 81 4e 2c 00 mov r14, 44(r1) ;0x002c(r1) 9c84: 07 43 clr r7 9c86: 0e 3c jmp $+30 ;abs 0x9ca4 9c88: 91 41 26 00 mov 38(r1), 48(r1) ;0x0026(r1), 0x0030(r1) 9c8c: 30 00 9c8e: d1 43 2e 00 mov.b #1, 46(r1) ;r3 As==01, 0x002e(r1) 9c92: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) 9c96: 03 3c jmp $+8 ;abs 0x9c9e 9c98: 05 4e mov r14, r5 9c9a: d1 43 2a 00 mov.b #1, 42(r1) ;r3 As==01, 0x002a(r1) 9c9e: 81 43 26 00 mov #0, 38(r1) ;r3 As==00, 0x0026(r1) 9ca2: 17 43 mov #1, r7 ;r3 As==01 9ca4: 16 41 40 00 mov 64(r1), r6 ;0x0040(r1) 9ca8: 6e 46 mov.b @r6, r14 9caa: 4e 93 tst.b r14 9cac: 02 24 jz $+6 ;abs 0x9cb2 9cae: 30 40 7a 96 br #0x967a 9cb2: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) 9cb6: 31 50 4a 00 add #74, r1 ;#0x004a 9cba: 34 41 pop r4 9cbc: 35 41 pop r5 9cbe: 36 41 pop r6 9cc0: 37 41 pop r7 9cc2: 38 41 pop r8 9cc4: 39 41 pop r9 9cc6: 3a 41 pop r10 9cc8: 3b 41 pop r11 9cca: 30 41 ret 00009ccc : 9ccc: 0b 12 push r11 9cce: 0d 93 tst r13 9cd0: 0e 24 jz $+30 ;abs 0x9cee 9cd2: 6c 4f mov.b @r15, r12 9cd4: 7b 4e mov.b @r14+, r11 9cd6: 4c 9b cmp.b r11, r12 9cd8: 05 24 jz $+12 ;abs 0x9ce4 9cda: 4f 4c mov.b r12, r15 9cdc: 5e 4e ff ff mov.b -1(r14),r14 ;0xffff(r14) 9ce0: 0f 8e sub r14, r15 9ce2: 06 3c jmp $+14 ;abs 0x9cf0 9ce4: 1f 53 inc r15 9ce6: 4c 93 tst.b r12 9ce8: 02 24 jz $+6 ;abs 0x9cee 9cea: 3d 53 add #-1, r13 ;r3 As==11 9cec: f0 3f jmp $-30 ;abs 0x9cce 9cee: 0f 43 clr r15 9cf0: 3b 41 pop r11 9cf2: 30 41 ret 00009cf4 <__xabi_udivmod64>: 9cf4: 07 12 push r7 9cf6: 06 12 push r6 9cf8: 05 12 push r5 9cfa: 04 12 push r4 9cfc: 30 12 40 00 push #64 ;#0x0040 9d00: 04 48 mov r8, r4 9d02: 05 49 mov r9, r5 9d04: 06 4a mov r10, r6 9d06: 07 4b mov r11, r7 9d08: 08 43 clr r8 9d0a: 09 43 clr r9 9d0c: 0a 43 clr r10 9d0e: 0b 43 clr r11 9d10: 0c 5c rla r12 9d12: 0d 6d rlc r13 9d14: 0e 6e rlc r14 9d16: 0f 6f rlc r15 9d18: 08 68 rlc r8 9d1a: 09 69 rlc r9 9d1c: 0a 6a rlc r10 9d1e: 0b 6b rlc r11 9d20: 0b 97 cmp r7, r11 9d22: 0e 28 jnc $+30 ;abs 0x9d40 9d24: 08 20 jnz $+18 ;abs 0x9d36 9d26: 0a 96 cmp r6, r10 9d28: 0b 28 jnc $+24 ;abs 0x9d40 9d2a: 05 20 jnz $+12 ;abs 0x9d36 9d2c: 09 95 cmp r5, r9 9d2e: 08 28 jnc $+18 ;abs 0x9d40 9d30: 02 20 jnz $+6 ;abs 0x9d36 9d32: 08 94 cmp r4, r8 9d34: 05 28 jnc $+12 ;abs 0x9d40 9d36: 08 84 sub r4, r8 9d38: 09 75 subc r5, r9 9d3a: 0a 76 subc r6, r10 9d3c: 0b 77 subc r7, r11 9d3e: 1c d3 bis #1, r12 ;r3 As==01 9d40: 91 83 00 00 dec 0(r1) ;0x0000(r1) 9d44: e5 23 jnz $-52 ;abs 0x9d10 9d46: 21 53 incd r1 9d48: 34 41 pop r4 9d4a: 35 41 pop r5 9d4c: 36 41 pop r6 9d4e: 37 41 pop r7 9d50: 30 41 ret 00009d52 <__udivdi3>: 9d52: 0b 12 push r11 9d54: 0a 12 push r10 9d56: 09 12 push r9 9d58: 08 12 push r8 9d5a: 18 41 0a 00 mov 10(r1), r8 ;0x000a(r1) 9d5e: 19 41 0c 00 mov 12(r1), r9 ;0x000c(r1) 9d62: 1a 41 0e 00 mov 14(r1), r10 ;0x000e(r1) 9d66: 1b 41 10 00 mov 16(r1), r11 ;0x0010(r1) 9d6a: b0 12 f4 9c call #0x9cf4 9d6e: 38 41 pop r8 9d70: 39 41 pop r9 9d72: 3a 41 pop r10 9d74: 3b 41 pop r11 9d76: 30 41 ret 00009d78 <__umoddi3>: 9d78: 0b 12 push r11 9d7a: 0a 12 push r10 9d7c: 09 12 push r9 9d7e: 08 12 push r8 9d80: 18 41 0a 00 mov 10(r1), r8 ;0x000a(r1) 9d84: 19 41 0c 00 mov 12(r1), r9 ;0x000c(r1) 9d88: 1a 41 0e 00 mov 14(r1), r10 ;0x000e(r1) 9d8c: 1b 41 10 00 mov 16(r1), r11 ;0x0010(r1) 9d90: b0 12 f4 9c call #0x9cf4 9d94: 0c 48 mov r8, r12 9d96: 0d 49 mov r9, r13 9d98: 0e 4a mov r10, r14 9d9a: 0f 4b mov r11, r15 9d9c: 38 41 pop r8 9d9e: 39 41 pop r9 9da0: 3a 41 pop r10 9da2: 3b 41 pop r11 9da4: 30 41 ret 00009da6 <__udivmoddi4>: 9da6: 0b 12 push r11 9da8: 0a 12 push r10 9daa: 09 12 push r9 9dac: 08 12 push r8 9dae: 07 12 push r7 9db0: 18 41 0c 00 mov 12(r1), r8 ;0x000c(r1) 9db4: 19 41 0e 00 mov 14(r1), r9 ;0x000e(r1) 9db8: 1a 41 10 00 mov 16(r1), r10 ;0x0010(r1) 9dbc: 1b 41 12 00 mov 18(r1), r11 ;0x0012(r1) 9dc0: b0 12 f4 9c call #0x9cf4 9dc4: 17 41 14 00 mov 20(r1), r7 ;0x0014(r1) 9dc8: 87 48 00 00 mov r8, 0(r7) ;0x0000(r7) 9dcc: 87 49 02 00 mov r9, 2(r7) ;0x0002(r7) 9dd0: 87 4a 04 00 mov r10, 4(r7) ;0x0004(r7) 9dd4: 87 4b 06 00 mov r11, 6(r7) ;0x0006(r7) 9dd8: 37 41 pop r7 9dda: 38 41 pop r8 9ddc: 39 41 pop r9 9dde: 3a 41 pop r10 9de0: 3b 41 pop r11 9de2: 30 41 ret 00009de4 <_unexpected_>: 9de4: 00 13 reti Disassembly of section .vectors: 0000ffe0 <__ivtbl_16>: ffe0: 44 86 44 86 6a 86 48 86 44 86 8c 86 44 86 c4 86 D.D.j.H.D...D... fff0: 94 86 44 86 44 86 44 86 44 86 44 86 44 86 00 80 ..D.D.D.D.D.D...