charlcd.elf: file format elf32-msp430 SYMBOL TABLE: 00001100 l d .text 00000000 .text 00000200 l d .bss 00000000 .bss 0000ffe0 l d .vectors 00000000 .vectors 00000000 l d .stab 00000000 .stab 00000000 l d .stabstr 00000000 .stabstr 00000040 l *ABS* 00000000 BTCTL 00000046 l *ABS* 00000000 BTCNT1 00000047 l *ABS* 00000000 BTCNT2 00000050 l *ABS* 00000000 SCFI0 00000051 l *ABS* 00000000 SCFI1 00000052 l *ABS* 00000000 SCFQCTL 00000053 l *ABS* 00000000 FLL_CTL0 00000054 l *ABS* 00000000 FLL_CTL1 00000056 l *ABS* 00000000 SVSCTL 00000090 l *ABS* 00000000 LCDCTL 00000091 l *ABS* 00000000 LCDM1 00000092 l *ABS* 00000000 LCDM2 00000093 l *ABS* 00000000 LCDM3 00000094 l *ABS* 00000000 LCDM4 00000095 l *ABS* 00000000 LCDM5 00000096 l *ABS* 00000000 LCDM6 00000097 l *ABS* 00000000 LCDM7 00000098 l *ABS* 00000000 LCDM8 00000099 l *ABS* 00000000 LCDM9 0000009a l *ABS* 00000000 LCDM10 0000009b l *ABS* 00000000 LCDM11 0000009c l *ABS* 00000000 LCDM12 0000009d l *ABS* 00000000 LCDM13 0000009e l *ABS* 00000000 LCDM14 0000009f l *ABS* 00000000 LCDM15 0000009a l *ABS* 00000000 LCDMA 0000009b l *ABS* 00000000 LCDMB 0000009c l *ABS* 00000000 LCDMC 0000009d l *ABS* 00000000 LCDMD 0000009e l *ABS* 00000000 LCDME 0000009f l *ABS* 00000000 LCDMF 000000a0 l *ABS* 00000000 LCDM16 000000a1 l *ABS* 00000000 LCDM17 000000a2 l *ABS* 00000000 LCDM18 000000a3 l *ABS* 00000000 LCDM19 000000a4 l *ABS* 00000000 LCDM20 00000128 l *ABS* 00000000 FCTL1 0000012a l *ABS* 00000000 FCTL2 0000012c l *ABS* 00000000 FCTL3 0000012e l *ABS* 00000000 TA0IV 00000160 l *ABS* 00000000 TA0CTL 00000170 l *ABS* 00000000 TA0R 00000162 l *ABS* 00000000 TA0CCTL0 00000164 l *ABS* 00000000 TA0CCTL1 00000172 l *ABS* 00000000 TA0CCR0 00000174 l *ABS* 00000000 TA0CCR1 00000166 l *ABS* 00000000 TA0CCTL2 00000176 l *ABS* 00000000 TA0CCR2 0000011e l *ABS* 00000000 TBIV 00000180 l *ABS* 00000000 TBCTL 00000190 l *ABS* 00000000 TBR 00000182 l *ABS* 00000000 TBCCTL0 00000184 l *ABS* 00000000 TBCCTL1 00000186 l *ABS* 00000000 TBCCTL2 00000192 l *ABS* 00000000 TBCCR0 00000194 l *ABS* 00000000 TBCCR1 00000196 l *ABS* 00000000 TBCCR2 00000188 l *ABS* 00000000 TBCCTL3 0000018a l *ABS* 00000000 TBCCTL4 0000018c l *ABS* 00000000 TBCCTL5 0000018e l *ABS* 00000000 TBCCTL6 00000198 l *ABS* 00000000 TBCCR3 0000019a l *ABS* 00000000 TBCCR4 0000019c l *ABS* 00000000 TBCCR5 0000019e l *ABS* 00000000 TBCCR6 00000070 l *ABS* 00000000 U0CTL 00000071 l *ABS* 00000000 U0TCTL 00000072 l *ABS* 00000000 U0RCTL 00000073 l *ABS* 00000000 U0MCTL 00000074 l *ABS* 00000000 U0BR0 00000075 l *ABS* 00000000 U0BR1 00000076 l *ABS* 00000000 U0RXBUF 00000077 l *ABS* 00000000 U0TXBUF 00000070 l *ABS* 00000000 UCTL 00000071 l *ABS* 00000000 UTCTL 00000072 l *ABS* 00000000 URCTL 00000073 l *ABS* 00000000 UMCTL 00000074 l *ABS* 00000000 UBR0 00000075 l *ABS* 00000000 UBR1 00000076 l *ABS* 00000000 RXBUF 00000077 l *ABS* 00000000 TXBUF 00000070 l *ABS* 00000000 UCTL0 00000071 l *ABS* 00000000 UTCTL0 00000072 l *ABS* 00000000 URCTL0 00000073 l *ABS* 00000000 UMCTL0 00000074 l *ABS* 00000000 UBR00 00000075 l *ABS* 00000000 UBR10 00000076 l *ABS* 00000000 RXBUF0 00000077 l *ABS* 00000000 TXBUF0 00000070 l *ABS* 00000000 UCTL_0 00000071 l *ABS* 00000000 UTCTL_0 00000072 l *ABS* 00000000 URCTL_0 00000073 l *ABS* 00000000 UMCTL_0 00000074 l *ABS* 00000000 UBR0_0 00000075 l *ABS* 00000000 UBR1_0 00000076 l *ABS* 00000000 RXBUF_0 00000077 l *ABS* 00000000 TXBUF_0 00000078 l *ABS* 00000000 U1CTL 00000079 l *ABS* 00000000 U1TCTL 0000007a l *ABS* 00000000 U1RCTL 0000007b l *ABS* 00000000 U1MCTL 0000007c l *ABS* 00000000 U1BR0 0000007d l *ABS* 00000000 U1BR1 0000007e l *ABS* 00000000 U1RXBUF 0000007f l *ABS* 00000000 U1TXBUF 00000078 l *ABS* 00000000 UCTL1 00000079 l *ABS* 00000000 UTCTL1 0000007a l *ABS* 00000000 URCTL1 0000007b l *ABS* 00000000 UMCTL1 0000007c l *ABS* 00000000 UBR01 0000007d l *ABS* 00000000 UBR11 0000007e l *ABS* 00000000 RXBUF1 0000007f l *ABS* 00000000 TXBUF1 00000078 l *ABS* 00000000 UCTL_1 00000079 l *ABS* 00000000 UTCTL_1 0000007a l *ABS* 00000000 URCTL_1 0000007b l *ABS* 00000000 UMCTL_1 0000007c l *ABS* 00000000 UBR0_1 0000007d l *ABS* 00000000 UBR1_1 0000007e l *ABS* 00000000 RXBUF_1 0000007f l *ABS* 00000000 TXBUF_1 000001a0 l *ABS* 00000000 ADC12CTL0 000001a2 l *ABS* 00000000 ADC12CTL1 000001a4 l *ABS* 00000000 ADC12IFG 000001a6 l *ABS* 00000000 ADC12IE 000001a8 l *ABS* 00000000 ADC12IV 00000140 l *ABS* 00000000 ADC12MEM0 00000142 l *ABS* 00000000 ADC12MEM1 00000144 l *ABS* 00000000 ADC12MEM2 00000146 l *ABS* 00000000 ADC12MEM3 00000148 l *ABS* 00000000 ADC12MEM4 0000014a l *ABS* 00000000 ADC12MEM5 0000014c l *ABS* 00000000 ADC12MEM6 0000014e l *ABS* 00000000 ADC12MEM7 00000150 l *ABS* 00000000 ADC12MEM8 00000152 l *ABS* 00000000 ADC12MEM9 00000154 l *ABS* 00000000 ADC12MEM10 00000156 l *ABS* 00000000 ADC12MEM11 00000158 l *ABS* 00000000 ADC12MEM12 0000015a l *ABS* 00000000 ADC12MEM13 0000015c l *ABS* 00000000 ADC12MEM14 0000015e l *ABS* 00000000 ADC12MEM15 00000080 l *ABS* 00000000 ADC12MCTL0 00000081 l *ABS* 00000000 ADC12MCTL1 00000082 l *ABS* 00000000 ADC12MCTL2 00000083 l *ABS* 00000000 ADC12MCTL3 00000084 l *ABS* 00000000 ADC12MCTL4 00000085 l *ABS* 00000000 ADC12MCTL5 00000086 l *ABS* 00000000 ADC12MCTL6 00000087 l *ABS* 00000000 ADC12MCTL7 00000088 l *ABS* 00000000 ADC12MCTL8 00000089 l *ABS* 00000000 ADC12MCTL9 0000008a l *ABS* 00000000 ADC12MCTL10 0000008b l *ABS* 00000000 ADC12MCTL11 0000008c l *ABS* 00000000 ADC12MCTL12 0000008d l *ABS* 00000000 ADC12MCTL13 0000008e l *ABS* 00000000 ADC12MCTL14 0000008f l *ABS* 00000000 ADC12MCTL15 00000130 l *ABS* 00000000 MPY 00000132 l *ABS* 00000000 MPYS 00000134 l *ABS* 00000000 MAC 00000136 l *ABS* 00000000 MACS 00000138 l *ABS* 00000000 OP2 0000013a l *ABS* 00000000 RESLO 0000013c l *ABS* 00000000 RESHI 0000013e l *ABS* 00000000 SUMEXT 00000020 l *ABS* 00000000 P1IN 00000021 l *ABS* 00000000 P1OUT 00000022 l *ABS* 00000000 P1DIR 00000023 l *ABS* 00000000 P1IFG 00000024 l *ABS* 00000000 P1IES 00000025 l *ABS* 00000000 P1IE 00000026 l *ABS* 00000000 P1SEL 00000028 l *ABS* 00000000 P2IN 00000029 l *ABS* 00000000 P2OUT 0000002a l *ABS* 00000000 P2DIR 0000002b l *ABS* 00000000 P2IFG 0000002c l *ABS* 00000000 P2IES 0000002d l *ABS* 00000000 P2IE 0000002e l *ABS* 00000000 P2SEL 00000018 l *ABS* 00000000 P3IN 00000019 l *ABS* 00000000 P3OUT 0000001a l *ABS* 00000000 P3DIR 0000001b l *ABS* 00000000 P3SEL 0000001c l *ABS* 00000000 P4IN 0000001d l *ABS* 00000000 P4OUT 0000001e l *ABS* 00000000 P4DIR 0000001f l *ABS* 00000000 P4SEL 00000030 l *ABS* 00000000 P5IN 00000031 l *ABS* 00000000 P5OUT 00000032 l *ABS* 00000000 P5DIR 00000033 l *ABS* 00000000 P5SEL 00000034 l *ABS* 00000000 P6IN 00000035 l *ABS* 00000000 P6OUT 00000036 l *ABS* 00000000 P6DIR 00000037 l *ABS* 00000000 P6SEL 00000059 l *ABS* 00000000 CACTL1 0000005a l *ABS* 00000000 CACTL2 0000005b l *ABS* 00000000 CAPD 00000120 l *ABS* 00000000 WDTCTL 00000000 l *ABS* 00000000 IE1 00000002 l *ABS* 00000000 IFG1 00000001 l *ABS* 00000000 IE2 00000003 l *ABS* 00000000 IFG2 00000004 l *ABS* 00000000 ME1 00000005 l *ABS* 00000000 ME2 00000000 l df *ABS* 00000000 main.c 00000130 l *ABS* 00000000 __MPY 00000132 l *ABS* 00000000 __MPYS 00000134 l *ABS* 00000000 __MAC 00000136 l *ABS* 00000000 __MACS 00000138 l *ABS* 00000000 __OP2 0000013a l *ABS* 00000000 __RESLO 0000013c l *ABS* 00000000 __RESHI 0000013e l *ABS* 00000000 __SUMEXT 00001376 l .text 00000000 Letext 00000000 g *ABS* 00000000 __data_size 00000200 g O .bss 00000002 PC_EN 00001378 g .text 00000000 _etext 00001268 g F .text 0000000e relay_deenergize 00000004 g *ABS* 00000000 __bss_size 00001376 w .text 00000000 __stop_progExec__ 00001130 g .text 00000000 _unexpected_1_ 00001130 w .text 00000000 vector_ffe0 00001136 g .text 00000000 vector_ffec 00001130 w .text 00000000 vector_fff0 00001378 g *ABS* 00000000 __data_load_start 00001130 g .text 00000000 __dtors_end 00001162 g .text 00000000 vector_fffc 00001130 w .text 00000000 vector_ffe4 0000ffe0 g O .vectors 00000020 InterruptVectors 0000111c w .text 00000000 __do_clear_bss 00001130 w .text 00000000 vector_ffe2 00001130 w .text 00000000 vector_ffe8 00001134 w .text 00000000 _unexpected_ 00001142 g .text 00000000 vector_fffa 000011a4 g F .text 000000c4 init 00001100 w .text 00000000 _reset_vector__ 00001142 g F .text 00000012 INT_TimerB_CCR0 00001130 g .text 00000000 __ctors_start 00001136 g F .text 0000000c INT_TimerA_CCR0 0000110a w .text 00000000 __do_copy_data 00000200 g .bss 00000000 __bss_start 00001130 w .text 00000000 vector_ffee 00001130 w .text 00000000 vector_fff4 0000130c g F .text 0000006a main 00001154 g F .text 0000000e INT_TimerB_CCR1 00001154 g .text 00000000 vector_fff8 00001130 w .text 00000000 vector_fff2 00010000 g .vectors 00000000 _vectors_end 00001130 w .text 00000000 vector_ffe6 00001176 g F .text 0000002e delay 00001162 g F .text 00000014 INT_OFIFG 00001100 w .text 00000000 __init_stack 00000202 g O .bss 00000002 FLAGS 00001130 g .text 00000000 __dtors_start 00001130 g .text 00000000 __ctors_end 00000a00 g *ABS* 00000000 __stack 00000200 g .bss 00000000 _edata 00000204 g .bss 00000000 _end 00001130 w .text 00000000 vector_fff6 00001104 w .text 00000000 __low_level_init 0000112c w .text 00000000 __jump_to_main 00000200 g .bss 00000000 __data_start 00001130 w .text 00000000 vector_ffea 00001276 g F .text 00000096 relay_control Disassembly of section .text: 00001100 <__init_stack>: 1100: 31 40 00 0a mov #2560, r1 ;#0x0a00 00001104 <__low_level_init>: 1104: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 1108: 20 01 0000110a <__do_copy_data>: 110a: 3f 40 00 00 mov #0, r15 ;#0x0000 110e: 0f 93 tst r15 1110: 05 24 jz $+12 ;abs 0x111c 1112: 2f 83 decd r15 1114: 9f 4f 78 13 mov 4984(r15),512(r15);0x1378(r15), 0x0200(r15) 1118: 00 02 111a: fb 23 jnz $-8 ;abs 0x1112 0000111c <__do_clear_bss>: 111c: 3f 40 04 00 mov #4, r15 ;#0x0004 1120: 0f 93 tst r15 1122: 04 24 jz $+10 ;abs 0x112c 1124: 1f 83 dec r15 1126: cf 43 00 02 mov.b #0, 512(r15);r3 As==00, 0x0200(r15) 112a: fc 23 jnz $-6 ;abs 0x1124 0000112c <__jump_to_main>: 112c: 30 40 0c 13 br #0x130c 00001130 <__ctors_end>: 1130: 30 40 34 11 br #0x1134 00001134 <_unexpected_>: 1134: 00 13 reti 00001136 : This one is executed once a second. it counts seconds, minutes, hours - hey it should be a clock ;-) it does not count days, but i think you'll get the idea :-) */ wakeup interrupt (TIMERA0_VECTOR) INT_TimerA_CCR0(void) { FLAGS |= ONE_SECOND; 1136: 92 d3 02 02 bis #1, &0x0202 ;r3 As==01 } 113a: b1 c0 f0 00 bic #240, 0(r1) ;#0x00f0, 0x0000(r1) 113e: 00 00 1140: 00 13 reti 00001142 : /** 18Khz clock to run the power converter! */ interrupt (TIMERB0_VECTOR) INT_TimerB_CCR0(void) { if(PC_EN) 1142: 82 93 00 02 tst &0x0200 1146: 03 24 jz $+8 ;abs 0x114e P6OUT &= ~PC_OUT; 1148: e2 c2 35 00 bic.b #4, &0x0035 ;r2 As==10 else P6OUT |= PC_OUT; //is inverted } 114c: 00 13 reti interrupt (TIMERB0_VECTOR) INT_TimerB_CCR0(void) { if(PC_EN) P6OUT &= ~PC_OUT; else P6OUT |= PC_OUT; //is inverted 114e: e2 d2 35 00 bis.b #4, &0x0035 ;r2 As==10 } 1152: 00 13 reti 00001154 : /** 18Khz clock to run the power converter! */ interrupt (TIMERB1_VECTOR) INT_TimerB_CCR1(void) { if(TBIV == 0x02) 1154: a2 93 1e 01 cmp #2, &0x011e ;r3 As==10 1158: 01 24 jz $+4 ;abs 0x115c P6OUT |= PC_OUT; //else // P6OUT |= PC_OUT; //is inverted } } 115a: 00 13 reti interrupt (TIMERB1_VECTOR) INT_TimerB_CCR1(void) { if(TBIV == 0x02) { //if(PC_EN) P6OUT |= PC_OUT; 115c: e2 d2 35 00 bis.b #4, &0x0035 ;r2 As==10 1160: fc 3f jmp $-6 ;abs 0x115a 00001162 : } /** 18Khz clock to run the power converter! */ interrupt (NMI_VECTOR) INT_OFIFG(void) { 1162: 0f 12 push r15 do{ PC_EN = 0; 1164: 82 43 00 02 mov #0, &0x0200 ;r3 As==00 //P1OUT |= LED; IFG1 &= ~OFIFG; 1168: e2 c3 02 00 bic.b #2, &0x0002 ;r3 As==10 }while (IFG1 & OFIFG); 116c: e2 b3 02 00 bit.b #2, &0x0002 ;r3 As==10 1170: f9 23 jnz $-12 ;abs 0x1164 //P1OUT &= ~LED; } 1172: 3f 41 pop r15 1174: 00 13 reti 00001176 : Delay function. */ void delay(unsigned int d) { int i; for (i = 0; i: /** Initialization procedures */ void init() { WDTCTL = WDTCTL_INIT; //Init watchdog timer 11a4: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 11a8: 20 01 P1OUT = P1OUT_INIT; //Init output data of port1 11aa: c2 43 21 00 mov.b #0, &0x0021 ;r3 As==00 P2OUT = P2OUT_INIT; //Init output data of port2 11ae: c2 43 29 00 mov.b #0, &0x0029 ;r3 As==00 P3OUT = P3OUT_INIT; //Init output data of port3 11b2: c2 43 19 00 mov.b #0, &0x0019 ;r3 As==00 P4OUT = P4OUT_INIT; //Init output data of port4 11b6: c2 43 1d 00 mov.b #0, &0x001d ;r3 As==00 P5OUT = P5OUT_INIT; //Init output data of port5 11ba: c2 43 31 00 mov.b #0, &0x0031 ;r3 As==00 P6OUT = P6OUT_INIT; //Init output data of port6 11be: e2 42 35 00 mov.b #4, &0x0035 ;r2 As==10 P1SEL = P1SEL_INIT; //Select port or module -function on port1 11c2: c2 43 26 00 mov.b #0, &0x0026 ;r3 As==00 P2SEL = P2SEL_INIT; //Select port or module -function on port2 11c6: c2 43 2e 00 mov.b #0, &0x002e ;r3 As==00 P3SEL = P3SEL_INIT; //Select port or module -function on port3 11ca: c2 43 1b 00 mov.b #0, &0x001b ;r3 As==00 P4SEL = P4SEL_INIT; //Select port or module -function on port4 11ce: c2 43 1f 00 mov.b #0, &0x001f ;r3 As==00 P5SEL = P5SEL_INIT; //Select port or module -function on port5 11d2: c2 43 33 00 mov.b #0, &0x0033 ;r3 As==00 P6SEL = P6SEL_INIT; //Select port or module -function on port6 11d6: c2 43 37 00 mov.b #0, &0x0037 ;r3 As==00 P1DIR = P1DIR_INIT; //Init port direction register of port1 11da: d2 43 22 00 mov.b #1, &0x0022 ;r3 As==01 P2DIR = P2DIR_INIT; //Init port direction register of port2 11de: c2 43 2a 00 mov.b #0, &0x002a ;r3 As==00 P3DIR = P3DIR_INIT; //Init port direction register of port3 11e2: c2 43 1a 00 mov.b #0, &0x001a ;r3 As==00 P4DIR = P4DIR_INIT; //Init port direction register of port4 11e6: f2 40 fc ff mov.b #-4, &0x001e ;#0xfffc 11ea: 1e 00 P5DIR = P5DIR_INIT; //Init port direction register of port5 11ec: f2 40 3f 00 mov.b #63, &0x0032 ;#0x003f 11f0: 32 00 P6DIR = P6DIR_INIT; //Init port direction register of port6 11f2: e2 42 36 00 mov.b #4, &0x0036 ;r2 As==10 P1IES = P1IES_INIT; //init port interrupts 11f6: c2 43 24 00 mov.b #0, &0x0024 ;r3 As==00 P2IES = P2IES_INIT; 11fa: c2 43 2c 00 mov.b #0, &0x002c ;r3 As==00 P1IE = P1IE_INIT; 11fe: c2 43 25 00 mov.b #0, &0x0025 ;r3 As==00 P2IE = P2IE_INIT; 1202: c2 43 2d 00 mov.b #0, &0x002d ;r3 As==00 FLL_CTL1 &= ~XT2OFF; //Start the 9Mhz clock 1206: f2 f0 df ff and.b #-33, &0x0054 ;#0xffdf 120a: 54 00 IFG1 &= ~OFIFG; delay(0xFFF); }while(IFG1 & OFIFG);*/ do{ IFG1 &= ~OFIFG; 120c: e2 c3 02 00 bic.b #2, &0x0002 ;r3 As==10 }while (IFG1 & OFIFG); 1210: e2 b3 02 00 bit.b #2, &0x0002 ;r3 As==10 1214: fb 23 jnz $-8 ;abs 0x120c FLL_CTL1 = SELS; //Start the 9Mhz clock, SMCLK<=XT2CLK 1216: e2 42 54 00 mov.b #4, &0x0054 ;r2 As==10 TACTL = TASSEL0|TACLR; //setup timer (still stopped) 121a: b2 40 04 01 mov #260, &0x0160 ;#0x0104 121e: 60 01 TACCR0 = ONESECOND; //setup first RTC irq 1220: b2 40 00 80 mov #-32768,&0x0172 ;#0x8000 1224: 72 01 TACCTL0 = CCIE; //enable compare interrupts 1226: b2 40 10 00 mov #16, &0x0162 ;#0x0010 122a: 62 01 TACCTL1 = 0; //the other modules are not used 122c: 82 43 64 01 mov #0, &0x0164 ;r3 As==00 TACCTL2 = 0; //... 1230: 82 43 66 01 mov #0, &0x0166 ;r3 As==00 TACTL |= MC0; //start timer 1234: b2 d0 10 00 bis #16, &0x0160 ;#0x0010 1238: 60 01 PC_EN = 0; 123a: 82 43 00 02 mov #0, &0x0200 ;r3 As==00 TBCTL = TBSSEL1|TBCLR; //SMCLK, clear 123e: b2 40 04 02 mov #516, &0x0180 ;#0x0204 1242: 80 01 //actual crystal freq = 8991000 TBCCR0 = 1240;//250; //18khz = 9,000,000/500 = 18,000. use 250 because we change states every 2f 1244: b2 40 d8 04 mov #1240, &0x0192 ;#0x04d8 1248: 92 01 //we want 18.5% for resonance TBCCR1 = 229;//250; //18khz = 9,000,000/500 = 18,000. use 250 because we change states every 2f 124a: b2 40 e5 00 mov #229, &0x0194 ;#0x00e5 124e: 94 01 TBCCTL0 = CCIE; //enable compare interrupts 1250: b2 40 10 00 mov #16, &0x0182 ;#0x0010 1254: 82 01 TBCCTL1 = OUTMOD_6 | CCIE; //the other modules are not used 1256: b2 40 d0 00 mov #208, &0x0184 ;#0x00d0 125a: 84 01 //TBCCTL2 = 0; //... TBCTL |= MC_UPTO_CCR0;// | TBIE; //enable interrupts, sTBrt counting! 125c: b2 d0 10 00 bis #16, &0x0180 ;#0x0010 1260: 80 01 IE1 |= OFIE; 1262: e2 d3 00 00 bis.b #2, &0x0000 ;r3 As==10 } 1266: 30 41 ret 00001268 : void relay_deenergize() { P5OUT &= ~(bit0 | bit1 | bit2 | bit3 | bit4 | bit5); //clear all relay control lines 1268: f2 f0 c0 ff and.b #-64, &0x0031 ;#0xffc0 126c: 31 00 P4OUT &= ~(bit2 | bit3 | bit4 | bit5 | bit6 | bit7); //clear all relay control lines 126e: f2 f0 03 00 and.b #3, &0x001d ;#0x0003 1272: 1d 00 } 1274: 30 41 ret 00001276 : void relay_control(char c,char pos) { //toggle switch, 1 is closed and 0 is open (or 1 is the back two contacts, and 0 is the middle two contacts switch(c) 1276: 8f 11 sxt r15 1278: 3f 90 03 00 cmp #3, r15 ;#0x0003 127c: 3d 24 jz $+124 ;abs 0x12f8 127e: 2f 92 cmp #4, r15 ;r2 As==10 1280: 17 34 jge $+48 ;abs 0x12b0 1282: 1f 93 cmp #1, r15 ;r3 As==01 1284: 0d 24 jz $+28 ;abs 0x12a0 1286: 2f 93 cmp #2, r15 ;r3 As==10 1288: 01 24 jz $+4 ;abs 0x128c //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 128a: 30 41 ret //delay(d); //P5OUT &= ~(bit0 | bit1); //never hurts to be overly explicit } break; case 2: if(pos == 1) 128c: 5e 93 cmp.b #1, r14 ;r3 As==01 128e: 04 24 jz $+10 ;abs 0x1298 //P4OUT &= ~(bit6 | bit7); //never hurts to be overly explicit } else { P4OUT |= bit7; 1290: f2 d0 80 ff bis.b #-128, &0x001d ;#0xff80 1294: 1d 00 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 1296: 30 41 ret break; case 2: if(pos == 1) { P4OUT |= bit6; 1298: f2 d0 40 00 bis.b #64, &0x001d ;#0x0040 129c: 1d 00 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 129e: 30 41 ret //toggle switch, 1 is closed and 0 is open (or 1 is the back two contacts, and 0 is the middle two contacts switch(c) { case 1: if(pos == 1) 12a0: 5e 93 cmp.b #1, r14 ;r3 As==01 12a2: 03 24 jz $+8 ;abs 0x12aa //P5OUT &= ~(bit0 | bit1); //never hurts to be overly explicit } else { P5OUT |= bit1; 12a4: e2 d3 31 00 bis.b #2, &0x0031 ;r3 As==10 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12a8: 30 41 ret case 1: if(pos == 1) { P5OUT |= bit0; 12aa: d2 d3 31 00 bis.b #1, &0x0031 ;r3 As==01 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12ae: 30 41 ret 12b0: 3f 90 05 00 cmp #5, r15 ;#0x0005 12b4: 19 24 jz $+52 ;abs 0x12e8 12b6: 3f 90 05 00 cmp #5, r15 ;#0x0005 12ba: 0e 38 jl $+30 ;abs 0x12d8 12bc: 3f 90 06 00 cmp #6, r15 ;#0x0006 12c0: 01 24 jz $+4 ;abs 0x12c4 12c2: 30 41 ret //delay(d); //P5OUT &= ~(bit2 | bit3); //never hurts to be overly explicit } break; case 6: if(pos == 1) 12c4: 5e 93 cmp.b #1, r14 ;r3 As==01 12c6: 04 24 jz $+10 ;abs 0x12d0 //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } else { P5OUT |= bit4; 12c8: f2 d0 10 00 bis.b #16, &0x0031 ;#0x0010 12cc: 31 00 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12ce: 30 41 ret break; case 6: if(pos == 1) { P5OUT |= bit5; 12d0: f2 d0 20 00 bis.b #32, &0x0031 ;#0x0020 12d4: 31 00 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12d6: 30 41 ret //delay(d); //P4OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; case 4: if(pos == 1) 12d8: 5e 93 cmp.b #1, r14 ;r3 As==01 12da: 03 24 jz $+8 ;abs 0x12e2 //P4OUT &= ~(bit2 | bit3); //never hurts to be overly explicit } else { P4OUT |= bit2; 12dc: e2 d2 1d 00 bis.b #4, &0x001d ;r2 As==10 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12e0: 30 41 ret break; case 4: if(pos == 1) { P4OUT |= bit3; 12e2: f2 d2 1d 00 bis.b #8, &0x001d ;r2 As==11 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12e6: 30 41 ret //delay(d); //P4OUT &= ~(bit2 | bit3); //never hurts to be overly explicit } break; case 5: if(pos == 1) 12e8: 5e 93 cmp.b #1, r14 ;r3 As==01 12ea: 03 24 jz $+8 ;abs 0x12f2 //P5OUT &= ~(bit2 | bit3); //never hurts to be overly explicit } else { P5OUT |= bit2; 12ec: e2 d2 31 00 bis.b #4, &0x0031 ;r2 As==10 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12f0: 30 41 ret break; case 5: if(pos == 1) { P5OUT |= bit3; 12f2: f2 d2 31 00 bis.b #8, &0x0031 ;r2 As==11 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 12f6: 30 41 ret //delay(d); //P4OUT &= ~(bit6 | bit7); //never hurts to be overly explicit } break; case 3: if(pos == 1) 12f8: 5e 93 cmp.b #1, r14 ;r3 As==01 12fa: 04 24 jz $+10 ;abs 0x1304 //P4OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } else { P4OUT |= bit5; 12fc: f2 d0 20 00 bis.b #32, &0x001d ;#0x0020 1300: 1d 00 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 1302: 30 41 ret break; case 3: if(pos == 1) { P4OUT |= bit4; 1304: f2 d0 10 00 bis.b #16, &0x001d ;#0x0010 1308: 1d 00 //delay(d); //P5OUT &= ~(bit4 | bit5); //never hurts to be overly explicit } break; } } 130a: 30 41 ret 0000130c
: /** Main function with init an an endless loop that is synced with the interrupts trough the lowpower mode. */ int main(void) { 130c: 31 40 00 0a mov #2560, r1 ;#0x0a00 int i,strand=4; 1310: 2a 42 mov #4, r10 ;r2 As==10 init(); 1312: b0 12 a4 11 call #0x11a4 eint(); //enable interrupts 1316: 32 d2 eint P1OUT |= LED; //light LED during init 1318: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 delay(0xF); 131c: 3f 40 0f 00 mov #15, r15 ;#0x000f 1320: b0 12 76 11 call #0x1176 P1OUT &= ~LED; //switch off LED 1324: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 TACCR0 = ONESECOND/20; 1328: b2 40 66 06 mov #1638, &0x0172 ;#0x0666 132c: 72 01 delay(0xFF); PC_EN = 0; delay(0xFF);*/ //P1OUT ^= LED; PC_EN = 0; 132e: 82 43 00 02 mov #0, &0x0200 ;r3 As==00 if(strand > 5) 1332: 3a 90 06 00 cmp #6, r10 ;#0x0006 1336: 01 38 jl $+4 ;abs 0x133a strand = 1; 1338: 1a 43 mov #1, r10 ;r3 As==01 relay_deenergize(); 133a: b0 12 68 12 call #0x1268 for(i=1; i<6; i++) 133e: 1b 43 mov #1, r11 ;r3 As==01 { if(i == strand) 1340: 0b 9a cmp r10, r11 1342: 14 24 jz $+42 ;abs 0x136c relay_control(i,1); else relay_control(i,0); 1344: 4e 43 clr.b r14 1346: 4f 4b mov.b r11, r15 1348: b0 12 76 12 call #0x1276 PC_EN = 0; if(strand > 5) strand = 1; relay_deenergize(); for(i=1; i<6; i++) 134c: 1b 53 inc r11 134e: 3b 90 06 00 cmp #6, r11 ;#0x0006 1352: f6 3b jl $-18 ;abs 0x1340 if(i == strand) relay_control(i,1); else relay_control(i,0); } delay(0x5F); //allow relays to switch 1354: 3f 40 5f 00 mov #95, r15 ;#0x005f 1358: b0 12 76 11 call #0x1176 relay_deenergize(); 135c: b0 12 68 12 call #0x1268 PC_EN = 1; 1360: 92 43 00 02 mov #1, &0x0200 ;r3 As==01 { delay(0x1FF); //TBCCR1++; }*/ strand++; 1364: 1a 53 inc r10 //P1OUT ^= LED; //delay(0xFF); //delay(0xFFF); LPM0; //sync, wakeup by irq 1366: 32 d0 10 00 bis #16, r2 ;#0x0010 136a: e1 3f jmp $-60 ;abs 0x132e strand = 1; relay_deenergize(); for(i=1; i<6; i++) { if(i == strand) relay_control(i,1); 136c: 5e 43 mov.b #1, r14 ;r3 As==01 136e: 4f 4a mov.b r10, r15 1370: eb 3f jmp $-40 ;abs 0x1348 //delay(0xFF); } } 1372: 30 40 76 13 br #0x1376 00001376 <__stop_progExec__>: 1376: ff 3f jmp $+0 ;abs 0x1376 Disassembly of section .vectors: 0000ffe0 : ffe0: 30 11 30 11 30 11 30 11 30 11 30 11 36 11 30 11 0.0.0.0.0.0.6.0. fff0: 30 11 30 11 30 11 30 11 54 11 42 11 62 11 00 11 0.0.0.0.T.B.b...