carputerTT.elf: file format elf32-msp430 SYMBOL TABLE: 00008000 l d .text 00000000 .text 00009f58 l d .rodata 00000000 .rodata 00000200 l d .bss 00000000 .bss 00000212 l d .noinit 00000000 .noinit 0000ffe0 l d .vectors 00000000 .vectors 00000000 l d .debug_aranges 00000000 .debug_aranges 00000000 l d .debug_info 00000000 .debug_info 00000000 l d .debug_abbrev 00000000 .debug_abbrev 00000000 l d .debug_line 00000000 .debug_line 00000000 l d .debug_frame 00000000 .debug_frame 00000000 l d .debug_str 00000000 .debug_str 00000000 l d .debug_loc 00000000 .debug_loc 00000000 l d .debug_ranges 00000000 .debug_ranges 00000000 l df *ABS* 00000000 main.c 000085e2 l .text 00000000 __br_unexpected_ 00000000 l df *ABS* 00000000 spi_hardware.c 00000000 l df *ABS* 00000000 fp-bit.c 00000000 l df *ABS* 00000000 fp-bit.c 00000000 l df *ABS* 00000000 fp-bit.c 00000000 l df *ABS* 00000000 fp-bit.c 00000000 l df *ABS* 00000000 libgcc2.c 00000000 l df *ABS* 00000000 fp-bit.c 00000000 l df *ABS* 00000000 fp-bit.c 00000000 l df *ABS* 00000000 libgcc2.c 00000000 l df *ABS* 00000000 strchr.c 00000000 l df *ABS* 00000000 memcmp.c 00000000 l df *ABS* 00000000 memcpy.c 00000000 l df *ABS* 00000000 memset.c 00000000 l df *ABS* 00000000 strstr.c 00000000 l df *ABS* 00000000 atoi.c 00000000 l df *ABS* 00000000 sprintf.c 0000954c l F .text 00000022 append 00000204 l O .bss 00000002 available_ 00000202 l O .bss 00000002 destination_ 0000956e l F .text 0000003c call_vuprintf 00000000 l df *ABS* 00000000 vuprintf.c 00009608 l F .text 00000198 print_field 00000000 l df *ABS* 00000000 strncmp.c 00000057 g *ABS* 00000000 __BCSCTL1 00000174 g *ABS* 00000000 __TACCR1 00000000 g *ABS* 00000000 __data_size 000085e2 w .text 00000000 __isr_14 00000128 g *ABS* 00000000 __FCTL1 00000024 g *ABS* 00000000 __P1IES 0000004b g *ABS* 00000000 __ADC10AE1 00000069 g *ABS* 00000000 __UCB0CTL1 000095e0 g F .text 00000016 vsprintf 00000206 g O .bss 00000001 RSSI_DBM_2500 000085e2 w .text 00000000 __isr_4 00000002 g *ABS* 00000000 __IFG1 00000060 g *ABS* 00000000 __UCA0CTL0 00008782 g F .text 0000003a sample_adc_chan 00008cdc g F .text 00000150 __divsf3 0000012e g *ABS* 00000000 __TAIV 000095c6 g F .text 0000001a snprintf 00000200 g O .bss 00000001 currentCarStatus 00008ed2 g F .text 00000090 __fixsfsi 00000207 g O .bss 00000001 inputEventByte 00000000 g .vectors 00000000 _efartext 00008c7a g F .text 00000000 __udivhi3 00000001 g *ABS* 00000000 __IE2 0000002b g *ABS* 00000000 __P2IFG 0000001a g *ABS* 00000000 __P3DIR 0000a198 g *ABS* 00000000 _etext 00000190 g *ABS* 00000000 __TBR 000010f8 g *ABS* 00000000 __CALDCO_16MHZ 00000208 g O .bss 00000001 RSSI_2500 0000001d g *ABS* 00000000 __P4OUT 00008770 g F .text 00000012 sample_adc 00000012 g *ABS* 00000000 __bss_size 000089e8 g F .text 000000ee RX_STRING_2500 000010fd g *ABS* 00000000 __CALBC1_8MHZ 00008000 w .text 00000000 __watchdog_support 000085dc w .text 00000000 __stop_progExec__ 00008bb8 g F .text 0000004e CC2500_SPI_WRREG 00009308 g F .text 000000fa memcpy 00008800 g F .text 00000020 init_B_UART_SPI 0000002d g *ABS* 00000000 __P2IE 000086f8 g F .text 00000064 sys_init 00000192 g *ABS* 00000000 __TBCCR0 000085e2 w .text 00000000 __isr_11 00000186 g *ABS* 00000000 __TBCCTL2 00008c9c g F .text 00000000 __udivsi3 00000025 g *ABS* 00000000 __P1IE 0000006b g *ABS* 00000000 __UCB0BR1 00008640 g F .text 0000008a tinit 000095f6 g F .text 00000012 vsnprintf 00000049 g *ABS* 00000000 __ADC10DTC1 00000066 g *ABS* 00000000 __UCA0RXBUF 00000061 g *ABS* 00000000 __UCA0CTL1 00009f18 g .text 00000000 __udivmoddi4 000085e6 g F .text 00000022 P2_VEC 00000209 g O .bss 00000001 LQI_2500 00000182 g *ABS* 00000000 __TBCCTL0 0000006d g *ABS* 00000000 __UCB0STAT 00008608 g .text 00000000 __isr_5 00000063 g *ABS* 00000000 __UCA0BR1 00009eea g F .text 00000000 __umoddi3 0000a198 g *ABS* 00000000 __data_load_start 000085e2 g .text 00000000 __dtors_end 00000053 g *ABS* 00000000 __BCSCTL3 000001bc g *ABS* 00000000 __ADC10SA 00000166 g *ABS* 00000000 __TACCTL2 00009ec4 g F .text 00000000 __udivdi3 00000065 g *ABS* 00000000 __UCA0STAT 000085e2 w .text 00000000 __isr_2 00000160 g *ABS* 00000000 __TACTL 0000012c g *ABS* 00000000 __FCTL3 000085e2 w .text 00000000 __isr_10 0000002e g *ABS* 00000000 __P2SEL 00000180 g *ABS* 00000000 __TBCTL 000010f9 g *ABS* 00000000 __CALBC1_16MHZ 000000c3 g *ABS* 00000000 __OA1CTL1 00000023 g *ABS* 00000000 __P1IFG 000010fb g *ABS* 00000000 __CALBC1_12MHZ 000091b2 g F .text 00000124 __unpack_f 0000004a g *ABS* 00000000 __ADC10AE0 0000011a g *ABS* 00000000 __UCB0I2CSA 00000172 g *ABS* 00000000 __TACCR0 00000056 g *ABS* 00000000 __DCOCTL 00000003 g *ABS* 00000000 __IFG2 00000212 g O .noinit 00000002 __wdt_clear_value 00008ad6 g F .text 0000004c TX_2500_STRING 0000001b g *ABS* 00000000 __P3SEL 000085e2 w .text 00000000 __isr_7 0000ffe0 g O .vectors 00000020 __ivtbl_16 0000006c g *ABS* 00000000 __UCB0I2CIE 0000006a g *ABS* 00000000 __UCB0BR0 00008cd2 g F .text 00000000 __umodsi3 00000028 g *ABS* 00000000 __P2IN 000089be g F .text 0000002a RX_MODE_2500 00008820 g F .text 0000019e CC2500_WRITE_SPI_RF_SETTINGS 00008fd4 g F .text 000001de __pack_f 00000118 g *ABS* 00000000 __UCB0I2COA 00000184 g *ABS* 00000000 __TBCCTL1 000001b4 g *ABS* 00000000 __ADC10MEM 00008c94 g F .text 00000000 __umodhi3 000085e2 w .text 00000000 __isr_0 00000029 g *ABS* 00000000 __P2OUT 0000012a g *ABS* 00000000 __FCTL2 00008f62 g F .text 00000072 __clzsi2 00000064 g *ABS* 00000000 __UCA0MCTL 00008028 w .text 00000000 __do_clear_bss 00000021 g *ABS* 00000000 __P1OUT 0000002c g *ABS* 00000000 __P2IES 00000026 g *ABS* 00000000 __P1SEL 0000946c g F .text 00000056 strstr 00008610 g F .text 00000030 TA1_VEC 00008e2c g F .text 000000a6 __floatsisf 00009e3e g F .text 00000028 strncmp 00008c9c g .text 00000000 __ext_udivmod32 00000027 g *ABS* 00000000 __P1REN 000000c0 g *ABS* 00000000 __OA0CTL0 00009f56 w .text 00000000 _unexpected_ 00008610 g .text 00000000 __isr_8 000085e6 g .text 00000000 __isr_3 000097a0 g F .text 0000069e vuprintf 000092e8 g F .text 00000020 memcmp 0000875c g F .text 00000014 init_adc 000010fc g *ABS* 00000000 __CALDCO_8MHZ 00008c7a g .text 00000000 __ext_udivmod16 00008000 w .text 00000000 _reset_vector__ 000085e2 g .text 00000000 __ctors_start 00009e66 g .text 00000000 __xabi_udivmod64 000085e2 w .text 00000000 __isr_12 000010fa g *ABS* 00000000 __CALDCO_12MHZ 0000a088 g O .rodata 00000008 __thenan_sf 00000018 g *ABS* 00000000 __P3IN 00008010 w .text 00000000 __do_copy_data 00008608 g F .text 00000008 ADC_VEC 00000200 g .bss 00000000 __bss_start 00009402 g F .text 0000006a memset 0000803e g F .text 0000059e main 00000176 g *ABS* 00000000 __TACCR2 000000c2 g *ABS* 00000000 __OA1CTL0 000085e2 w .text 00000000 __isr_13 00000170 g *ABS* 00000000 __TAR 0000001e g *ABS* 00000000 __P4DIR 0000020a g O .bss 00000002 seconds 00000162 g *ABS* 00000000 __TACCTL0 00010000 g .vectors 00000000 _vectors_end 0000002a g *ABS* 00000000 __P2DIR 000086ca g F .text 0000002e delay 00000068 g *ABS* 00000000 __UCB0CTL0 0000002f g *ABS* 00000000 __P2REN 000095aa g F .text 0000001c sprintf 0000a090 g O .rodata 00000100 __clz_tab 00008b5a g F .text 0000005e CC2500_SPI_RDREG 0000006e g *ABS* 00000000 __UCB0RXBUF 000001b0 g *ABS* 00000000 __ADC10CTL0 000085e2 w .text 00000000 __isr_9 0000005e g *ABS* 00000000 __UCA0IRTCTL 000010fe g *ABS* 00000000 __CALDCO_1MHZ 00000067 g *ABS* 00000000 __UCA0TXBUF 0000800c w .text 00000000 __init_stack 0000005d g *ABS* 00000000 __UCA0ABCTL 000087bc g F .text 00000044 shiftOut 00000019 g *ABS* 00000000 __P3OUT 000000c1 g *ABS* 00000000 __OA0CTL1 00008b22 g F .text 00000038 CC2500_SPI_STROBE 000085e2 g .text 00000000 __dtors_start 000085e2 w .text 00000000 __isr_6 000085e2 g .text 00000000 __ctors_end 00000062 g *ABS* 00000000 __UCA0BR0 00000600 g *ABS* 00000000 __stack 000085e2 w .text 00000000 __isr_1 00000200 g .rodata 00000000 _edata 00000214 g *ABS* 00000000 _end 00000194 g *ABS* 00000000 __TBCCR1 00000048 g *ABS* 00000000 __ADC10DTC0 0000011e g *ABS* 00000000 __TBIV 0000020c g O .bss 00000001 PKTSTATUS_2500 000001b2 g *ABS* 00000000 __ADC10CTL1 0000020e g O .bss 00000002 flags 00000058 g *ABS* 00000000 __BCSCTL2 000085dc w .text 00000000 _endless_loop__ 0000001f g *ABS* 00000000 __P4SEL 00000196 g *ABS* 00000000 __TBCCR2 000094c2 g F .text 0000008a atoi 00000022 g *ABS* 00000000 __P1DIR 00000210 g O .bss 00000001 status_2500 0000005f g *ABS* 00000000 __UCA0IRRCTL 00000010 g *ABS* 00000000 __P3REN 00000164 g *ABS* 00000000 __TACCTL1 0000006f g *ABS* 00000000 __UCB0TXBUF 000010ff g *ABS* 00000000 __CALBC1_1MHZ 00008010 w .text 00000000 __low_level_init 00008c06 g F .text 00000074 CC2500_SPI_BURST_WRREG 000092d6 g F .text 00000012 strchr 00000011 g *ABS* 00000000 __P4REN 00000200 g .rodata 00000000 __data_start 00000120 g *ABS* 00000000 __WDTCTL 00000000 g *ABS* 00000000 __IE1 00000020 g *ABS* 00000000 __P1IN 0000001c g *ABS* 00000000 __P4IN 00000211 g O .bss 00000001 rx_char Disassembly of section .text: 00008000 <__watchdog_support>: 8000: 55 42 20 01 mov.b &0x0120,r5 8004: 35 d0 08 5a bis #23048, r5 ;#0x5a08 8008: 82 45 12 02 mov r5, &0x0212 0000800c <__init_stack>: 800c: 31 40 00 06 mov #1536, r1 ;#0x0600 00008010 <__do_copy_data>: 8010: 3f 40 00 00 mov #0, r15 ;#0x0000 8014: 0f 93 tst r15 8016: 08 24 jz $+18 ;abs 0x8028 8018: 92 42 12 02 mov &0x0212,&0x0120 801c: 20 01 801e: 2f 83 decd r15 8020: 9f 4f 98 a1 mov -24168(r15),512(r15);0xa198(r15), 0x0200(r15) 8024: 00 02 8026: f8 23 jnz $-14 ;abs 0x8018 00008028 <__do_clear_bss>: 8028: 3f 40 12 00 mov #18, r15 ;#0x0012 802c: 0f 93 tst r15 802e: 07 24 jz $+16 ;abs 0x803e 8030: 92 42 12 02 mov &0x0212,&0x0120 8034: 20 01 8036: 1f 83 dec r15 8038: cf 43 00 02 mov.b #0, 512(r15);r3 As==00, 0x0200(r15) 803c: f9 23 jnz $-12 ;abs 0x8030 0000803e
: /** Main function. */ int main(void) { 803e: 31 50 b6 ff add #-74, r1 ;#0xffb6 int degC, volt, ibat, vbat; volatile long vbatraw, ibatraw, traw,vraw; int interval=100; //set report interval to every other interrupt (5hz) sys_init(); //initialize system parameters 8042: b0 12 f8 86 call #0x86f8 //SR_DATA } void init_B_UART_SPI() { UCB0CTL1 = UCSWRST; 8046: d2 43 69 00 mov.b #1, &0x0069 ;r3 As==01 UCB0CTL1 = UCSWRST | UCSSEL1; 804a: f2 40 81 ff mov.b #-127, &0x0069 ;#0xff81 804e: 69 00 UCB0CTL0 = UCCKPH | UCMSB | UCMST | UCSYNC; 8050: f2 40 a9 ff mov.b #-87, &0x0068 ;#0xffa9 8054: 68 00 UCB0BR0 = 2; 8056: e2 43 6a 00 mov.b #2, &0x006a ;r3 As==10 UCB0BR1 = 0; 805a: c2 43 6b 00 mov.b #0, &0x006b ;r3 As==00 UCB0CTL1 &= ~UCSWRST; 805e: f2 f0 fe ff and.b #-2, &0x0069 ;#0xfffe 8062: 69 00 /**init the ADC10 */ void init_adc() { ADC10AE1 = bit6; //bit6 = A14 8064: f2 40 40 00 mov.b #64, &0x004b ;#0x0040 8068: 4b 00 ADC10CTL0 = ADC10SR | ADC10ON | ADC10SHT_DIV64; //50kbps reduced power mode, ADC on, 16 clocks per sample window 806a: b2 40 10 1c mov #7184, &0x01b0 ;#0x1c10 806e: b0 01 ADC10CTL1 = ADC10SSEL_ACLK | INCH_2; //ACLK sourced, A2 input 8070: b2 40 08 20 mov #8200, &0x01b2 ;#0x2008 8074: b2 01 init_B_UART_SPI(); //get the UART into SPI mode such that we can talk to the CC2500 init_adc(); //turn on the ADC P4OUT ^= LED_GRN; 8076: f2 50 80 ff add.b #-128, &0x001d ;#0xff80 807a: 1d 00 delay(0xFFFF); //lil bit O delay 807c: 3f 43 mov #-1, r15 ;r3 As==11 807e: b0 12 ca 86 call #0x86ca P4OUT ^= LED_GRN; 8082: f2 50 80 ff add.b #-128, &0x001d ;#0xff80 8086: 1d 00 memset(CC2500_buffer, '\0', 64); //clear the buffer 8088: 3d 40 40 00 mov #64, r13 ;#0x0040 808c: 0e 43 clr r14 808e: 0f 41 mov r1, r15 8090: 2f 52 add #4, r15 ;r2 As==10 8092: b0 12 02 94 call #0x9402 //power on reset for 2500 P2OUT &= ~CSn_2500; //power on reset for radio, strobe CSn 8096: f2 f0 fb ff and.b #-5, &0x0029 ;#0xfffb 809a: 29 00 delay(0xFF); 809c: 3f 40 ff 00 mov #255, r15 ;#0x00ff 80a0: b0 12 ca 86 call #0x86ca P2OUT |= CSn_2500; 80a4: e2 d2 29 00 bis.b #4, &0x0029 ;r2 As==10 delay(0xFFFF); //Give chips time to reset 80a8: 3f 43 mov #-1, r15 ;r3 As==11 80aa: b0 12 ca 86 call #0x86ca //init CC2500 CC2500_SPI_STROBE(CCxxx0_SRES); //reset chip 80ae: 7f 40 30 00 mov.b #48, r15 ;#0x0030 80b2: b0 12 22 8b call #0x8b22 CC2500_WRITE_SPI_RF_SETTINGS(); //init chip 80b6: b0 12 20 88 call #0x8820 CC2500_SPI_STROBE(CCxxx0_SIDLE); //put into idle state 80ba: 7f 40 36 00 mov.b #54, r15 ;#0x0036 80be: b0 12 22 8b call #0x8b22 do{ CC2500_SPI_STROBE(CCxxx0_SIDLE);//Idle 80c2: 7f 40 36 00 mov.b #54, r15 ;#0x0036 80c6: b0 12 22 8b call #0x8b22 }while((status_2500 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle 80ca: 5f 42 10 02 mov.b &0x0210,r15 80ce: 3f b0 70 00 bit #112, r15 ;#0x0070 80d2: f7 23 jnz $-16 ;abs 0x80c2 delay(0xFFFF); P4OUT ^= LED_GRN; TX_2500_STRING("GND:TTC 2500 Startup", 20); P4OUT ^= LED_GRN; }*/ TX_2500_STRING("GND:TTC 2500 Startup", 20); 80d4: 7e 40 14 00 mov.b #20, r14 ;#0x0014 80d8: 3f 40 58 9f mov #-24744,r15 ;#0x9f58 80dc: b0 12 d6 8a call #0x8ad6 //length = sprintf(CC2500_buffer,"GND:TTC 2500 Startup"); //TX_2500_STRING(CC2500_buffer, length); //Blink out LED to verify bootup P4OUT ^= LED_RED; 80e0: f2 e0 40 00 xor.b #64, &0x001d ;#0x0040 80e4: 1d 00 delay(0xFF); //lil bit O delay 80e6: 3f 40 ff 00 mov #255, r15 ;#0x00ff 80ea: b0 12 ca 86 call #0x86ca P4OUT ^= LED_RED; 80ee: f2 e0 40 00 xor.b #64, &0x001d ;#0x0040 80f2: 1d 00 flags = 0; 80f4: 82 43 0e 02 mov #0, &0x020e ;r3 As==00 /** Setup the timer to generate an interrupt at an interval of milliseconds */ void tinit(unsigned int milliseconds) { TACCTL0 = CCIE; // TACCR0 interrupt enabled 80f8: b2 40 10 00 mov #16, &0x0162 ;#0x0010 80fc: 62 01 TACTL = TASSEL_1; // ACLK, upmode 80fe: b2 40 00 01 mov #256, &0x0160 ;#0x0100 8102: 60 01 TACTL &= ~TAIFG; //clear interrupt 8104: b2 f0 fe ff and #-2, &0x0160 ;#0xfffe 8108: 60 01 TACCR0 = (milliseconds * (unsigned long)12000)/1000; //one second intervals 810a: b2 40 e0 2e mov #12000, &0x0172 ;#0x2ee0 810e: 72 01 //TACCR0 = 12000; // ~1 second TAR = 0; 8110: 82 43 70 01 mov #0, &0x0170 ;r3 As==00 TACTL |= MC_UPTO_CCR0 | TAIE; //enable interrupts, start counting! 8114: b2 d0 12 00 bis #18, &0x0160 ;#0x0012 8118: 60 01 P4OUT ^= LED_RED; flags = 0; tinit(1000); //start generating an interrupts every 100mS seconds = 0; 811a: 82 43 0a 02 mov #0, &0x020a ;r3 As==00 P2IFG = 0x00; 811e: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 P1IFG = 0x00; 8122: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 eint(); //enable interrupts 8126: 32 d2 eint RX_MODE_2500(); //put CC2500 into listen mode. 8128: b0 12 be 89 call #0x89be shiftOut(outputWord); 812c: 0f 43 clr r15 812e: b0 12 bc 87 call #0x87bc unsigned char loop; int degC, volt, ibat, vbat; volatile long vbatraw, ibatraw, traw,vraw; int interval=100; //set report interval to every other interrupt (5hz) 8132: 36 40 64 00 mov #100, r6 ;#0x0064 /** Main function. */ int main(void) { unsigned int sample,length=0,i,outputWord=0x0000; 8136: 81 43 48 00 mov #0, 72(r1) ;r3 As==00, 0x0048(r1) shiftOut(outputWord); while (1) //main loop, never ends... { loop = 0; if(flags & CC2500_RDY) //Incoming packet on the CC2500 813a: a2 b3 0e 02 bit #2, &0x020e ;r3 As==10 813e: 02 20 jnz $+6 ;abs 0x8144 8140: 30 40 6e 84 br #0x846e { dint(); 8144: 32 c2 dint 8146: 03 43 nop loop = 1; P4OUT |= LED_RED; 8148: f2 d0 40 00 bis.b #64, &0x001d ;#0x0040 814c: 1d 00 flags &= ~CC2500_RDY; 814e: b2 f0 fd ff and #-3, &0x020e ;#0xfffd 8152: 0e 02 length = RX_STRING_2500(CC2500_buffer, 64); 8154: 7e 40 40 00 mov.b #64, r14 ;#0x0040 8158: 0f 41 mov r1, r15 815a: 2f 52 add #4, r15 ;r2 As==10 815c: b0 12 e8 89 call #0x89e8 P2IFG &= ~GDO0_2500; //reset trashed interrupt state 8160: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 8164: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets 8166: b0 12 be 89 call #0x89be //TX_2500_STRING(CC2500_buffer,length); if(LQI_2500 & bit7) //CRC ok 816a: 5a 42 09 02 mov.b &0x0209,r10 816e: 4a 93 tst.b r10 8170: 02 38 jl $+6 ;abs 0x8176 8172: 30 40 54 84 br #0x8454 { //TX_2500_STRING(CC2500_buffer,length); //P4OUT |= LED_GRN; if(!memcmp(CALLSIGN,CC2500_buffer,3)) //packet addressed to us 8176: 3d 40 03 00 mov #3, r13 ;#0x0003 817a: 0e 41 mov r1, r14 817c: 2e 52 add #4, r14 ;r2 As==10 817e: 3f 40 6d 9f mov #-24723,r15 ;#0x9f6d 8182: b0 12 e8 92 call #0x92e8 8186: 0f 93 tst r15 8188: 02 24 jz $+6 ;abs 0x818e 818a: 30 40 54 84 br #0x8454 { if(strstr( CC2500_buffer, "interval" ) != NULL) //its an interval query 818e: 3e 40 71 9f mov #-24719,r14 ;#0x9f71 8192: 0f 41 mov r1, r15 8194: 2f 52 add #4, r15 ;r2 As==10 8196: b0 12 6c 94 call #0x946c 819a: 0f 93 tst r15 819c: 2f 24 jz $+96 ;abs 0x81fc { length = atoi(strchr(CC2500_buffer, '=' )+1); //The new interval should follow the equals sign 819e: 3e 40 3d 00 mov #61, r14 ;#0x003d 81a2: 0f 41 mov r1, r15 81a4: 2f 52 add #4, r15 ;r2 As==10 81a6: b0 12 d6 92 call #0x92d6 81aa: 1f 53 inc r15 81ac: b0 12 c2 94 call #0x94c2 81b0: 0a 4f mov r15, r10 if(length > 0) 81b2: 0f 93 tst r15 81b4: 0f 24 jz $+32 ;abs 0x81d4 { interval = length; length = snprintf(CC2500_buffer,64,"GND:TTC Interval is now %d",interval); 81b6: 0f 12 push r15 81b8: 30 12 7a 9f push #-24710 ;#0x9f7a 81bc: 30 12 40 00 push #64 ;#0x0040 81c0: 3f 40 0a 00 mov #10, r15 ;#0x000a 81c4: 0f 51 add r1, r15 81c6: 0f 12 push r15 81c8: b0 12 c6 95 call #0x95c6 81cc: 31 52 add #8, r1 ;r2 As==11 81ce: 0d 4f mov r15, r13 81d0: 06 4a mov r10, r6 81d2: 0d 3c jmp $+28 ;abs 0x81ee } else length = snprintf(CC2500_buffer,64,"GND:TTC Reporting every %d seconds",interval); 81d4: 06 12 push r6 81d6: 30 12 95 9f push #-24683 ;#0x9f95 81da: 30 12 40 00 push #64 ;#0x0040 81de: 3f 40 0a 00 mov #10, r15 ;#0x000a 81e2: 0f 51 add r1, r15 81e4: 0f 12 push r15 81e6: b0 12 c6 95 call #0x95c6 81ea: 31 52 add #8, r1 ;r2 As==11 81ec: 0d 4f mov r15, r13 TX_2500_STRING(CC2500_buffer,length); 81ee: 4e 4d mov.b r13, r14 81f0: 0f 41 mov r1, r15 81f2: 2f 52 add #4, r15 ;r2 As==10 81f4: b0 12 d6 8a call #0x8ad6 81f8: 30 40 4a 84 br #0x844a } else if(strstr( CC2500_buffer, "status" ) != NULL) //its a status inquiery 81fc: 3e 40 b8 9f mov #-24648,r14 ;#0x9fb8 8200: 0f 41 mov r1, r15 8202: 2f 52 add #4, r15 ;r2 As==10 8204: b0 12 6c 94 call #0x946c 8208: 0f 93 tst r15 820a: 19 24 jz $+52 ;abs 0x823e { length = snprintf(CC2500_buffer,64,"GND:TTC R:%ddBm L:%u", RSSI_DBM_2500, LQI_2500); 820c: 4a 4a mov.b r10, r10 820e: 0a 12 push r10 8210: 5d 42 06 02 mov.b &0x0206,r13 8214: 8d 11 sxt r13 8216: 0d 12 push r13 8218: 30 12 bf 9f push #-24641 ;#0x9fbf 821c: 30 12 40 00 push #64 ;#0x0040 8220: 3f 40 0c 00 mov #12, r15 ;#0x000c 8224: 0f 51 add r1, r15 8226: 0f 12 push r15 8228: b0 12 c6 95 call #0x95c6 822c: 31 50 0a 00 add #10, r1 ;#0x000a TX_2500_STRING(CC2500_buffer,length); 8230: 4e 4f mov.b r15, r14 8232: 0f 41 mov r1, r15 8234: 2f 52 add #4, r15 ;r2 As==10 8236: b0 12 d6 8a call #0x8ad6 823a: 30 40 4a 84 br #0x844a } else if(strstr( CC2500_buffer, "now" ) != NULL) //report now 823e: 3e 40 d4 9f mov #-24620,r14 ;#0x9fd4 8242: 0f 41 mov r1, r15 8244: 2f 52 add #4, r15 ;r2 As==10 8246: b0 12 6c 94 call #0x946c 824a: 0f 93 tst r15 824c: 05 24 jz $+12 ;abs 0x8258 { flags |= GO_NOW | TIMER_UP; ///set event flags to trigger the reporting 824e: b2 d0 09 00 bis #9, &0x020e ;#0x0009 8252: 0e 02 8254: 30 40 4a 84 br #0x844a } else if(strstr( CC2500_buffer, "setword" ) != NULL) //its an interval query 8258: 3e 40 d8 9f mov #-24616,r14 ;#0x9fd8 825c: 0f 41 mov r1, r15 825e: 2f 52 add #4, r15 ;r2 As==10 8260: b0 12 6c 94 call #0x946c 8264: 0f 93 tst r15 8266: 2a 24 jz $+86 ;abs 0x82bc { length = atoi(strchr(CC2500_buffer, '=' )+1); //The new interval should follow the equals sign 8268: 3e 40 3d 00 mov #61, r14 ;#0x003d 826c: 0f 41 mov r1, r15 826e: 2f 52 add #4, r15 ;r2 As==10 8270: b0 12 d6 92 call #0x92d6 8274: 1f 53 inc r15 8276: b0 12 c2 94 call #0x94c2 if(length > 0) 827a: 0f 93 tst r15 827c: 0e 24 jz $+30 ;abs 0x829a { outputWord |= length; 827e: 81 df 48 00 bis r15, 72(r1) ;0x0048(r1) length = sprintf(CC2500_buffer,"GND:TTC output is now %u",outputWord); 8282: 11 12 4a 00 push 74(r1) ;0x004a(r1) 8286: 30 12 e0 9f push #-24608 ;#0x9fe0 828a: 3f 42 mov #8, r15 ;r2 As==11 828c: 0f 51 add r1, r15 828e: 0f 12 push r15 8290: b0 12 aa 95 call #0x95aa 8294: 31 50 06 00 add #6, r1 ;#0x0006 8298: 0b 3c jmp $+24 ;abs 0x82b0 } else length = sprintf(CC2500_buffer,"GND:TTC output state=%u",outputWord); 829a: 11 12 4a 00 push 74(r1) ;0x004a(r1) 829e: 30 12 f9 9f push #-24583 ;#0x9ff9 82a2: 3f 42 mov #8, r15 ;r2 As==11 82a4: 0f 51 add r1, r15 82a6: 0f 12 push r15 82a8: b0 12 aa 95 call #0x95aa 82ac: 31 50 06 00 add #6, r1 ;#0x0006 TX_2500_STRING(CC2500_buffer,length); 82b0: 4e 4f mov.b r15, r14 82b2: 0f 41 mov r1, r15 82b4: 2f 52 add #4, r15 ;r2 As==10 82b6: b0 12 d6 8a call #0x8ad6 82ba: c7 3c jmp $+400 ;abs 0x844a } else if(strstr( CC2500_buffer, "clearword" ) != NULL) //its an interval query 82bc: 3e 40 11 a0 mov #-24559,r14 ;#0xa011 82c0: 0f 41 mov r1, r15 82c2: 2f 52 add #4, r15 ;r2 As==10 82c4: b0 12 6c 94 call #0x946c 82c8: 0f 93 tst r15 82ca: 2a 24 jz $+86 ;abs 0x8320 { length = atoi(strchr(CC2500_buffer, '=' )+1); //The new interval should follow the equals sign 82cc: 3e 40 3d 00 mov #61, r14 ;#0x003d 82d0: 0f 41 mov r1, r15 82d2: 2f 52 add #4, r15 ;r2 As==10 82d4: b0 12 d6 92 call #0x92d6 82d8: 1f 53 inc r15 82da: b0 12 c2 94 call #0x94c2 if(length > 0) 82de: 0f 93 tst r15 82e0: 0e 24 jz $+30 ;abs 0x82fe { outputWord &= ~length; 82e2: 81 cf 48 00 bic r15, 72(r1) ;0x0048(r1) length = sprintf(CC2500_buffer,"GND:TTC output is now %u",outputWord); 82e6: 11 12 4a 00 push 74(r1) ;0x004a(r1) 82ea: 30 12 e0 9f push #-24608 ;#0x9fe0 82ee: 3f 42 mov #8, r15 ;r2 As==11 82f0: 0f 51 add r1, r15 82f2: 0f 12 push r15 82f4: b0 12 aa 95 call #0x95aa 82f8: 31 50 06 00 add #6, r1 ;#0x0006 82fc: 0b 3c jmp $+24 ;abs 0x8314 } else length = sprintf(CC2500_buffer,"GND:TTC output state=%u",outputWord); 82fe: 11 12 4a 00 push 74(r1) ;0x004a(r1) 8302: 30 12 f9 9f push #-24583 ;#0x9ff9 8306: 3f 42 mov #8, r15 ;r2 As==11 8308: 0f 51 add r1, r15 830a: 0f 12 push r15 830c: b0 12 aa 95 call #0x95aa 8310: 31 50 06 00 add #6, r1 ;#0x0006 TX_2500_STRING(CC2500_buffer,length); 8314: 4e 4f mov.b r15, r14 8316: 0f 41 mov r1, r15 8318: 2f 52 add #4, r15 ;r2 As==10 831a: b0 12 d6 8a call #0x8ad6 831e: 95 3c jmp $+300 ;abs 0x844a } else if(strstr( CC2500_buffer, "shift" ) != NULL) //report now 8320: 3e 40 1b a0 mov #-24549,r14 ;#0xa01b 8324: 0f 41 mov r1, r15 8326: 2f 52 add #4, r15 ;r2 As==10 8328: b0 12 6c 94 call #0x946c 832c: 0f 93 tst r15 832e: 05 24 jz $+12 ;abs 0x833a { shiftOut(outputWord); 8330: 1f 41 48 00 mov 72(r1), r15 ;0x0048(r1) 8334: b0 12 bc 87 call #0x87bc 8338: 88 3c jmp $+274 ;abs 0x844a } else if(strstr( CC2500_buffer, " lock" ) != NULL) //report now 833a: 3e 40 21 a0 mov #-24543,r14 ;#0xa021 833e: 0f 41 mov r1, r15 8340: 2f 52 add #4, r15 ;r2 As==10 8342: b0 12 6c 94 call #0x946c 8346: 0f 93 tst r15 8348: 2e 24 jz $+94 ;abs 0x83a6 { outputWord |= OUT_LOCK | OUT_BLINK; 834a: 1a 41 48 00 mov 72(r1), r10 ;0x0048(r1) 834e: 3a d0 00 a0 bis #-24576,r10 ;#0xa000 shiftOut(outputWord); 8352: 0f 4a mov r10, r15 8354: b0 12 bc 87 call #0x87bc delay(0xFFFF); 8358: 3f 43 mov #-1, r15 ;r3 As==11 835a: b0 12 ca 86 call #0x86ca delay(0xFFFF); 835e: 3f 43 mov #-1, r15 ;r3 As==11 8360: b0 12 ca 86 call #0x86ca outputWord &= ~OUT_LOCK; shiftOut(outputWord); 8364: 0f 4a mov r10, r15 8366: 3f f0 ff 7f and #32767, r15 ;#0x7fff 836a: b0 12 bc 87 call #0x87bc delay(0xFFFF); 836e: 3f 43 mov #-1, r15 ;r3 As==11 8370: b0 12 ca 86 call #0x86ca delay(0xFFFF); 8374: 3f 43 mov #-1, r15 ;r3 As==11 8376: b0 12 ca 86 call #0x86ca outputWord &= ~OUT_BLINK; 837a: 3a f0 ff 5f and #24575, r10 ;#0x5fff 837e: 81 4a 48 00 mov r10, 72(r1) ;0x0048(r1) shiftOut(outputWord); 8382: 0f 4a mov r10, r15 8384: b0 12 bc 87 call #0x87bc length = sprintf(CC2500_buffer,"GND:TTC Doors Locked"); 8388: 3d 40 15 00 mov #21, r13 ;#0x0015 838c: 3e 40 27 a0 mov #-24537,r14 ;#0xa027 8390: 0f 41 mov r1, r15 8392: 2f 52 add #4, r15 ;r2 As==10 8394: b0 12 08 93 call #0x9308 TX_2500_STRING(CC2500_buffer,length); 8398: 7e 40 14 00 mov.b #20, r14 ;#0x0014 839c: 0f 41 mov r1, r15 839e: 2f 52 add #4, r15 ;r2 As==10 83a0: b0 12 d6 8a call #0x8ad6 83a4: 52 3c jmp $+166 ;abs 0x844a } else if(strstr( CC2500_buffer, " unlock" ) != NULL) //report now 83a6: 3e 40 3c a0 mov #-24516,r14 ;#0xa03c 83aa: 0f 41 mov r1, r15 83ac: 2f 52 add #4, r15 ;r2 As==10 83ae: b0 12 6c 94 call #0x946c 83b2: 0f 93 tst r15 83b4: 2e 24 jz $+94 ;abs 0x8412 { outputWord |= OUT_UNLOCK | OUT_BLINK; 83b6: 1a 41 48 00 mov 72(r1), r10 ;0x0048(r1) 83ba: 3a d0 00 60 bis #24576, r10 ;#0x6000 shiftOut(outputWord); 83be: 0f 4a mov r10, r15 83c0: b0 12 bc 87 call #0x87bc delay(0xFFFF); 83c4: 3f 43 mov #-1, r15 ;r3 As==11 83c6: b0 12 ca 86 call #0x86ca delay(0xFFFF); 83ca: 3f 43 mov #-1, r15 ;r3 As==11 83cc: b0 12 ca 86 call #0x86ca outputWord &= ~OUT_UNLOCK; shiftOut(outputWord); 83d0: 0f 4a mov r10, r15 83d2: 3f f0 ff bf and #-16385,r15 ;#0xbfff 83d6: b0 12 bc 87 call #0x87bc delay(0xFFFF); 83da: 3f 43 mov #-1, r15 ;r3 As==11 83dc: b0 12 ca 86 call #0x86ca delay(0xFFFF); 83e0: 3f 43 mov #-1, r15 ;r3 As==11 83e2: b0 12 ca 86 call #0x86ca outputWord &= ~OUT_BLINK; 83e6: 3a f0 ff 9f and #-24577,r10 ;#0x9fff 83ea: 81 4a 48 00 mov r10, 72(r1) ;0x0048(r1) shiftOut(outputWord); 83ee: 0f 4a mov r10, r15 83f0: b0 12 bc 87 call #0x87bc length = sprintf(CC2500_buffer,"GND:TTC Doors UN-Locked"); 83f4: 3d 40 18 00 mov #24, r13 ;#0x0018 83f8: 3e 40 44 a0 mov #-24508,r14 ;#0xa044 83fc: 0f 41 mov r1, r15 83fe: 2f 52 add #4, r15 ;r2 As==10 8400: b0 12 08 93 call #0x9308 TX_2500_STRING(CC2500_buffer,length); 8404: 7e 40 17 00 mov.b #23, r14 ;#0x0017 8408: 0f 41 mov r1, r15 840a: 2f 52 add #4, r15 ;r2 As==10 840c: b0 12 d6 8a call #0x8ad6 8410: 1c 3c jmp $+58 ;abs 0x844a } else if(strstr( CC2500_buffer, " reboot" ) != NULL) //report now 8412: 3e 40 5c a0 mov #-24484,r14 ;#0xa05c 8416: 0f 41 mov r1, r15 8418: 2f 52 add #4, r15 ;r2 As==10 841a: b0 12 6c 94 call #0x946c 841e: 0f 93 tst r15 8420: 04 24 jz $+10 ;abs 0x842a { WDTCTL = WDTCNTCL|WDTPW; 8422: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 8426: 20 01 8428: ff 3f jmp $+0 ;abs 0x8428 while(1); //reboot in 32ms } else //command not recognized, give a pong to ack reception { length = snprintf(CC2500_buffer,64,"GND:TTC Pong!"); 842a: 30 12 64 a0 push #-24476 ;#0xa064 842e: 30 12 40 00 push #64 ;#0x0040 8432: 3f 42 mov #8, r15 ;r2 As==11 8434: 0f 51 add r1, r15 8436: 0f 12 push r15 8438: b0 12 c6 95 call #0x95c6 843c: 31 50 06 00 add #6, r1 ;#0x0006 TX_2500_STRING(CC2500_buffer, length); 8440: 4e 4f mov.b r15, r14 8442: 0f 41 mov r1, r15 8444: 2f 52 add #4, r15 ;r2 As==10 8446: b0 12 d6 8a call #0x8ad6 } P2IFG &= ~GDO0_2500; //reset trashed interrupt state 844a: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 844e: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets 8450: b0 12 be 89 call #0x89be //P2IFG &= ~GDO0_2500; //reset trashed interrupt state //RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets //turn off LEDs P4OUT &= ~(LED_RED | LED_GRN); 8454: f2 f0 3f 00 and.b #63, &0x001d ;#0x003f 8458: 1d 00 memset(CC2500_buffer, 0, 64); 845a: 3d 40 40 00 mov #64, r13 ;#0x0040 845e: 0e 43 clr r14 8460: 0f 41 mov r1, r15 8462: 2f 52 add #4, r15 ;r2 As==10 8464: b0 12 02 94 call #0x9402 eint(); 8468: 32 d2 eint loop = 0; if(flags & CC2500_RDY) //Incoming packet on the CC2500 { dint(); loop = 1; 846a: 5c 43 mov.b #1, r12 ;r3 As==01 846c: 01 3c jmp $+4 ;abs 0x8470 RX_MODE_2500(); //put CC2500 into listen mode. shiftOut(outputWord); while (1) //main loop, never ends... { loop = 0; 846e: 4c 43 clr.b r12 //turn off LEDs P4OUT &= ~(LED_RED | LED_GRN); memset(CC2500_buffer, 0, 64); eint(); } if(flags & TIMER_UP) //Did the timer expire? report your findings! 8470: 92 b3 0e 02 bit #1, &0x020e ;r3 As==01 8474: ab 24 jz $+344 ;abs 0x85cc { //(100 / 764) = 0.1309 loop = 1; if(((seconds) % interval) == 0 || (flags & GO_NOW)) //report every 20 second by default 8476: 1f 42 0a 02 mov &0x020a,r15 847a: 0e 46 mov r6, r14 847c: b0 12 94 8c call #0x8c94 8480: 0f 93 tst r15 8482: 05 24 jz $+12 ;abs 0x848e 8484: b2 b2 0e 02 bit #8, &0x020e ;r2 As==11 8488: 02 20 jnz $+6 ;abs 0x848e 848a: 30 40 3a 81 br #0x813a { flags &= ~(TIMER_UP|GO_NOW); //clear the flag 848e: b2 f0 f6 ff and #-10, &0x020e ;#0xfff6 8492: 0e 02 ADC10CTL1 = INCH_10 + ADC10DIV_4; // Temp Sensor ADC10CLK/5 8494: b2 40 80 a0 mov #-24448,&0x01b2 ;#0xa080 8498: b2 01 ADC10CTL0 = SREF_1 + ADC10SHT_3 + REFON + ADC10ON + ADC10IE + ADC10SR; 849a: b2 40 38 3c mov #15416, &0x01b0 ;#0x3c38 849e: b0 01 for( degC = 240; degC > 0; degC-- ); // delay to allow reference to settle ADC10CTL0 |= ENC + ADC10SC; // Sampling and conversion start 84a0: b2 d0 03 00 bis #3, &0x01b0 ;#0x0003 84a4: b0 01 LPM3; 84a6: 32 d0 d0 00 bis #208, r2 ;#0x00d0 traw = ADC10MEM; 84aa: 14 42 b4 01 mov &0x01b4,r4 84ae: 05 43 clr r5 84b0: 81 44 00 00 mov r4, 0(r1) ;0x0000(r1) 84b4: 81 45 02 00 mov r5, 2(r1) ;0x0002(r1) ADC10CTL0 &= ~(REFON + ADC10ON); // turn off A/D to save power 84b8: b2 f0 cf ff and #-49, &0x01b0 ;#0xffcf 84bc: b0 01 dint(); 84be: 32 c2 dint 84c0: 03 43 nop degC = (((traw - 673) * 4230) / 1024); 84c2: 28 41 mov @r1, r8 84c4: 19 41 02 00 mov 2(r1), r9 ;0x0002(r1) traw = sample_adc_chan(ADC_IN_VBATT); 84c8: 3f 40 00 e0 mov #-8192, r15 ;#0xe000 84cc: b0 12 82 87 call #0x8782 84d0: 81 4f 44 00 mov r15, 68(r1) ;0x0044(r1) 84d4: 8f 10 swpb r15 84d6: 8f 11 sxt r15 84d8: 8f 10 swpb r15 84da: 8f 11 sxt r15 84dc: 81 4f 46 00 mov r15, 70(r1) ;0x0046(r1) 84e0: 91 41 44 00 mov 68(r1), 0(r1) ;0x0044(r1), 0x0000(r1) 84e4: 00 00 84e6: 91 41 46 00 mov 70(r1), 2(r1) ;0x0046(r1), 0x0002(r1) 84ea: 02 00 length=snprintf(CC2500_buffer,64, "GND:%s S:%u T:%d V:%d", CALLSIGN, seconds, degC, (int)(traw/7.64)); //send the temperature to the ground 84ec: 2e 41 mov @r1, r14 84ee: 1f 41 02 00 mov 2(r1), r15 ;0x0002(r1) 84f2: 17 42 0a 02 mov &0x020a,r7 84f6: b0 12 2c 8e call #0x8e2c 84fa: 3c 40 e1 7a mov #31457, r12 ;#0x7ae1 84fe: 3d 40 f4 40 mov #16628, r13 ;#0x40f4 8502: b0 12 dc 8c call #0x8cdc 8506: b0 12 d2 8e call #0x8ed2 850a: 0e 12 push r14 LPM3; traw = ADC10MEM; ADC10CTL0 &= ~(REFON + ADC10ON); // turn off A/D to save power dint(); degC = (((traw - 673) * 4230) / 1024); 850c: 0c 48 mov r8, r12 850e: 0d 49 mov r9, r13 8510: 0c 5c rla r12 8512: 0d 6d rlc r13 8514: 0c 5c rla r12 8516: 0d 6d rlc r13 8518: 0c 5c rla r12 851a: 0d 6d rlc r13 851c: 0c 5c rla r12 851e: 0d 6d rlc r13 8520: 0a 4c mov r12, r10 8522: 0b 4d mov r13, r11 8524: 0a 5a rla r10 8526: 0b 6b rlc r11 8528: 0a 5a rla r10 852a: 0b 6b rlc r11 852c: 0a 5a rla r10 852e: 0b 6b rlc r11 8530: 0a 5a rla r10 8532: 0b 6b rlc r11 8534: 0a 5a rla r10 8536: 0b 6b rlc r11 8538: 0c 5a add r10, r12 853a: 0d 6b addc r11, r13 853c: 0c 58 add r8, r12 853e: 0d 69 addc r9, r13 8540: 0c 5c rla r12 8542: 0d 6d rlc r13 8544: 0c 5c rla r12 8546: 0d 6d rlc r13 8548: 0c 88 sub r8, r12 854a: 0d 79 subc r9, r13 854c: 0c 5c rla r12 854e: 0d 6d rlc r13 8550: 0a 4c mov r12, r10 8552: 0b 4d mov r13, r11 8554: 3a 50 ba 8f add #-28742,r10 ;#0x8fba 8558: 3b 60 d4 ff addc #-44, r11 ;#0xffd4 855c: 0b 93 tst r11 855e: 06 34 jge $+14 ;abs 0x856c 8560: 0a 4c mov r12, r10 8562: 0b 4d mov r13, r11 8564: 3a 50 b9 93 add #-27719,r10 ;#0x93b9 8568: 3b 60 d4 ff addc #-44, r11 ;#0xffd4 856c: 0c 4a mov r10, r12 856e: 0d 4b mov r11, r13 8570: 0c 4a mov r10, r12 8572: 8c 10 swpb r12 8574: 8d 10 swpb r13 8576: 4c ed xor.b r13, r12 8578: 0c ed xor r13, r12 857a: 8d 11 sxt r13 857c: 0d 11 rra r13 857e: 0c 10 rrc r12 8580: 0d 11 rra r13 8582: 0c 10 rrc r12 traw = sample_adc_chan(ADC_IN_VBATT); length=snprintf(CC2500_buffer,64, "GND:%s S:%u T:%d V:%d", CALLSIGN, seconds, degC, (int)(traw/7.64)); //send the temperature to the ground 8584: 0c 12 push r12 8586: 07 12 push r7 8588: 30 12 6d 9f push #-24723 ;#0x9f6d 858c: 30 12 72 a0 push #-24462 ;#0xa072 8590: 30 12 40 00 push #64 ;#0x0040 8594: 3f 40 10 00 mov #16, r15 ;#0x0010 8598: 0f 51 add r1, r15 859a: 0f 12 push r15 859c: b0 12 c6 95 call #0x95c6 85a0: 31 50 0e 00 add #14, r1 ;#0x000e TX_2500_STRING(CC2500_buffer,length); 85a4: 4e 4f mov.b r15, r14 85a6: 0f 41 mov r1, r15 85a8: 2f 52 add #4, r15 ;r2 As==10 85aa: b0 12 d6 8a call #0x8ad6 P2IFG &= ~GDO0_2500; //reset trashed interrupt state 85ae: f2 f0 fe ff and.b #-2, &0x002b ;#0xfffe 85b2: 2b 00 RX_MODE_2500(); //set the radio back to RX mode so we don't miss any packets 85b4: b0 12 be 89 call #0x89be memset(CC2500_buffer, 0, 64); 85b8: 3d 40 40 00 mov #64, r13 ;#0x0040 85bc: 0e 43 clr r14 85be: 0f 41 mov r1, r15 85c0: 2f 52 add #4, r15 ;r2 As==10 85c2: b0 12 02 94 call #0x9402 eint(); 85c6: 32 d2 eint 85c8: 30 40 3a 81 br #0x813a } } if(loop == 0) 85cc: 4c 93 tst.b r12 85ce: 02 24 jz $+6 ;abs 0x85d4 85d0: 30 40 3a 81 br #0x813a LPM3; //when we wake up it'll be because of an event 85d4: 32 d0 d0 00 bis #208, r2 ;#0x00d0 85d8: 30 40 3a 81 br #0x813a 000085dc <__stop_progExec__>: 85dc: 32 d0 f0 00 bis #240, r2 ;#0x00f0 85e0: fd 3f jmp $-4 ;abs 0x85dc 000085e2 <__ctors_end>: 85e2: 30 40 56 9f br #0x9f56 000085e6 : This interrupt is trigger when a packet arrives on the CC2500 */ // Port 2 interripts : the allspice controller is talking to us interrupt (PORT2_VECTOR) P2_VEC(void) { 85e6: 0f 12 push r15 dint(); //no nesting! 85e8: 32 c2 dint 85ea: 03 43 nop if((P2IFG & GDO0_2500) == GDO0_2500) 85ec: 5f 42 2b 00 mov.b &0x002b,r15 85f0: 1f f3 and #1, r15 ;r3 As==01 85f2: 05 24 jz $+12 ;abs 0x85fe { flags |= CC2500_RDY; 85f4: a2 d3 0e 02 bis #2, &0x020e ;r3 As==10 LPM3_EXIT; 85f8: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) 85fc: 02 00 //We need to grab that byte! } P2IFG=0x00; 85fe: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 eint(); 8602: 32 d2 eint } 8604: 3f 41 pop r15 8606: 00 13 reti 00008608 : */ // Port 2 interripts : the allspice controller is talking to us interrupt (ADC10_VECTOR) ADC_VEC(void) { LPM3_EXIT; 8608: b1 c0 d0 00 bic #208, 0(r1) ;#0x00d0, 0x0000(r1) 860c: 00 00 } 860e: 00 13 reti 00008610 : /** This is called once every overflow */ interrupt (TIMERA1_VECTOR) TA1_VEC(void) { 8610: 0f 12 push r15 dint(); //no nesting! 8612: 32 c2 dint 8614: 03 43 nop if(TAIV == 0x0A) //reading this bit will clear the interrupt flags 8616: 1f 42 2e 01 mov &0x012e,r15 861a: 3f 90 0a 00 cmp #10, r15 ;#0x000a 861e: 03 24 jz $+8 ;abs 0x8626 flags |= TIMER_UP; seconds++; TACTL &= ~TAIFG; //clear the flag LPM3_EXIT; } eint(); 8620: 32 d2 eint } 8622: 3f 41 pop r15 8624: 00 13 reti dint(); //no nesting! if(TAIV == 0x0A) //reading this bit will clear the interrupt flags { //P1OUT ^= LED_RED; flags |= TIMER_UP; 8626: 92 d3 0e 02 bis #1, &0x020e ;r3 As==01 seconds++; 862a: 92 53 0a 02 inc &0x020a TACTL &= ~TAIFG; //clear the flag 862e: b2 f0 fe ff and #-2, &0x0160 ;#0xfffe 8632: 60 01 LPM3_EXIT; 8634: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) 8638: 02 00 } eint(); 863a: 32 d2 eint } 863c: 3f 41 pop r15 863e: 00 13 reti 00008640 : /** Setup the timer to generate an interrupt at an interval of milliseconds */ void tinit(unsigned int milliseconds) { 8640: 0b 12 push r11 8642: 0a 12 push r10 TACCTL0 = CCIE; // TACCR0 interrupt enabled 8644: b2 40 10 00 mov #16, &0x0162 ;#0x0010 8648: 62 01 TACTL = TASSEL_1; // ACLK, upmode 864a: b2 40 00 01 mov #256, &0x0160 ;#0x0100 864e: 60 01 TACTL &= ~TAIFG; //clear interrupt 8650: b2 f0 fe ff and #-2, &0x0160 ;#0xfffe 8654: 60 01 TACCR0 = (milliseconds * (unsigned long)12000)/1000; //one second intervals 8656: 0c 43 clr r12 8658: 0e 4f mov r15, r14 865a: 0f 4c mov r12, r15 865c: 0e 5e rla r14 865e: 0f 6f rlc r15 8660: 0e 5e rla r14 8662: 0f 6f rlc r15 8664: 0e 5e rla r14 8666: 0f 6f rlc r15 8668: 0e 5e rla r14 866a: 0f 6f rlc r15 866c: 0e 5e rla r14 866e: 0f 6f rlc r15 8670: 0c 4e mov r14, r12 8672: 0d 4f mov r15, r13 8674: 0c 5c rla r12 8676: 0d 6d rlc r13 8678: 0c 5c rla r12 867a: 0d 6d rlc r13 867c: 0e 5c add r12, r14 867e: 0f 6d addc r13, r15 8680: 0c 4e mov r14, r12 8682: 0d 4f mov r15, r13 8684: 0c 5c rla r12 8686: 0d 6d rlc r13 8688: 0c 5c rla r12 868a: 0d 6d rlc r13 868c: 0a 4e mov r14, r10 868e: 0b 4f mov r15, r11 8690: 0a 5c add r12, r10 8692: 0b 6d addc r13, r11 8694: 0e 4a mov r10, r14 8696: 0f 4b mov r11, r15 8698: 0e 5e rla r14 869a: 0f 6f rlc r15 869c: 0e 5e rla r14 869e: 0f 6f rlc r15 86a0: 0e 5e rla r14 86a2: 0f 6f rlc r15 86a4: 0e 5e rla r14 86a6: 0f 6f rlc r15 86a8: 3c 40 e8 03 mov #1000, r12 ;#0x03e8 86ac: 0d 43 clr r13 86ae: 0e 8a sub r10, r14 86b0: 0f 7b subc r11, r15 86b2: b0 12 9c 8c call #0x8c9c 86b6: 82 4e 72 01 mov r14, &0x0172 //TACCR0 = 12000; // ~1 second TAR = 0; 86ba: 82 43 70 01 mov #0, &0x0170 ;r3 As==00 TACTL |= MC_UPTO_CCR0 | TAIE; //enable interrupts, start counting! 86be: b2 d0 12 00 bis #18, &0x0160 ;#0x0012 86c2: 60 01 } 86c4: 3a 41 pop r10 86c6: 3b 41 pop r11 86c8: 30 41 ret 000086ca : Delay function. */ void delay(unsigned int d) { int i; for (i = 0; i: Set up the system */ void sys_init() { WDTCTL = WDTCTL_INIT; //Init watchdog timer 86f8: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 86fc: 20 01 P1OUT = P1OUT_INIT; //Init output data of port1 86fe: c2 43 21 00 mov.b #0, &0x0021 ;r3 As==00 P2OUT = P2OUT_INIT; //Init output data of port2 8702: f2 40 14 00 mov.b #20, &0x0029 ;#0x0014 8706: 29 00 P3OUT = P3OUT_INIT; 8708: c2 43 19 00 mov.b #0, &0x0019 ;r3 As==00 P4OUT = P4OUT_INIT; 870c: c2 43 1d 00 mov.b #0, &0x001d ;r3 As==00 P1SEL = P1SEL_INIT; //Select port or module -function on port1 8710: c2 43 26 00 mov.b #0, &0x0026 ;r3 As==00 P2SEL = P2SEL_INIT; //Select port or module -function on port2 8714: c2 43 2e 00 mov.b #0, &0x002e ;r3 As==00 P3SEL = P3SEL_INIT; 8718: c2 43 1b 00 mov.b #0, &0x001b ;r3 As==00 P4SEL = P4SEL_INIT; 871c: f2 40 20 00 mov.b #32, &0x001f ;#0x0020 8720: 1f 00 P1DIR = P1DIR_INIT; //Init port direction register of port1 8722: f2 43 22 00 mov.b #-1, &0x0022 ;r3 As==11 P2DIR = P2DIR_INIT; //Init port direction register of port2 8726: f2 40 fc ff mov.b #-4, &0x002a ;#0xfffc 872a: 2a 00 P3DIR = P3DIR_INIT; 872c: f2 40 fb ff mov.b #-5, &0x001a ;#0xfffb 8730: 1a 00 P4DIR = P4DIR_INIT; 8732: f2 40 df ff mov.b #-33, &0x001e ;#0xffdf 8736: 1e 00 P1IES = P1IES_INIT; //init port interrupts 8738: c2 43 24 00 mov.b #0, &0x0024 ;r3 As==00 P2IES = P2IES_INIT; 873c: d2 43 2c 00 mov.b #1, &0x002c ;r3 As==01 P1IE = P1IE_INIT; 8740: c2 43 25 00 mov.b #0, &0x0025 ;r3 As==00 P2IE = P2IE_INIT; 8744: d2 43 2d 00 mov.b #1, &0x002d ;r3 As==01 //P1REN = P1REN_INIT; BCSCTL1 = CALBC1_12MHZ; // Set DCO 8748: d2 42 fb 10 mov.b &0x10fb,&0x0057 874c: 57 00 DCOCTL = CALDCO_12MHZ; 874e: d2 42 fa 10 mov.b &0x10fa,&0x0056 8752: 56 00 BCSCTL3 = LFXT1S_2; //use the ultra low oscilator for wakeup intervals, not very accurate/ 8754: f2 40 20 00 mov.b #32, &0x0053 ;#0x0020 8758: 53 00 } 875a: 30 41 ret 0000875c : /**init the ADC10 */ void init_adc() { ADC10AE1 = bit6; //bit6 = A14 875c: f2 40 40 00 mov.b #64, &0x004b ;#0x0040 8760: 4b 00 ADC10CTL0 = ADC10SR | ADC10ON | ADC10SHT_DIV64; //50kbps reduced power mode, ADC on, 16 clocks per sample window 8762: b2 40 10 1c mov #7184, &0x01b0 ;#0x1c10 8766: b0 01 ADC10CTL1 = ADC10SSEL_ACLK | INCH_2; //ACLK sourced, A2 input 8768: b2 40 08 20 mov #8200, &0x01b2 ;#0x2008 876c: b2 01 } 876e: 30 41 ret 00008770 : //get a reading from the ADC10MEM int sample_adc() { ADC10CTL0 |= ENC | ADC10SC; // Sampling and conversion start 8770: b2 d0 03 00 bis #3, &0x01b0 ;#0x0003 8774: b0 01 while(ADC10CTL1 & ADC10BUSY); 8776: 92 b3 b2 01 bit #1, &0x01b2 ;r3 As==01 877a: fd 23 jnz $-4 ;abs 0x8776 return ADC10MEM; 877c: 1f 42 b4 01 mov &0x01b4,r15 } 8780: 30 41 ret 00008782 : int sample_adc_chan(int chan) { ADC10CTL0 &= ~ENC; // have to disable ADC10 to change channel 8782: b2 f0 fd ff and #-3, &0x01b0 ;#0xfffd 8786: b0 01 if(chan == INCH_TEMP) ADC10CTL0 |= SREF_VREF_AVSS; //set the ref to 1.5V for the temp sensor 8788: 1e 42 b0 01 mov &0x01b0,r14 } int sample_adc_chan(int chan) { ADC10CTL0 &= ~ENC; // have to disable ADC10 to change channel if(chan == INCH_TEMP) 878c: 3f 90 00 a0 cmp #-24576,r15 ;#0xa000 8790: 10 24 jz $+34 ;abs 0x87b2 ADC10CTL0 |= SREF_VREF_AVSS; //set the ref to 1.5V for the temp sensor else ADC10CTL0 &= ~SREF_VREF_AVSS; //set the ref to VCC for the external sensors 8792: 3e f0 ff df and #-8193, r14 ;#0xdfff 8796: 82 4e b0 01 mov r14, &0x01b0 ADC10CTL1 = ADC10SSEL_ACLK | chan; //ACLK sourced, A2 input 879a: 3f d2 bis #8, r15 ;r2 As==11 879c: 82 4f b2 01 mov r15, &0x01b2 ADC10CTL0 |= ENC | ADC10SC; // Sampling and conversion start 87a0: b2 d0 03 00 bis #3, &0x01b0 ;#0x0003 87a4: b0 01 while(ADC10CTL1 & ADC10BUSY); 87a6: 92 b3 b2 01 bit #1, &0x01b2 ;r3 As==01 87aa: fd 23 jnz $-4 ;abs 0x87a6 return ADC10MEM; 87ac: 1f 42 b4 01 mov &0x01b4,r15 } 87b0: 30 41 ret int sample_adc_chan(int chan) { ADC10CTL0 &= ~ENC; // have to disable ADC10 to change channel if(chan == INCH_TEMP) ADC10CTL0 |= SREF_VREF_AVSS; //set the ref to 1.5V for the temp sensor 87b2: 3e d0 00 20 bis #8192, r14 ;#0x2000 87b6: 82 4e b0 01 mov r14, &0x01b0 87ba: ef 3f jmp $-32 ;abs 0x879a 000087bc : } void shiftOut(unsigned int data) { unsigned int i; P4OUT |= SR_CLEAR; //pulse clock resets (tied) low to clear ouputs 87bc: e2 d2 1d 00 bis.b #4, &0x001d ;r2 As==10 P4OUT &= ~(SR_CLEAR | SR_RCLK | SR_SCLK); //Make sure clocks are low 87c0: f2 f0 f8 ff and.b #-8, &0x001d ;#0xfff8 87c4: 1d 00 P4OUT |= SR_CLEAR; 87c6: e2 d2 1d 00 bis.b #4, &0x001d ;r2 As==10 87ca: 3d 40 10 00 mov #16, r13 ;#0x0010 for(i=0;i<16;i++) { P4OUT &= ~(SR_SCLK | SR_DATA); 87ce: f2 f0 f5 ff and.b #-11, &0x001d ;#0xfff5 87d2: 1d 00 P4OUT |= SR_DATA & (data << 3);//bit3 is the data line 87d4: 5c 42 1d 00 mov.b &0x001d,r12 87d8: 4e 4f mov.b r15, r14 87da: 4e 5e rla.b r14 87dc: 4e 5e rla.b r14 87de: 4e 5e rla.b r14 87e0: 7e f2 and.b #8, r14 ;r2 As==11 87e2: 4e dc bis.b r12, r14 87e4: c2 4e 1d 00 mov.b r14, &0x001d P4OUT |= SR_SCLK; 87e8: e2 d3 1d 00 bis.b #2, &0x001d ;r3 As==10 data = data >> 1; 87ec: 12 c3 clrc 87ee: 0f 10 rrc r15 87f0: 3d 53 add #-1, r13 ;r3 As==11 { unsigned int i; P4OUT |= SR_CLEAR; //pulse clock resets (tied) low to clear ouputs P4OUT &= ~(SR_CLEAR | SR_RCLK | SR_SCLK); //Make sure clocks are low P4OUT |= SR_CLEAR; for(i=0;i<16;i++) 87f2: ed 23 jnz $-36 ;abs 0x87ce P4OUT &= ~(SR_SCLK | SR_DATA); P4OUT |= SR_DATA & (data << 3);//bit3 is the data line P4OUT |= SR_SCLK; data = data >> 1; } P4OUT |= SR_RCLK; 87f4: d2 d3 1d 00 bis.b #1, &0x001d ;r3 As==01 P4OUT &= ~(SR_SCLK | SR_RCLK | SR_DATA); 87f8: f2 f0 f4 ff and.b #-12, &0x001d ;#0xfff4 87fc: 1d 00 //SR_RCLK //storage register //SR_SCLK //shift //SR_CLEAR //SR_DATA } 87fe: 30 41 ret 00008800 : void init_B_UART_SPI() { UCB0CTL1 = UCSWRST; 8800: d2 43 69 00 mov.b #1, &0x0069 ;r3 As==01 UCB0CTL1 = UCSWRST | UCSSEL1; 8804: f2 40 81 ff mov.b #-127, &0x0069 ;#0xff81 8808: 69 00 UCB0CTL0 = UCCKPH | UCMSB | UCMST | UCSYNC; 880a: f2 40 a9 ff mov.b #-87, &0x0068 ;#0xffa9 880e: 68 00 UCB0BR0 = 2; 8810: e2 43 6a 00 mov.b #2, &0x006a ;r3 As==10 UCB0BR1 = 0; 8814: c2 43 6b 00 mov.b #0, &0x006b ;r3 As==00 UCB0CTL1 &= ~UCSWRST; 8818: f2 f0 fe ff and.b #-2, &0x0069 ;#0xfffe 881c: 69 00 } 881e: 30 41 ret 00008820 : Configure the CC2500 chip */ void CC2500_WRITE_SPI_RF_SETTINGS() { // Write register settings CC2500_SPI_WRREG(CCxxx0_IOCFG2, P2_IOCFG2); // GDO2 output pin config. 8820: 7e 40 0b 00 mov.b #11, r14 ;#0x000b 8824: 4f 43 clr.b r15 8826: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_IOCFG0, P2_IOCFG0); // GDO0 output pin config. 882a: 7e 40 06 00 mov.b #6, r14 ;#0x0006 882e: 6f 43 mov.b #2, r15 ;r3 As==10 8830: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_PKTLEN, P2_PKTLEN); // Packet length. 8834: 7e 40 3c 00 mov.b #60, r14 ;#0x003c 8838: 7f 40 06 00 mov.b #6, r15 ;#0x0006 883c: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_PKTCTRL1, P2_PKTCTRL1); // Packet automation control. 8840: 6e 42 mov.b #4, r14 ;r2 As==10 8842: 7f 40 07 00 mov.b #7, r15 ;#0x0007 8846: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_PKTCTRL0, P2_PKTCTRL0); // Packet automation control. 884a: 7e 40 05 00 mov.b #5, r14 ;#0x0005 884e: 7f 42 mov.b #8, r15 ;r2 As==11 8850: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_ADDR, P2_ADDR); // Device address. 8854: 5e 43 mov.b #1, r14 ;r3 As==01 8856: 7f 40 09 00 mov.b #9, r15 ;#0x0009 885a: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_CHANNR, P2_CHANNR); // Channel number. 885e: 7e 40 9a ff mov.b #-102, r14 ;#0xff9a 8862: 7f 40 0a 00 mov.b #10, r15 ;#0x000a 8866: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FSCTRL1, P2_FSCTRL1); // Freq synthesizer control. 886a: 7e 40 0a 00 mov.b #10, r14 ;#0x000a 886e: 7f 40 0b 00 mov.b #11, r15 ;#0x000b 8872: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FSCTRL0, P2_FSCTRL0); // Freq synthesizer control. 8876: 4e 43 clr.b r14 8878: 7f 40 0c 00 mov.b #12, r15 ;#0x000c 887c: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FREQ2, P2_FREQ2); // Freq control word, high byte 8880: 7e 40 5c 00 mov.b #92, r14 ;#0x005c 8884: 7f 40 0d 00 mov.b #13, r15 ;#0x000d 8888: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FREQ1, P2_FREQ1); // Freq control word, mid byte. 888c: 7e 40 4f 00 mov.b #79, r14 ;#0x004f 8890: 7f 40 0e 00 mov.b #14, r15 ;#0x000e 8894: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FREQ0, P2_FREQ0); // Freq control word, low byte. 8898: 7e 40 c0 ff mov.b #-64, r14 ;#0xffc0 889c: 7f 40 0f 00 mov.b #15, r15 ;#0x000f 88a0: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_MDMCFG4, P2_MDMCFG4); // Modem configuration. 88a4: 7e 40 2d 00 mov.b #45, r14 ;#0x002d 88a8: 7f 40 10 00 mov.b #16, r15 ;#0x0010 88ac: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_MDMCFG3, P2_MDMCFG3); // Modem configuration. 88b0: 7e 40 3b 00 mov.b #59, r14 ;#0x003b 88b4: 7f 40 11 00 mov.b #17, r15 ;#0x0011 88b8: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_MDMCFG2, P2_MDMCFG2); // Modem configuration. 88bc: 7e 40 73 00 mov.b #115, r14 ;#0x0073 88c0: 7f 40 12 00 mov.b #18, r15 ;#0x0012 88c4: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_MDMCFG1, P2_MDMCFG1); // Modem configuration. 88c8: 7e 40 23 00 mov.b #35, r14 ;#0x0023 88cc: 7f 40 13 00 mov.b #19, r15 ;#0x0013 88d0: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_MDMCFG0, P2_MDMCFG0); // Modem configuration. 88d4: 7e 40 b9 ff mov.b #-71, r14 ;#0xffb9 88d8: 7f 40 14 00 mov.b #20, r15 ;#0x0014 88dc: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_DEVIATN, P2_DEVIATN); // Modem dev (when FSK mod en) 88e0: 5e 43 mov.b #1, r14 ;r3 As==01 88e2: 7f 40 15 00 mov.b #21, r15 ;#0x0015 88e6: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_MCSM1 , P2_MCSM1 ); //MainRadio Cntrl State Machine 88ea: 7e 40 33 00 mov.b #51, r14 ;#0x0033 88ee: 7f 40 17 00 mov.b #23, r15 ;#0x0017 88f2: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_MCSM0 , P2_MCSM0 ); //MainRadio Cntrl State Machine 88f6: 7e 40 18 00 mov.b #24, r14 ;#0x0018 88fa: 7f 40 18 00 mov.b #24, r15 ;#0x0018 88fe: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FOCCFG, P2_FOCCFG); // Freq Offset Compens. Config 8902: 7e 40 1d 00 mov.b #29, r14 ;#0x001d 8906: 7f 40 19 00 mov.b #25, r15 ;#0x0019 890a: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_BSCFG, P2_BSCFG); // Bit synchronization config. 890e: 7e 40 1c 00 mov.b #28, r14 ;#0x001c 8912: 7f 40 1a 00 mov.b #26, r15 ;#0x001a 8916: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_AGCCTRL2, P2_AGCCTRL2); // AGC control. 891a: 7e 40 c7 ff mov.b #-57, r14 ;#0xffc7 891e: 7f 40 1b 00 mov.b #27, r15 ;#0x001b 8922: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_AGCCTRL1, P2_AGCCTRL1); // AGC control. 8926: 4e 43 clr.b r14 8928: 7f 40 1c 00 mov.b #28, r15 ;#0x001c 892c: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_AGCCTRL0, P2_AGCCTRL0); // AGC control. 8930: 7e 40 b0 ff mov.b #-80, r14 ;#0xffb0 8934: 7f 40 1d 00 mov.b #29, r15 ;#0x001d 8938: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FREND1, P2_FREND1); // Front end RX configuration. 893c: 7e 40 b6 ff mov.b #-74, r14 ;#0xffb6 8940: 7f 40 21 00 mov.b #33, r15 ;#0x0021 8944: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FREND0, P2_FREND0); // Front end RX configuration. 8948: 7e 40 10 00 mov.b #16, r14 ;#0x0010 894c: 7f 40 22 00 mov.b #34, r15 ;#0x0022 8950: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FSCAL3, P2_FSCAL3); // Frequency synthesizer cal. 8954: 7e 40 ea ff mov.b #-22, r14 ;#0xffea 8958: 7f 40 23 00 mov.b #35, r15 ;#0x0023 895c: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FSCAL2, P2_FSCAL2); // Frequency synthesizer cal. 8960: 7e 40 0a 00 mov.b #10, r14 ;#0x000a 8964: 7f 40 24 00 mov.b #36, r15 ;#0x0024 8968: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FSCAL1, P2_FSCAL1); // Frequency synthesizer cal. 896c: 4e 43 clr.b r14 896e: 7f 40 25 00 mov.b #37, r15 ;#0x0025 8972: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FSCAL0, P2_FSCAL0); // Frequency synthesizer cal. 8976: 7e 40 11 00 mov.b #17, r14 ;#0x0011 897a: 7f 40 26 00 mov.b #38, r15 ;#0x0026 897e: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_FSTEST, P2_FSTEST); // Frequency synthesizer cal. 8982: 7e 40 59 00 mov.b #89, r14 ;#0x0059 8986: 7f 40 29 00 mov.b #41, r15 ;#0x0029 898a: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_TEST2, P2_TEST2); // Various test settings. 898e: 7e 40 88 ff mov.b #-120, r14 ;#0xff88 8992: 7f 40 2c 00 mov.b #44, r15 ;#0x002c 8996: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_TEST1, P2_TEST1); // Various test settings. 899a: 7e 40 31 00 mov.b #49, r14 ;#0x0031 899e: 7f 40 2d 00 mov.b #45, r15 ;#0x002d 89a2: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_TEST0, P2_TEST0); // Various test settings. 89a6: 7e 40 0b 00 mov.b #11, r14 ;#0x000b 89aa: 7f 40 2e 00 mov.b #46, r15 ;#0x002e 89ae: b0 12 b8 8b call #0x8bb8 CC2500_SPI_WRREG(CCxxx0_PATABLE, P2_PATABLE); // Output Power 89b2: 7e 43 mov.b #-1, r14 ;r3 As==11 89b4: 7f 40 3e 00 mov.b #62, r15 ;#0x003e 89b8: b0 12 b8 8b call #0x8bb8 } 89bc: 30 41 ret 000089be : Put the CC2500 chip into listen mode */ void RX_MODE_2500() { CC2500_SPI_STROBE(CCxxx0_SIDLE); 89be: 7f 40 36 00 mov.b #54, r15 ;#0x0036 89c2: b0 12 22 8b call #0x8b22 while(status_2500!=15) //(15)31 for return to TX on complete, see MCSM1 89c6: f2 90 0f 00 cmp.b #15, &0x0210 ;#0x000f 89ca: 10 02 89cc: 08 24 jz $+18 ;abs 0x89de CC2500_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... 89ce: 7f 40 3d 00 mov.b #61, r15 ;#0x003d 89d2: b0 12 22 8b call #0x8b22 */ void RX_MODE_2500() { CC2500_SPI_STROBE(CCxxx0_SIDLE); while(status_2500!=15) //(15)31 for return to TX on complete, see MCSM1 89d6: f2 90 0f 00 cmp.b #15, &0x0210 ;#0x000f 89da: 10 02 89dc: f8 23 jnz $-14 ;abs 0x89ce CC2500_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... CC2500_SPI_STROBE(CCxxx0_SRX);//Recieve Mode 89de: 7f 40 34 00 mov.b #52, r15 ;#0x0034 89e2: b0 12 22 8b call #0x8b22 } 89e6: 30 41 ret 000089e8 : /** Grab the waiting packet from the CC2500 */ char RX_STRING_2500(unsigned char *buffer, unsigned char length) { 89e8: 0b 12 push r11 89ea: 0a 12 push r10 89ec: 09 12 push r9 89ee: 08 12 push r8 89f0: 07 12 push r7 89f2: 06 12 push r6 89f4: 07 4f mov r15, r7 89f6: 48 4e mov.b r14, r8 //interrupt driven, GDO0 had better be low! //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet 89f8: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 89fc: b0 12 5a 8b call #0x8b5a 8a00: 49 4f mov.b r15, r9 real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet 8a02: 7f 40 3b 00 mov.b #59, r15 ;#0x003b 8a06: b0 12 5a 8b call #0x8b5a 8a0a: 46 4f mov.b r15, r6 for(i=0; i < length && i < pkt_length; i++) 8a0c: 48 93 tst.b r8 8a0e: 59 24 jz $+180 ;abs 0x8ac2 8a10: 49 93 tst.b r9 8a12: 5b 24 jz $+184 ;abs 0x8aca 8a14: 0a 47 mov r7, r10 8a16: 4b 43 clr.b r11 8a18: 03 3c jmp $+8 ;abs 0x8a20 8a1a: 1a 53 inc r10 8a1c: 49 9b cmp.b r11, r9 8a1e: 41 24 jz $+132 ;abs 0x8aa2 { buffer[i] = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the byte 8a20: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8a24: b0 12 5a 8b call #0x8b5a 8a28: ca 4f 00 00 mov.b r15, 0(r10) ;0x0000(r10) //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8a2c: 5b 53 inc.b r11 8a2e: 4b 98 cmp.b r8, r11 8a30: f4 23 jnz $-22 ;abs 0x8a1a 8a32: 4e 4b mov.b r11, r14 8a34: 4a 49 mov.b r9, r10 { buffer[i] = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the byte } buffer[i] = '\0';//set the NULL terminator 8a36: 0e 57 add r7, r14 8a38: ce 43 00 00 mov.b #0, 0(r14) ;r3 As==00, 0x0000(r14) RSSI_2500 = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the ESSI 8a3c: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8a40: b0 12 5a 8b call #0x8b5a 8a44: c2 4f 08 02 mov.b r15, &0x0208 LQI_2500 = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//get the CRC 8a48: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf 8a4c: b0 12 5a 8b call #0x8b5a 8a50: c2 4f 09 02 mov.b r15, &0x0209 PKTSTATUS_2500 = CC2500_SPI_RDREG(CCxxx0_PKTSTATUS); 8a54: 7f 40 38 00 mov.b #56, r15 ;#0x0038 8a58: b0 12 5a 8b call #0x8b5a 8a5c: c2 4f 0c 02 mov.b r15, &0x020c if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported 8a60: 4e 46 mov.b r6, r14 8a62: 2a 53 incd r10 8a64: 0e 9a cmp r10, r14 8a66: 03 24 jz $+8 ;abs 0x8a6e LQI_2500 &= ~bit7; //force it to be INVALID! 8a68: f2 f0 7f 00 and.b #127, &0x0209 ;#0x007f 8a6c: 09 02 if (RSSI_2500 >= 128) 8a6e: 5e 42 08 02 mov.b &0x0208,r14 8a72: 4e 93 tst.b r14 8a74: 1a 38 jl $+54 ;abs 0x8aaa RSSI_DBM_2500 = (int)((int )(RSSI_2500 - 256) / 2) - 72; else RSSI_DBM_2500 = (RSSI_2500 / 2) - 72; 8a76: 12 c3 clrc 8a78: 4e 10 rrc.b r14 8a7a: 7e 50 b8 ff add.b #-72, r14 ;#0xffb8 8a7e: c2 4e 06 02 mov.b r14, &0x0206 CC2500_SPI_STROBE(CCxxx0_SFRX); //flush the buffer 8a82: 7f 40 3a 00 mov.b #58, r15 ;#0x003a 8a86: b0 12 22 8b call #0x8b22 CC2500_SPI_STROBE(CCxxx0_SIDLE); //return to IDLE state 8a8a: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8a8e: b0 12 22 8b call #0x8b22 return i; //i = real length } 8a92: 4f 4b mov.b r11, r15 8a94: 36 41 pop r6 8a96: 37 41 pop r7 8a98: 38 41 pop r8 8a9a: 39 41 pop r9 8a9c: 3a 41 pop r10 8a9e: 3b 41 pop r11 8aa0: 30 41 ret //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8aa2: 4a 49 mov.b r9, r10 8aa4: 0e 4a mov r10, r14 8aa6: 4b 49 mov.b r9, r11 8aa8: c6 3f jmp $-114 ;abs 0x8a36 if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported LQI_2500 &= ~bit7; //force it to be INVALID! if (RSSI_2500 >= 128) RSSI_DBM_2500 = (int)((int )(RSSI_2500 - 256) / 2) - 72; 8aaa: 4e 4e mov.b r14, r14 8aac: 0f 4e mov r14, r15 8aae: 3f 50 00 ff add #-256, r15 ;#0xff00 8ab2: 0f 93 tst r15 8ab4: 0e 38 jl $+30 ;abs 0x8ad2 8ab6: 0f 11 rra r15 8ab8: 7f 50 b8 ff add.b #-72, r15 ;#0xffb8 8abc: c2 4f 06 02 mov.b r15, &0x0206 8ac0: e0 3f jmp $-62 ;abs 0x8a82 //if((P2IN&GDO0) == GDO0) //wait wha? // break; pkt_length = CC2500_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CC2500_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) 8ac2: 4b 43 clr.b r11 8ac4: 0e 43 clr r14 8ac6: 4a 49 mov.b r9, r10 8ac8: b6 3f jmp $-146 ;abs 0x8a36 8aca: 4b 43 clr.b r11 8acc: 0e 43 clr r14 8ace: 0a 43 clr r10 8ad0: b2 3f jmp $-154 ;abs 0x8a36 if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported LQI_2500 &= ~bit7; //force it to be INVALID! if (RSSI_2500 >= 128) RSSI_DBM_2500 = (int)((int )(RSSI_2500 - 256) / 2) - 72; 8ad2: 1f 53 inc r15 8ad4: f0 3f jmp $-30 ;abs 0x8ab6 00008ad6 : /** Transmit a string of bytes.on the CC2500 */ void TX_2500_STRING(unsigned char *txstring, unsigned char length) { 8ad6: 0b 12 push r11 8ad8: 0a 12 push r10 8ada: 0b 4f mov r15, r11 8adc: 4a 4e mov.b r14, r10 //unsigned char i; //length += 3; do{ CC2500_SPI_STROBE(CCxxx0_SIDLE);//Idle 8ade: 7f 40 36 00 mov.b #54, r15 ;#0x0036 8ae2: b0 12 22 8b call #0x8b22 }while((status_2500 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle 8ae6: 5f 42 10 02 mov.b &0x0210,r15 8aea: 3f b0 70 00 bit #112, r15 ;#0x0070 8aee: f7 23 jnz $-16 ;abs 0x8ade //CC2500_SPI_WRREG(CCxxx0_TXFIFO, length);//Write the data length first CC2500_SPI_BURST_WRREG(CCxxx0_TXFIFO_BURST, txstring, length); 8af0: 4d 4a mov.b r10, r13 8af2: 0e 4b mov r11, r14 8af4: 7f 40 7f 00 mov.b #127, r15 ;#0x007f 8af8: b0 12 06 8c call #0x8c06 CC2500_SPI_STROBE(CCxxx0_STX); // send tx strobe and TX begins, returns to 15 or 31 when complete (depending on MCSM1) 8afc: 7f 40 35 00 mov.b #53, r15 ;#0x0035 8b00: b0 12 22 8b call #0x8b22 do { CC2500_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... 8b04: 7f 40 3d 00 mov.b #61, r15 ;#0x003d 8b08: b0 12 22 8b call #0x8b22 if(status_2500 == 31) //fast RX mode yay 8b0c: 5f 42 10 02 mov.b &0x0210,r15 8b10: 7f 90 1f 00 cmp.b #31, r15 ;#0x001f 8b14: 03 24 jz $+8 ;abs 0x8b1c break; }while((status_2500 & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //(15)31 for return to TX on complete, see MCSM1 8b16: 3f b0 70 00 bit #112, r15 ;#0x0070 8b1a: f4 23 jnz $-22 ;abs 0x8b04 } 8b1c: 3a 41 pop r10 8b1e: 3b 41 pop r11 8b20: 30 41 ret 00008b22 : Strobe a command to the CC2500 */ void CC2500_SPI_STROBE(char reg) { status_2500=0; P2OUT &= ~CSn_2500; //pull CSn low to activate chip 8b22: f2 f0 fb ff and.b #-5, &0x0029 ;#0xfffb 8b26: 29 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 8b28: 5e 42 18 00 mov.b &0x0018,r14 8b2c: 2e f2 and #4, r14 ;r2 As==10 8b2e: fc 23 jnz $-6 ;abs 0x8b28 P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 8b30: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 8b34: 1b 00 IFG2 &= ~UCB0RXIFG; 8b36: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8b3a: 03 00 UCB0TXBUF = reg; 8b3c: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 8b40: 5f 42 03 00 mov.b &0x0003,r15 8b44: 2f f2 and #4, r15 ;r2 As==10 8b46: fc 27 jz $-6 ;abs 0x8b40 status_2500 = UCB0RXBUF; 8b48: d2 42 6e 00 mov.b &0x006e,&0x0210 8b4c: 10 02 P2OUT |= CSn_2500; //pull CSn high, we're done with the transfer 8b4e: e2 d2 29 00 bis.b #4, &0x0029 ;r2 As==10 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 8b52: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 8b56: 1b 00 } 8b58: 30 41 ret 00008b5a : Read a register from the CC2500 */ char CC2500_SPI_RDREG(char reg) { unsigned char rx=0; if(reg >= 0x30) 8b5a: 7f 90 30 00 cmp.b #48, r15 ;#0x0030 8b5e: 29 38 jl $+84 ;abs 0x8bb2 reg |= 0xC0; 8b60: 7f d0 c0 ff bis.b #-64, r15 ;#0xffc0 else reg |= 0x80; status_2500=0; P2OUT &= ~CSn_2500; //pull CSn low to activate chip 8b64: f2 f0 fb ff and.b #-5, &0x0029 ;#0xfffb 8b68: 29 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 8b6a: 5e 42 18 00 mov.b &0x0018,r14 8b6e: 2e f2 and #4, r14 ;r2 As==10 8b70: fc 23 jnz $-6 ;abs 0x8b6a P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 8b72: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 8b76: 1b 00 IFG2 &= ~UCB0RXIFG; 8b78: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8b7c: 03 00 UCB0TXBUF = reg; 8b7e: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 8b82: 5f 42 03 00 mov.b &0x0003,r15 8b86: 2f f2 and #4, r15 ;r2 As==10 8b88: fc 27 jz $-6 ;abs 0x8b82 status_2500 = UCB0RXBUF; 8b8a: d2 42 6e 00 mov.b &0x006e,&0x0210 8b8e: 10 02 IFG2 &= ~UCB0RXIFG; 8b90: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8b94: 03 00 UCB0TXBUF = 0; 8b96: c2 43 6f 00 mov.b #0, &0x006f ;r3 As==00 while (!(IFG2 & UCB0RXIFG)); 8b9a: 5f 42 03 00 mov.b &0x0003,r15 8b9e: 2f f2 and #4, r15 ;r2 As==10 8ba0: fc 27 jz $-6 ;abs 0x8b9a rx = UCB0RXBUF; 8ba2: 5f 42 6e 00 mov.b &0x006e,r15 P2OUT |= CSn_2500; //pull CSn high, we're done with the transfer 8ba6: e2 d2 29 00 bis.b #4, &0x0029 ;r2 As==10 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 8baa: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 8bae: 1b 00 return rx; } 8bb0: 30 41 ret { unsigned char rx=0; if(reg >= 0x30) reg |= 0xC0; else reg |= 0x80; 8bb2: 7f d0 80 ff bis.b #-128, r15 ;#0xff80 8bb6: d6 3f jmp $-82 ;abs 0x8b64 00008bb8 : { unsigned char dummy; status_2500=0; P2OUT &= ~CSn_2500; //pull CSn low to activate chip 8bb8: f2 f0 fb ff and.b #-5, &0x0029 ;#0xfffb 8bbc: 29 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 8bbe: 5d 42 18 00 mov.b &0x0018,r13 8bc2: 2d f2 and #4, r13 ;r2 As==10 8bc4: fc 23 jnz $-6 ;abs 0x8bbe P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 8bc6: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 8bca: 1b 00 IFG2 &= ~UCB0RXIFG; 8bcc: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8bd0: 03 00 UCB0TXBUF = reg; 8bd2: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 8bd6: 5f 42 03 00 mov.b &0x0003,r15 8bda: 2f f2 and #4, r15 ;r2 As==10 8bdc: fc 27 jz $-6 ;abs 0x8bd6 status_2500 = UCB0RXBUF; 8bde: d2 42 6e 00 mov.b &0x006e,&0x0210 8be2: 10 02 //lil delay //delay(1); IFG2 &= ~UCB0RXIFG; 8be4: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8be8: 03 00 UCB0TXBUF = byte; 8bea: c2 4e 6f 00 mov.b r14, &0x006f while (!(IFG2 & UCB0RXIFG)); 8bee: 5f 42 03 00 mov.b &0x0003,r15 8bf2: 2f f2 and #4, r15 ;r2 As==10 8bf4: fc 27 jz $-6 ;abs 0x8bee dummy = UCB0RXBUF; 8bf6: 5f 42 6e 00 mov.b &0x006e,r15 P2OUT |= CSn_2500; //pull CSn high, we're done with the transfer 8bfa: e2 d2 29 00 bis.b #4, &0x0029 ;r2 As==10 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 8bfe: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 8c02: 1b 00 } 8c04: 30 41 ret 00008c06 : { unsigned char dummy; unsigned int index; status_2500=0; P2OUT &= ~CSn_2500; //pull CSn low to activate chip 8c06: f2 f0 fb ff and.b #-5, &0x0029 ;#0xfffb 8c0a: 29 00 while(P3IN & SOMI_2500); //wait for the CCXX good signal, wait for SOMI to drop low 8c0c: 5c 42 18 00 mov.b &0x0018,r12 8c10: 2c f2 and #4, r12 ;r2 As==10 8c12: fc 23 jnz $-6 ;abs 0x8c0c P3SEL |= UARTB0_SPI_MODULES; //this will bring the clock edge high 8c14: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e 8c18: 1b 00 IFG2 &= ~UCB0RXIFG; 8c1a: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8c1e: 03 00 UCB0TXBUF = reg; 8c20: c2 4f 6f 00 mov.b r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 8c24: 5f 42 03 00 mov.b &0x0003,r15 8c28: 2f f2 and #4, r15 ;r2 As==10 8c2a: fc 27 jz $-6 ;abs 0x8c24 status_2500 = UCB0RXBUF; 8c2c: d2 42 6e 00 mov.b &0x006e,&0x0210 8c30: 10 02 //write out length IFG2 &= ~UCB0RXIFG; 8c32: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8c36: 03 00 UCB0TXBUF = length; 8c38: c2 4d 6f 00 mov.b r13, &0x006f while (!(IFG2 & UCB0RXIFG)); 8c3c: 5f 42 03 00 mov.b &0x0003,r15 8c40: 2f f2 and #4, r15 ;r2 As==10 8c42: fc 27 jz $-6 ;abs 0x8c3c dummy = UCB0RXBUF; 8c44: 5f 42 6e 00 mov.b &0x006e,r15 for(index = 0; index < length; index++) 8c48: 8d 11 sxt r13 8c4a: 11 24 jz $+36 ;abs 0x8c6e 8c4c: 0c 43 clr r12 { IFG2 &= ~UCB0RXIFG; 8c4e: f2 f0 fb ff and.b #-5, &0x0003 ;#0xfffb 8c52: 03 00 /** Write a register from the CC2500 */ void CC2500_SPI_BURST_WRREG(char reg, char *buf, char length) 8c54: 0f 4e mov r14, r15 8c56: 0f 5c add r12, r15 for(index = 0; index < length; index++) { IFG2 &= ~UCB0RXIFG; UCB0TXBUF = buf[index]; 8c58: e2 4f 6f 00 mov.b @r15, &0x006f while (!(IFG2 & UCB0RXIFG)); 8c5c: 5f 42 03 00 mov.b &0x0003,r15 8c60: 2f f2 and #4, r15 ;r2 As==10 8c62: fc 27 jz $-6 ;abs 0x8c5c dummy = UCB0RXBUF; 8c64: 5f 42 6e 00 mov.b &0x006e,r15 UCB0TXBUF = length; while (!(IFG2 & UCB0RXIFG)); dummy = UCB0RXBUF; for(index = 0; index < length; index++) 8c68: 1c 53 inc r12 8c6a: 0c 9d cmp r13, r12 8c6c: f0 2b jnc $-30 ;abs 0x8c4e UCB0TXBUF = buf[index]; while (!(IFG2 & UCB0RXIFG)); dummy = UCB0RXBUF; } P2OUT |= CSn_2500; //pull CSn high, we're done with the transfer 8c6e: e2 d2 29 00 bis.b #4, &0x0029 ;r2 As==10 P3SEL &= ~UARTB0_SPI_MODULES; //take the pins back out of SPI mode 8c72: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 8c76: 1b 00 } 8c78: 30 41 ret 00008c7a <__udivhi3>: 8c7a: 7c 40 10 00 mov.b #16, r12 ;#0x0010 8c7e: 0d 4e mov r14, r13 8c80: 0e 43 clr r14 8c82: 0f 5f rla r15 8c84: 0e 6e rlc r14 8c86: 0e 9d cmp r13, r14 8c88: 02 28 jnc $+6 ;abs 0x8c8e 8c8a: 0e 8d sub r13, r14 8c8c: 1f d3 bis #1, r15 ;r3 As==01 8c8e: 1c 83 dec r12 8c90: f8 23 jnz $-14 ;abs 0x8c82 8c92: 30 41 ret 00008c94 <__umodhi3>: 8c94: b0 12 7a 8c call #0x8c7a 8c98: 0f 4e mov r14, r15 8c9a: 30 41 ret 00008c9c <__udivsi3>: 8c9c: 0b 12 push r11 8c9e: 0a 12 push r10 8ca0: 09 12 push r9 8ca2: 79 40 20 00 mov.b #32, r9 ;#0x0020 8ca6: 0a 4c mov r12, r10 8ca8: 0b 4d mov r13, r11 8caa: 0c 43 clr r12 8cac: 0d 43 clr r13 8cae: 0e 5e rla r14 8cb0: 0f 6f rlc r15 8cb2: 0c 6c rlc r12 8cb4: 0d 6d rlc r13 8cb6: 0d 9b cmp r11, r13 8cb8: 06 28 jnc $+14 ;abs 0x8cc6 8cba: 02 20 jnz $+6 ;abs 0x8cc0 8cbc: 0c 9a cmp r10, r12 8cbe: 03 28 jnc $+8 ;abs 0x8cc6 8cc0: 0c 8a sub r10, r12 8cc2: 0d 7b subc r11, r13 8cc4: 1e d3 bis #1, r14 ;r3 As==01 8cc6: 19 83 dec r9 8cc8: f2 23 jnz $-26 ;abs 0x8cae 8cca: 39 41 pop r9 8ccc: 3a 41 pop r10 8cce: 3b 41 pop r11 8cd0: 30 41 ret 00008cd2 <__umodsi3>: 8cd2: b0 12 9c 8c call #0x8c9c 8cd6: 0e 4c mov r12, r14 8cd8: 0f 4d mov r13, r15 8cda: 30 41 ret 00008cdc <__divsf3>: 8cdc: 0b 12 push r11 8cde: 0a 12 push r10 8ce0: 09 12 push r9 8ce2: 08 12 push r8 8ce4: 07 12 push r7 8ce6: 31 50 e8 ff add #-24, r1 ;#0xffe8 8cea: 81 4e 04 00 mov r14, 4(r1) ;0x0004(r1) 8cee: 81 4f 06 00 mov r15, 6(r1) ;0x0006(r1) 8cf2: 81 4c 00 00 mov r12, 0(r1) ;0x0000(r1) 8cf6: 81 4d 02 00 mov r13, 2(r1) ;0x0002(r1) 8cfa: 0e 41 mov r1, r14 8cfc: 3e 50 10 00 add #16, r14 ;#0x0010 8d00: 0f 41 mov r1, r15 8d02: 2f 52 add #4, r15 ;r2 As==10 8d04: b0 12 b2 91 call #0x91b2 8d08: 0e 41 mov r1, r14 8d0a: 3e 52 add #8, r14 ;r2 As==11 8d0c: 0f 41 mov r1, r15 8d0e: b0 12 b2 91 call #0x91b2 8d12: 5f 41 10 00 mov.b 16(r1), r15 ;0x0010(r1) 8d16: 6f 93 cmp.b #2, r15 ;r3 As==10 8d18: 5d 28 jnc $+188 ;abs 0x8dd4 8d1a: 5e 41 08 00 mov.b 8(r1), r14 ;0x0008(r1) 8d1e: 6e 93 cmp.b #2, r14 ;r3 As==10 8d20: 82 28 jnc $+262 ;abs 0x8e26 8d22: d1 e1 09 00 xor.b 9(r1), 17(r1) ;0x0009(r1), 0x0011(r1) 8d26: 11 00 8d28: 6f 92 cmp.b #4, r15 ;r2 As==10 8d2a: 58 24 jz $+178 ;abs 0x8ddc 8d2c: 6f 93 cmp.b #2, r15 ;r3 As==10 8d2e: 56 24 jz $+174 ;abs 0x8ddc 8d30: 6e 92 cmp.b #4, r14 ;r2 As==10 8d32: 6f 24 jz $+224 ;abs 0x8e12 8d34: 6e 93 cmp.b #2, r14 ;r3 As==10 8d36: 4c 24 jz $+154 ;abs 0x8dd0 8d38: 1d 41 12 00 mov 18(r1), r13 ;0x0012(r1) 8d3c: 1d 81 0a 00 sub 10(r1), r13 ;0x000a(r1) 8d40: 81 4d 12 00 mov r13, 18(r1) ;0x0012(r1) 8d44: 1e 41 14 00 mov 20(r1), r14 ;0x0014(r1) 8d48: 1f 41 16 00 mov 22(r1), r15 ;0x0016(r1) 8d4c: 18 41 0c 00 mov 12(r1), r8 ;0x000c(r1) 8d50: 19 41 0e 00 mov 14(r1), r9 ;0x000e(r1) 8d54: 0f 99 cmp r9, r15 8d56: 1e 2c jc $+62 ;abs 0x8d94 8d58: 0e 5e rla r14 8d5a: 0f 6f rlc r15 8d5c: 3d 53 add #-1, r13 ;r3 As==11 8d5e: 81 4d 12 00 mov r13, 18(r1) ;0x0012(r1) 8d62: 37 40 1f 00 mov #31, r7 ;#0x001f 8d66: 0c 43 clr r12 8d68: 3d 40 00 40 mov #16384, r13 ;#0x4000 8d6c: 0a 43 clr r10 8d6e: 0b 43 clr r11 8d70: 0b 3c jmp $+24 ;abs 0x8d88 8d72: 0a dc bis r12, r10 8d74: 0b dd bis r13, r11 8d76: 0e 88 sub r8, r14 8d78: 0f 79 subc r9, r15 8d7a: 12 c3 clrc 8d7c: 0d 10 rrc r13 8d7e: 0c 10 rrc r12 8d80: 0e 5e rla r14 8d82: 0f 6f rlc r15 8d84: 37 53 add #-1, r7 ;r3 As==11 8d86: 0b 24 jz $+24 ;abs 0x8d9e 8d88: 0f 99 cmp r9, r15 8d8a: f7 2b jnc $-16 ;abs 0x8d7a 8d8c: f2 23 jnz $-26 ;abs 0x8d72 8d8e: 0e 98 cmp r8, r14 8d90: f4 2b jnc $-22 ;abs 0x8d7a 8d92: ef 3f jmp $-32 ;abs 0x8d72 8d94: 09 9f cmp r15, r9 8d96: e5 2b jnc $-52 ;abs 0x8d62 8d98: 0e 98 cmp r8, r14 8d9a: e3 2f jc $-56 ;abs 0x8d62 8d9c: dd 3f jmp $-68 ;abs 0x8d58 8d9e: 0c 4a mov r10, r12 8da0: 0d 4b mov r11, r13 8da2: 3c f0 7f 00 and #127, r12 ;#0x007f 8da6: 0d f3 and #0, r13 ;r3 As==00 8da8: 3c 90 40 00 cmp #64, r12 ;#0x0040 8dac: 1c 24 jz $+58 ;abs 0x8de6 8dae: 81 4a 14 00 mov r10, 20(r1) ;0x0014(r1) 8db2: 81 4b 16 00 mov r11, 22(r1) ;0x0016(r1) 8db6: 0f 41 mov r1, r15 8db8: 3f 50 10 00 add #16, r15 ;#0x0010 8dbc: b0 12 d4 8f call #0x8fd4 8dc0: 31 50 18 00 add #24, r1 ;#0x0018 8dc4: 37 41 pop r7 8dc6: 38 41 pop r8 8dc8: 39 41 pop r9 8dca: 3a 41 pop r10 8dcc: 3b 41 pop r11 8dce: 30 41 ret 8dd0: e1 42 10 00 mov.b #4, 16(r1) ;r2 As==10, 0x0010(r1) 8dd4: 0f 41 mov r1, r15 8dd6: 3f 50 10 00 add #16, r15 ;#0x0010 8dda: f0 3f jmp $-30 ;abs 0x8dbc 8ddc: 4f 9e cmp.b r14, r15 8dde: fa 23 jnz $-10 ;abs 0x8dd4 8de0: 3f 40 88 a0 mov #-24440,r15 ;#0xa088 8de4: eb 3f jmp $-40 ;abs 0x8dbc 8de6: 0d 93 tst r13 8de8: e2 23 jnz $-58 ;abs 0x8dae 8dea: 0c 4a mov r10, r12 8dec: 0d 4b mov r11, r13 8dee: 3c f0 80 00 and #128, r12 ;#0x0080 8df2: 0d f3 and #0, r13 ;r3 As==00 8df4: 0c 93 tst r12 8df6: db 23 jnz $-72 ;abs 0x8dae 8df8: 0d 93 tst r13 8dfa: d9 23 jnz $-76 ;abs 0x8dae 8dfc: 0e 93 tst r14 8dfe: 02 20 jnz $+6 ;abs 0x8e04 8e00: 0f 93 tst r15 8e02: d5 27 jz $-84 ;abs 0x8dae 8e04: 3a 50 40 00 add #64, r10 ;#0x0040 8e08: 0b 63 adc r11 8e0a: 3a f0 80 ff and #-128, r10 ;#0xff80 8e0e: 3b f3 and #-1, r11 ;r3 As==11 8e10: ce 3f jmp $-98 ;abs 0x8dae 8e12: 81 43 14 00 mov #0, 20(r1) ;r3 As==00, 0x0014(r1) 8e16: 81 43 16 00 mov #0, 22(r1) ;r3 As==00, 0x0016(r1) 8e1a: 81 43 12 00 mov #0, 18(r1) ;r3 As==00, 0x0012(r1) 8e1e: 0f 41 mov r1, r15 8e20: 3f 50 10 00 add #16, r15 ;#0x0010 8e24: cb 3f jmp $-104 ;abs 0x8dbc 8e26: 0f 41 mov r1, r15 8e28: 3f 52 add #8, r15 ;r2 As==11 8e2a: c8 3f jmp $-110 ;abs 0x8dbc 00008e2c <__floatsisf>: 8e2c: 0b 12 push r11 8e2e: 0a 12 push r10 8e30: 31 82 sub #8, r1 ;r2 As==11 8e32: f1 40 03 00 mov.b #3, 0(r1) ;#0x0003, 0x0000(r1) 8e36: 00 00 8e38: 0d 4f mov r15, r13 8e3a: 0d 5d rla r13 8e3c: 0d 43 clr r13 8e3e: 0d 6d rlc r13 8e40: 4c 4d mov.b r13, r12 8e42: c1 4d 01 00 mov.b r13, 1(r1) ;0x0001(r1) 8e46: 0e 93 tst r14 8e48: 0b 20 jnz $+24 ;abs 0x8e60 8e4a: 0f 93 tst r15 8e4c: 09 20 jnz $+20 ;abs 0x8e60 8e4e: e1 43 00 00 mov.b #2, 0(r1) ;r3 As==10, 0x0000(r1) 8e52: 0f 41 mov r1, r15 8e54: b0 12 d4 8f call #0x8fd4 8e58: 31 52 add #8, r1 ;r2 As==11 8e5a: 3a 41 pop r10 8e5c: 3b 41 pop r11 8e5e: 30 41 ret 8e60: b1 40 1e 00 mov #30, 2(r1) ;#0x001e, 0x0002(r1) 8e64: 02 00 8e66: 4c 93 tst.b r12 8e68: 1b 20 jnz $+56 ;abs 0x8ea0 8e6a: 0a 4e mov r14, r10 8e6c: 0b 4f mov r15, r11 8e6e: 81 4a 04 00 mov r10, 4(r1) ;0x0004(r1) 8e72: 81 4b 06 00 mov r11, 6(r1) ;0x0006(r1) 8e76: 0e 4a mov r10, r14 8e78: 0f 4b mov r11, r15 8e7a: b0 12 62 8f call #0x8f62 8e7e: 3f 53 add #-1, r15 ;r3 As==11 8e80: 1f 93 cmp #1, r15 ;r3 As==01 8e82: e7 3b jl $-48 ;abs 0x8e52 8e84: 81 4a 04 00 mov r10, 4(r1) ;0x0004(r1) 8e88: 81 4b 06 00 mov r11, 6(r1) ;0x0006(r1) 8e8c: 4e 4f mov.b r15, r14 8e8e: 7e f0 1f 00 and.b #31, r14 ;#0x001f 8e92: 0f 20 jnz $+32 ;abs 0x8eb2 8e94: 3e 40 1e 00 mov #30, r14 ;#0x001e 8e98: 0e 8f sub r15, r14 8e9a: 81 4e 02 00 mov r14, 2(r1) ;0x0002(r1) 8e9e: d9 3f jmp $-76 ;abs 0x8e52 8ea0: 0e 93 tst r14 8ea2: 10 24 jz $+34 ;abs 0x8ec4 8ea4: 0a 4e mov r14, r10 8ea6: 0b 4f mov r15, r11 8ea8: 3a e3 inv r10 8eaa: 3b e3 inv r11 8eac: 1a 53 inc r10 8eae: 0b 63 adc r11 8eb0: de 3f jmp $-66 ;abs 0x8e6e 8eb2: 91 51 04 00 rla 4(r1) ;0x0004(r1) 8eb6: 04 00 8eb8: 91 61 06 00 rlc 6(r1) ;0x0006(r1) 8ebc: 06 00 8ebe: 7e 53 add.b #-1, r14 ;r3 As==11 8ec0: f8 23 jnz $-14 ;abs 0x8eb2 8ec2: e8 3f jmp $-46 ;abs 0x8e94 8ec4: 3f 90 00 80 cmp #-32768,r15 ;#0x8000 8ec8: ed 23 jnz $-36 ;abs 0x8ea4 8eca: 0e 43 clr r14 8ecc: 3f 40 00 cf mov #-12544,r15 ;#0xcf00 8ed0: c3 3f jmp $-120 ;abs 0x8e58 00008ed2 <__fixsfsi>: 8ed2: 31 50 f4 ff add #-12, r1 ;#0xfff4 8ed6: 81 4e 00 00 mov r14, 0(r1) ;0x0000(r1) 8eda: 81 4f 02 00 mov r15, 2(r1) ;0x0002(r1) 8ede: 0e 41 mov r1, r14 8ee0: 2e 52 add #4, r14 ;r2 As==10 8ee2: 0f 41 mov r1, r15 8ee4: b0 12 b2 91 call #0x91b2 8ee8: 5f 41 04 00 mov.b 4(r1), r15 ;0x0004(r1) 8eec: 6f 93 cmp.b #2, r15 ;r3 As==10 8eee: 28 24 jz $+82 ;abs 0x8f40 8ef0: 27 28 jnc $+80 ;abs 0x8f40 8ef2: 6f 92 cmp.b #4, r15 ;r2 As==10 8ef4: 07 24 jz $+16 ;abs 0x8f04 8ef6: 1d 41 06 00 mov 6(r1), r13 ;0x0006(r1) 8efa: 0d 93 tst r13 8efc: 21 38 jl $+68 ;abs 0x8f40 8efe: 3d 90 1f 00 cmp #31, r13 ;#0x001f 8f02: 09 38 jl $+20 ;abs 0x8f16 8f04: c1 93 05 00 tst.b 5(r1) ;0x0005(r1) 8f08: 26 20 jnz $+78 ;abs 0x8f56 8f0a: 3e 43 mov #-1, r14 ;r3 As==11 8f0c: 3f 40 ff 7f mov #32767, r15 ;#0x7fff 8f10: 31 50 0c 00 add #12, r1 ;#0x000c 8f14: 30 41 ret 8f16: 1e 41 08 00 mov 8(r1), r14 ;0x0008(r1) 8f1a: 1f 41 0a 00 mov 10(r1), r15 ;0x000a(r1) 8f1e: 3c 40 1e 00 mov #30, r12 ;#0x001e 8f22: 4c 8d sub.b r13, r12 8f24: 4d 4c mov.b r12, r13 8f26: 7d f0 1f 00 and.b #31, r13 ;#0x001f 8f2a: 0f 20 jnz $+32 ;abs 0x8f4a 8f2c: c1 93 05 00 tst.b 5(r1) ;0x0005(r1) 8f30: ef 27 jz $-32 ;abs 0x8f10 8f32: 3e e3 inv r14 8f34: 3f e3 inv r15 8f36: 1e 53 inc r14 8f38: 0f 63 adc r15 8f3a: 31 50 0c 00 add #12, r1 ;#0x000c 8f3e: 30 41 ret 8f40: 0e 43 clr r14 8f42: 0f 43 clr r15 8f44: 31 50 0c 00 add #12, r1 ;#0x000c 8f48: 30 41 ret 8f4a: 12 c3 clrc 8f4c: 0f 10 rrc r15 8f4e: 0e 10 rrc r14 8f50: 7d 53 add.b #-1, r13 ;r3 As==11 8f52: fb 23 jnz $-8 ;abs 0x8f4a 8f54: eb 3f jmp $-40 ;abs 0x8f2c 8f56: 0e 43 clr r14 8f58: 3f 40 00 80 mov #-32768,r15 ;#0x8000 8f5c: 31 50 0c 00 add #12, r1 ;#0x000c 8f60: 30 41 ret 00008f62 <__clzsi2>: 8f62: 0b 12 push r11 8f64: 0a 12 push r10 8f66: 09 12 push r9 8f68: 1f 93 cmp #1, r15 ;r3 As==01 8f6a: 17 2c jc $+48 ;abs 0x8f9a 8f6c: 3e 90 00 01 cmp #256, r14 ;#0x0100 8f70: 2c 28 jnc $+90 ;abs 0x8fca 8f72: 3a 40 18 00 mov #24, r10 ;#0x0018 8f76: 0b 43 clr r11 8f78: 39 42 mov #8, r9 ;r2 As==11 8f7a: 0c 4e mov r14, r12 8f7c: 0d 4f mov r15, r13 8f7e: 4f 49 mov.b r9, r15 8f80: 4f 93 tst.b r15 8f82: 17 20 jnz $+48 ;abs 0x8fb2 8f84: 3c 50 90 a0 add #-24432,r12 ;#0xa090 8f88: 6e 4c mov.b @r12, r14 8f8a: 0f 43 clr r15 8f8c: 0a 8e sub r14, r10 8f8e: 0b 7f subc r15, r11 8f90: 0f 4a mov r10, r15 8f92: 39 41 pop r9 8f94: 3a 41 pop r10 8f96: 3b 41 pop r11 8f98: 30 41 ret 8f9a: 3f 90 00 01 cmp #256, r15 ;#0x0100 8f9e: 0f 28 jnc $+32 ;abs 0x8fbe 8fa0: 3a 42 mov #8, r10 ;r2 As==11 8fa2: 0b 43 clr r11 8fa4: 39 40 18 00 mov #24, r9 ;#0x0018 8fa8: 0c 4e mov r14, r12 8faa: 0d 4f mov r15, r13 8fac: 4f 49 mov.b r9, r15 8fae: 4f 93 tst.b r15 8fb0: e9 27 jz $-44 ;abs 0x8f84 8fb2: 12 c3 clrc 8fb4: 0d 10 rrc r13 8fb6: 0c 10 rrc r12 8fb8: 7f 53 add.b #-1, r15 ;r3 As==11 8fba: fb 23 jnz $-8 ;abs 0x8fb2 8fbc: e3 3f jmp $-56 ;abs 0x8f84 8fbe: 3a 40 10 00 mov #16, r10 ;#0x0010 8fc2: 0b 43 clr r11 8fc4: 39 40 10 00 mov #16, r9 ;#0x0010 8fc8: ef 3f jmp $-32 ;abs 0x8fa8 8fca: 3a 40 20 00 mov #32, r10 ;#0x0020 8fce: 0b 43 clr r11 8fd0: 09 43 clr r9 8fd2: ea 3f jmp $-42 ;abs 0x8fa8 00008fd4 <__pack_f>: 8fd4: 0b 12 push r11 8fd6: 0a 12 push r10 8fd8: 09 12 push r9 8fda: 08 12 push r8 8fdc: 07 12 push r7 8fde: 0d 4f mov r15, r13 8fe0: 1e 4f 04 00 mov 4(r15), r14 ;0x0004(r15) 8fe4: 1f 4f 06 00 mov 6(r15), r15 ;0x0006(r15) 8fe8: 5a 4d 01 00 mov.b 1(r13), r10 ;0x0001(r13) 8fec: 6c 4d mov.b @r13, r12 8fee: 6c 93 cmp.b #2, r12 ;r3 As==10 8ff0: 70 28 jnc $+226 ;abs 0x90d2 8ff2: 6c 92 cmp.b #4, r12 ;r2 As==10 8ff4: 6a 24 jz $+214 ;abs 0x90ca 8ff6: 6c 93 cmp.b #2, r12 ;r3 As==10 8ff8: 36 24 jz $+110 ;abs 0x9066 8ffa: 0e 93 tst r14 8ffc: 32 24 jz $+102 ;abs 0x9062 8ffe: 1b 4d 02 00 mov 2(r13), r11 ;0x0002(r13) 9002: 3b 90 82 ff cmp #-126, r11 ;#0xff82 9006: 6d 38 jl $+220 ;abs 0x90e2 9008: 3b 90 80 00 cmp #128, r11 ;#0x0080 900c: 5e 34 jge $+190 ;abs 0x90ca 900e: 0c 4e mov r14, r12 9010: 0d 4f mov r15, r13 9012: 3c f0 7f 00 and #127, r12 ;#0x007f 9016: 0d f3 and #0, r13 ;r3 As==00 9018: 3c 90 40 00 cmp #64, r12 ;#0x0040 901c: 40 24 jz $+130 ;abs 0x909e 901e: 3e 50 3f 00 add #63, r14 ;#0x003f 9022: 0f 63 adc r15 9024: 0f 93 tst r15 9026: 4a 38 jl $+150 ;abs 0x90bc 9028: 0d 4b mov r11, r13 902a: 3d 50 7f 00 add #127, r13 ;#0x007f 902e: 12 c3 clrc 9030: 0f 10 rrc r15 9032: 0e 10 rrc r14 9034: 12 c3 clrc 9036: 0f 10 rrc r15 9038: 0e 10 rrc r14 903a: 12 c3 clrc 903c: 0f 10 rrc r15 903e: 0e 10 rrc r14 9040: 12 c3 clrc 9042: 0f 10 rrc r15 9044: 0e 10 rrc r14 9046: 12 c3 clrc 9048: 0f 10 rrc r15 904a: 0e 10 rrc r14 904c: 12 c3 clrc 904e: 0f 10 rrc r15 9050: 0e 10 rrc r14 9052: 12 c3 clrc 9054: 0f 10 rrc r15 9056: 0e 10 rrc r14 9058: 3e f3 and #-1, r14 ;r3 As==11 905a: 3f f0 7f 00 and #127, r15 ;#0x007f 905e: 4d 4d mov.b r13, r13 9060: 05 3c jmp $+12 ;abs 0x906c 9062: 0f 93 tst r15 9064: cc 23 jnz $-102 ;abs 0x8ffe 9066: 4d 43 clr.b r13 9068: 0e 43 clr r14 906a: 0f 43 clr r15 906c: 4d 4d mov.b r13, r13 906e: 0d 5d rla r13 9070: 0d 5d rla r13 9072: 0d 5d rla r13 9074: 0d 5d rla r13 9076: 0d 5d rla r13 9078: 0d 5d rla r13 907a: 0d 5d rla r13 907c: 0c 4f mov r15, r12 907e: 3c f0 7f 00 and #127, r12 ;#0x007f 9082: 0c dd bis r13, r12 9084: 4f 4a mov.b r10, r15 9086: 0f 11 rra r15 9088: 0f 43 clr r15 908a: 0f 10 rrc r15 908c: 0d 4c mov r12, r13 908e: 0d df bis r15, r13 9090: 0f 4d mov r13, r15 9092: 37 41 pop r7 9094: 38 41 pop r8 9096: 39 41 pop r9 9098: 3a 41 pop r10 909a: 3b 41 pop r11 909c: 30 41 ret 909e: 0d 93 tst r13 90a0: be 23 jnz $-130 ;abs 0x901e 90a2: 0c 4e mov r14, r12 90a4: 0d 4f mov r15, r13 90a6: 3c f0 80 00 and #128, r12 ;#0x0080 90aa: 0d f3 and #0, r13 ;r3 As==00 90ac: 0c 93 tst r12 90ae: 02 20 jnz $+6 ;abs 0x90b4 90b0: 0d 93 tst r13 90b2: b8 27 jz $-142 ;abs 0x9024 90b4: 3e 50 40 00 add #64, r14 ;#0x0040 90b8: 0f 63 adc r15 90ba: b4 3f jmp $-150 ;abs 0x9024 90bc: 12 c3 clrc 90be: 0f 10 rrc r15 90c0: 0e 10 rrc r14 90c2: 0d 4b mov r11, r13 90c4: 3d 50 80 00 add #128, r13 ;#0x0080 90c8: b2 3f jmp $-154 ;abs 0x902e 90ca: 7d 43 mov.b #-1, r13 ;r3 As==11 90cc: 0e 43 clr r14 90ce: 0f 43 clr r15 90d0: cd 3f jmp $-100 ;abs 0x906c 90d2: 0e d3 bis #0, r14 ;r3 As==00 90d4: 3f d0 10 00 bis #16, r15 ;#0x0010 90d8: 3e f3 and #-1, r14 ;r3 As==11 90da: 3f f0 7f 00 and #127, r15 ;#0x007f 90de: 7d 43 mov.b #-1, r13 ;r3 As==11 90e0: c5 3f jmp $-116 ;abs 0x906c 90e2: 37 40 82 ff mov #-126, r7 ;#0xff82 90e6: 07 8b sub r11, r7 90e8: 37 90 1a 00 cmp #26, r7 ;#0x001a 90ec: 4f 34 jge $+160 ;abs 0x918c 90ee: 0c 4e mov r14, r12 90f0: 0d 4f mov r15, r13 90f2: 4b 47 mov.b r7, r11 90f4: 7b f0 1f 00 and.b #31, r11 ;#0x001f 90f8: 05 24 jz $+12 ;abs 0x9104 90fa: 12 c3 clrc 90fc: 0d 10 rrc r13 90fe: 0c 10 rrc r12 9100: 7b 53 add.b #-1, r11 ;r3 As==11 9102: fb 23 jnz $-8 ;abs 0x90fa 9104: 18 43 mov #1, r8 ;r3 As==01 9106: 09 43 clr r9 9108: 77 f0 1f 00 and.b #31, r7 ;#0x001f 910c: 04 24 jz $+10 ;abs 0x9116 910e: 08 58 rla r8 9110: 09 69 rlc r9 9112: 77 53 add.b #-1, r7 ;r3 As==11 9114: fc 23 jnz $-6 ;abs 0x910e 9116: 38 53 add #-1, r8 ;r3 As==11 9118: 39 63 addc #-1, r9 ;r3 As==11 911a: 08 fe and r14, r8 911c: 09 ff and r15, r9 911e: 1e 43 mov #1, r14 ;r3 As==01 9120: 0f 43 clr r15 9122: 08 93 tst r8 9124: 04 20 jnz $+10 ;abs 0x912e 9126: 09 93 tst r9 9128: 02 20 jnz $+6 ;abs 0x912e 912a: 0e 43 clr r14 912c: 0f 43 clr r15 912e: 08 4e mov r14, r8 9130: 09 4f mov r15, r9 9132: 08 dc bis r12, r8 9134: 09 dd bis r13, r9 9136: 0e 48 mov r8, r14 9138: 0f 49 mov r9, r15 913a: 3e f0 7f 00 and #127, r14 ;#0x007f 913e: 0f f3 and #0, r15 ;r3 As==00 9140: 3e 90 40 00 cmp #64, r14 ;#0x0040 9144: 26 24 jz $+78 ;abs 0x9192 9146: 38 50 3f 00 add #63, r8 ;#0x003f 914a: 09 63 adc r9 914c: 0e 48 mov r8, r14 914e: 0f 49 mov r9, r15 9150: 12 c3 clrc 9152: 0f 10 rrc r15 9154: 0e 10 rrc r14 9156: 12 c3 clrc 9158: 0f 10 rrc r15 915a: 0e 10 rrc r14 915c: 12 c3 clrc 915e: 0f 10 rrc r15 9160: 0e 10 rrc r14 9162: 12 c3 clrc 9164: 0f 10 rrc r15 9166: 0e 10 rrc r14 9168: 12 c3 clrc 916a: 0f 10 rrc r15 916c: 0e 10 rrc r14 916e: 12 c3 clrc 9170: 0f 10 rrc r15 9172: 0e 10 rrc r14 9174: 12 c3 clrc 9176: 0f 10 rrc r15 9178: 0e 10 rrc r14 917a: 3e f3 and #-1, r14 ;r3 As==11 917c: 3f f0 7f 00 and #127, r15 ;#0x007f 9180: 5d 43 mov.b #1, r13 ;r3 As==01 9182: 39 90 00 40 cmp #16384, r9 ;#0x4000 9186: 72 2f jc $-282 ;abs 0x906c 9188: 4d 43 clr.b r13 918a: 70 3f jmp $-286 ;abs 0x906c 918c: 08 43 clr r8 918e: 09 43 clr r9 9190: da 3f jmp $-74 ;abs 0x9146 9192: 0f 93 tst r15 9194: d8 23 jnz $-78 ;abs 0x9146 9196: 0e 48 mov r8, r14 9198: 0f 49 mov r9, r15 919a: 3e f0 80 00 and #128, r14 ;#0x0080 919e: 0f f3 and #0, r15 ;r3 As==00 91a0: 0e 93 tst r14 91a2: 04 24 jz $+10 ;abs 0x91ac 91a4: 38 50 40 00 add #64, r8 ;#0x0040 91a8: 09 63 adc r9 91aa: d0 3f jmp $-94 ;abs 0x914c 91ac: 0f 93 tst r15 91ae: ce 27 jz $-98 ;abs 0x914c 91b0: f9 3f jmp $-12 ;abs 0x91a4 000091b2 <__unpack_f>: 91b2: 0b 12 push r11 91b4: 0a 12 push r10 91b6: 2a 4f mov @r15, r10 91b8: 5b 4f 02 00 mov.b 2(r15), r11 ;0x0002(r15) 91bc: 3b f0 7f 00 and #127, r11 ;#0x007f 91c0: 1d 4f 02 00 mov 2(r15), r13 ;0x0002(r15) 91c4: 12 c3 clrc 91c6: 0d 10 rrc r13 91c8: 12 c3 clrc 91ca: 0d 10 rrc r13 91cc: 12 c3 clrc 91ce: 0d 10 rrc r13 91d0: 12 c3 clrc 91d2: 0d 10 rrc r13 91d4: 12 c3 clrc 91d6: 0d 10 rrc r13 91d8: 12 c3 clrc 91da: 0d 10 rrc r13 91dc: 12 c3 clrc 91de: 0d 10 rrc r13 91e0: 4d 4d mov.b r13, r13 91e2: 5f 4f 03 00 mov.b 3(r15), r15 ;0x0003(r15) 91e6: 3f b0 80 00 bit #128, r15 ;#0x0080 91ea: 0f 43 clr r15 91ec: 0f 6f rlc r15 91ee: ce 4f 01 00 mov.b r15, 1(r14) ;0x0001(r14) 91f2: 0d 93 tst r13 91f4: 2d 20 jnz $+92 ;abs 0x9250 91f6: 0a 93 tst r10 91f8: 51 24 jz $+164 ;abs 0x929c 91fa: be 40 82 ff mov #-126, 2(r14) ;#0xff82, 0x0002(r14) 91fe: 02 00 9200: 0c 4a mov r10, r12 9202: 0d 4b mov r11, r13 9204: 0c 5c rla r12 9206: 0d 6d rlc r13 9208: 0c 5c rla r12 920a: 0d 6d rlc r13 920c: 0c 5c rla r12 920e: 0d 6d rlc r13 9210: 0c 5c rla r12 9212: 0d 6d rlc r13 9214: 0c 5c rla r12 9216: 0d 6d rlc r13 9218: 0c 5c rla r12 921a: 0d 6d rlc r13 921c: 0c 5c rla r12 921e: 0d 6d rlc r13 9220: fe 40 03 00 mov.b #3, 0(r14) ;#0x0003, 0x0000(r14) 9224: 00 00 9226: 3d 90 00 40 cmp #16384, r13 ;#0x4000 922a: 0b 2c jc $+24 ;abs 0x9242 922c: 3f 40 81 ff mov #-127, r15 ;#0xff81 9230: 0c 5c rla r12 9232: 0d 6d rlc r13 9234: 0a 4f mov r15, r10 9236: 3f 53 add #-1, r15 ;r3 As==11 9238: 3d 90 00 40 cmp #16384, r13 ;#0x4000 923c: f9 2b jnc $-12 ;abs 0x9230 923e: 8e 4a 02 00 mov r10, 2(r14) ;0x0002(r14) 9242: 8e 4c 04 00 mov r12, 4(r14) ;0x0004(r14) 9246: 8e 4d 06 00 mov r13, 6(r14) ;0x0006(r14) 924a: 3a 41 pop r10 924c: 3b 41 pop r11 924e: 30 41 ret 9250: 3d 90 ff 00 cmp #255, r13 ;#0x00ff 9254: 2a 24 jz $+86 ;abs 0x92aa 9256: 3d 50 81 ff add #-127, r13 ;#0xff81 925a: 8e 4d 02 00 mov r13, 2(r14) ;0x0002(r14) 925e: fe 40 03 00 mov.b #3, 0(r14) ;#0x0003, 0x0000(r14) 9262: 00 00 9264: 0c 4a mov r10, r12 9266: 0d 4b mov r11, r13 9268: 0c 5c rla r12 926a: 0d 6d rlc r13 926c: 0c 5c rla r12 926e: 0d 6d rlc r13 9270: 0c 5c rla r12 9272: 0d 6d rlc r13 9274: 0c 5c rla r12 9276: 0d 6d rlc r13 9278: 0c 5c rla r12 927a: 0d 6d rlc r13 927c: 0c 5c rla r12 927e: 0d 6d rlc r13 9280: 0c 5c rla r12 9282: 0d 6d rlc r13 9284: 0a 4c mov r12, r10 9286: 0b 4d mov r13, r11 9288: 0a d3 bis #0, r10 ;r3 As==00 928a: 3b d0 00 40 bis #16384, r11 ;#0x4000 928e: 8e 4a 04 00 mov r10, 4(r14) ;0x0004(r14) 9292: 8e 4b 06 00 mov r11, 6(r14) ;0x0006(r14) 9296: 3a 41 pop r10 9298: 3b 41 pop r11 929a: 30 41 ret 929c: 0b 93 tst r11 929e: ad 23 jnz $-164 ;abs 0x91fa 92a0: ee 43 00 00 mov.b #2, 0(r14) ;r3 As==10, 0x0000(r14) 92a4: 3a 41 pop r10 92a6: 3b 41 pop r11 92a8: 30 41 ret 92aa: 0a 93 tst r10 92ac: 0c 24 jz $+26 ;abs 0x92c6 92ae: 0c 4a mov r10, r12 92b0: 0d 4b mov r11, r13 92b2: 0c f3 and #0, r12 ;r3 As==00 92b4: 3d f0 10 00 and #16, r13 ;#0x0010 92b8: 0c 93 tst r12 92ba: 02 20 jnz $+6 ;abs 0x92c0 92bc: 0d 93 tst r13 92be: 08 24 jz $+18 ;abs 0x92d0 92c0: de 43 00 00 mov.b #1, 0(r14) ;r3 As==01, 0x0000(r14) 92c4: e4 3f jmp $-54 ;abs 0x928e 92c6: 0b 93 tst r11 92c8: f2 23 jnz $-26 ;abs 0x92ae 92ca: ee 42 00 00 mov.b #4, 0(r14) ;r2 As==10, 0x0000(r14) 92ce: e3 3f jmp $-56 ;abs 0x9296 92d0: ce 43 00 00 mov.b #0, 0(r14) ;r3 As==00, 0x0000(r14) 92d4: dc 3f jmp $-70 ;abs 0x928e 000092d6 : 92d6: 6d 4f mov.b @r15, r13 92d8: 4d 9e cmp.b r14, r13 92da: 05 24 jz $+12 ;abs 0x92e6 92dc: 4d 93 tst.b r13 92de: 02 24 jz $+6 ;abs 0x92e4 92e0: 1f 53 inc r15 92e2: f9 3f jmp $-12 ;abs 0x92d6 92e4: 0f 43 clr r15 92e6: 30 41 ret 000092e8 : 92e8: 0b 12 push r11 92ea: 0d 93 tst r13 92ec: 0a 24 jz $+22 ;abs 0x9302 92ee: 7b 4f mov.b @r15+, r11 92f0: 7c 4e mov.b @r14+, r12 92f2: 4b 9c cmp.b r12, r11 92f4: 04 24 jz $+10 ;abs 0x92fe 92f6: 4f 4b mov.b r11, r15 92f8: 4e 4c mov.b r12, r14 92fa: 0f 8e sub r14, r15 92fc: 03 3c jmp $+8 ;abs 0x9304 92fe: 3d 53 add #-1, r13 ;r3 As==11 9300: f4 3f jmp $-22 ;abs 0x92ea 9302: 0f 43 clr r15 9304: 3b 41 pop r11 9306: 30 41 ret 00009308 : 9308: 0b 12 push r11 930a: 0a 12 push r10 930c: 09 12 push r9 930e: 08 12 push r8 9310: 07 12 push r7 9312: 0d 93 tst r13 9314: 70 24 jz $+226 ;abs 0x93f6 9316: 0f 9e cmp r14, r15 9318: 6e 24 jz $+222 ;abs 0x93f6 931a: 34 2c jc $+106 ;abs 0x9384 931c: 0c 4e mov r14, r12 931e: 0c df bis r15, r12 9320: 1c f3 and #1, r12 ;r3 As==01 9322: 1b 24 jz $+56 ;abs 0x935a 9324: 0c 4e mov r14, r12 9326: 0c ef xor r15, r12 9328: 1c f3 and #1, r12 ;r3 As==01 932a: 07 20 jnz $+16 ;abs 0x933a 932c: 2d 93 cmp #2, r13 ;r3 As==10 932e: 07 28 jnc $+16 ;abs 0x933e 9330: 0b 4e mov r14, r11 9332: 1b f3 and #1, r11 ;r3 As==01 9334: 2c 43 mov #2, r12 ;r3 As==10 9336: 0c 8b sub r11, r12 9338: 03 3c jmp $+8 ;abs 0x9340 933a: 0c 4d mov r13, r12 933c: 01 3c jmp $+4 ;abs 0x9340 933e: 1c 43 mov #1, r12 ;r3 As==01 9340: 0d 8c sub r12, r13 9342: 0a 4c mov r12, r10 9344: 09 4e mov r14, r9 9346: 0b 4f mov r15, r11 9348: fb 49 00 00 mov.b @r9+, 0(r11) ;0x0000(r11) 934c: 1b 53 inc r11 934e: 3a 53 add #-1, r10 ;r3 As==11 9350: fb 23 jnz $-8 ;abs 0x9348 9352: 0a 4f mov r15, r10 9354: 0a 5c add r12, r10 9356: 0e 5c add r12, r14 9358: 01 3c jmp $+4 ;abs 0x935c 935a: 0a 4f mov r15, r10 935c: 0b 4d mov r13, r11 935e: 12 c3 clrc 9360: 0b 10 rrc r11 9362: 0b 24 jz $+24 ;abs 0x937a 9364: 09 4b mov r11, r9 9366: 08 4e mov r14, r8 9368: 0c 4a mov r10, r12 936a: bc 48 00 00 mov @r8+, 0(r12) ;0x0000(r12) 936e: 2c 53 incd r12 9370: 39 53 add #-1, r9 ;r3 As==11 9372: fb 23 jnz $-8 ;abs 0x936a 9374: 0b 5b rla r11 9376: 0e 5b add r11, r14 9378: 0a 5b add r11, r10 937a: 1d f3 and #1, r13 ;r3 As==01 937c: 3c 24 jz $+122 ;abs 0x93f6 937e: ea 4e 00 00 mov.b @r14, 0(r10) ;0x0000(r10) 9382: 39 3c jmp $+116 ;abs 0x93f6 9384: 0e 5d add r13, r14 9386: 0c 4f mov r15, r12 9388: 0c 5d add r13, r12 938a: 0b 4c mov r12, r11 938c: 0b de bis r14, r11 938e: 1b f3 and #1, r11 ;r3 As==01 9390: 1b 24 jz $+56 ;abs 0x93c8 9392: 0b 4c mov r12, r11 9394: 0b ee xor r14, r11 9396: 1b f3 and #1, r11 ;r3 As==01 9398: 06 20 jnz $+14 ;abs 0x93a6 939a: 3d 90 03 00 cmp #3, r13 ;#0x0003 939e: 03 28 jnc $+8 ;abs 0x93a6 93a0: 0b 4e mov r14, r11 93a2: 1b f3 and #1, r11 ;r3 As==01 93a4: 01 3c jmp $+4 ;abs 0x93a8 93a6: 0b 4d mov r13, r11 93a8: 0d 8b sub r11, r13 93aa: 09 4e mov r14, r9 93ac: 0a 4c mov r12, r10 93ae: 08 4b mov r11, r8 93b0: 08 8c sub r12, r8 93b2: 3a 53 add #-1, r10 ;r3 As==11 93b4: 39 53 add #-1, r9 ;r3 As==11 93b6: ea 49 00 00 mov.b @r9, 0(r10) ;0x0000(r10) 93ba: 07 4a mov r10, r7 93bc: 07 58 add r8, r7 93be: f9 23 jnz $-12 ;abs 0x93b2 93c0: 3b e3 inv r11 93c2: 1b 53 inc r11 93c4: 0c 5b add r11, r12 93c6: 0e 5b add r11, r14 93c8: 0b 4d mov r13, r11 93ca: 12 c3 clrc 93cc: 0b 10 rrc r11 93ce: 0e 24 jz $+30 ;abs 0x93ec 93d0: 0a 4b mov r11, r10 93d2: 08 4e mov r14, r8 93d4: 09 4c mov r12, r9 93d6: 28 83 decd r8 93d8: 29 83 decd r9 93da: a9 48 00 00 mov @r8, 0(r9) ;0x0000(r9) 93de: 3a 53 add #-1, r10 ;r3 As==11 93e0: fa 23 jnz $-10 ;abs 0x93d6 93e2: 0a 8b sub r11, r10 93e4: 0b 4a mov r10, r11 93e6: 0b 5b rla r11 93e8: 0e 5b add r11, r14 93ea: 0c 5b add r11, r12 93ec: 1d f3 and #1, r13 ;r3 As==01 93ee: 03 24 jz $+8 ;abs 0x93f6 93f0: dc 4e ff ff mov.b -1(r14),-1(r12) ;0xffff(r14), 0xffff(r12) 93f4: ff ff 93f6: 37 41 pop r7 93f8: 38 41 pop r8 93fa: 39 41 pop r9 93fc: 3a 41 pop r10 93fe: 3b 41 pop r11 9400: 30 41 ret 00009402 : 9402: 0b 12 push r11 9404: 0a 12 push r10 9406: 09 12 push r9 9408: 08 12 push r8 940a: 3d 90 06 00 cmp #6, r13 ;#0x0006 940e: 09 2c jc $+20 ;abs 0x9422 9410: 0c 4f mov r15, r12 9412: 04 3c jmp $+10 ;abs 0x941c 9414: cc 4e 00 00 mov.b r14, 0(r12) ;0x0000(r12) 9418: 1c 53 inc r12 941a: 3d 53 add #-1, r13 ;r3 As==11 941c: 0d 93 tst r13 941e: fa 23 jnz $-10 ;abs 0x9414 9420: 20 3c jmp $+66 ;abs 0x9462 9422: 4e 4e mov.b r14, r14 9424: 4b 4e mov.b r14, r11 9426: 0b 93 tst r11 9428: 03 24 jz $+8 ;abs 0x9430 942a: 0c 4b mov r11, r12 942c: 8c 10 swpb r12 942e: 0b dc bis r12, r11 9430: 1f b3 bit #1, r15 ;r3 As==01 9432: 06 24 jz $+14 ;abs 0x9440 9434: 3d 53 add #-1, r13 ;r3 As==11 9436: cf 4e 00 00 mov.b r14, 0(r15) ;0x0000(r15) 943a: 09 4f mov r15, r9 943c: 19 53 inc r9 943e: 01 3c jmp $+4 ;abs 0x9442 9440: 09 4f mov r15, r9 9442: 0c 4d mov r13, r12 9444: 12 c3 clrc 9446: 0c 10 rrc r12 9448: 0a 49 mov r9, r10 944a: 08 4c mov r12, r8 944c: 8a 4b 00 00 mov r11, 0(r10) ;0x0000(r10) 9450: 2a 53 incd r10 9452: 38 53 add #-1, r8 ;r3 As==11 9454: fb 23 jnz $-8 ;abs 0x944c 9456: 0c 5c rla r12 9458: 0c 59 add r9, r12 945a: 1d f3 and #1, r13 ;r3 As==01 945c: 02 24 jz $+6 ;abs 0x9462 945e: cc 4e 00 00 mov.b r14, 0(r12) ;0x0000(r12) 9462: 38 41 pop r8 9464: 39 41 pop r9 9466: 3a 41 pop r10 9468: 3b 41 pop r11 946a: 30 41 ret 0000946c : 946c: 0b 12 push r11 946e: 0a 12 push r10 9470: 09 12 push r9 9472: 08 12 push r8 9474: 07 12 push r7 9476: 0b 4f mov r15, r11 9478: 69 4e mov.b @r14, r9 947a: 49 93 tst.b r9 947c: 1b 24 jz $+56 ;abs 0x94b4 947e: 0a 4e mov r14, r10 9480: 1a 53 inc r10 9482: 0d 4e mov r14, r13 9484: 1d 53 inc r13 9486: cd 93 00 00 tst.b 0(r13) ;0x0000(r13) 948a: fc 23 jnz $-6 ;abs 0x9484 948c: 07 4d mov r13, r7 948e: 07 8a sub r10, r7 9490: 01 3c jmp $+4 ;abs 0x9494 9492: 0b 48 mov r8, r11 9494: 6f 4b mov.b @r11, r15 9496: 4f 93 tst.b r15 9498: 0c 24 jz $+26 ;abs 0x94b2 949a: 08 4b mov r11, r8 949c: 18 53 inc r8 949e: 4f 99 cmp.b r9, r15 94a0: f8 23 jnz $-14 ;abs 0x9492 94a2: 0d 47 mov r7, r13 94a4: 0e 4a mov r10, r14 94a6: 0f 48 mov r8, r15 94a8: b0 12 3e 9e call #0x9e3e 94ac: 0f 93 tst r15 94ae: f1 23 jnz $-28 ;abs 0x9492 94b0: 01 3c jmp $+4 ;abs 0x94b4 94b2: 0b 43 clr r11 94b4: 0f 4b mov r11, r15 94b6: 37 41 pop r7 94b8: 38 41 pop r8 94ba: 39 41 pop r9 94bc: 3a 41 pop r10 94be: 3b 41 pop r11 94c0: 30 41 ret 000094c2 : 94c2: 0b 12 push r11 94c4: 0e 4f mov r15, r14 94c6: 01 3c jmp $+4 ;abs 0x94ca 94c8: 1e 53 inc r14 94ca: 6f 4e mov.b @r14, r15 94cc: 7f 90 20 00 cmp.b #32, r15 ;#0x0020 94d0: fb 27 jz $-8 ;abs 0x94c8 94d2: 7f 90 09 00 cmp.b #9, r15 ;#0x0009 94d6: f8 27 jz $-14 ;abs 0x94c8 94d8: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a 94dc: f5 27 jz $-20 ;abs 0x94c8 94de: 7f 90 0c 00 cmp.b #12, r15 ;#0x000c 94e2: f2 27 jz $-26 ;abs 0x94c8 94e4: 7f 90 0d 00 cmp.b #13, r15 ;#0x000d 94e8: ef 27 jz $-32 ;abs 0x94c8 94ea: 7f 90 0b 00 cmp.b #11, r15 ;#0x000b 94ee: ec 27 jz $-38 ;abs 0x94c8 94f0: 7f 90 2d 00 cmp.b #45, r15 ;#0x002d 94f4: 03 20 jnz $+8 ;abs 0x94fc 94f6: 1e 53 inc r14 94f8: 1b 43 mov #1, r11 ;r3 As==01 94fa: 05 3c jmp $+12 ;abs 0x9506 94fc: 7f 90 2b 00 cmp.b #43, r15 ;#0x002b 9500: 01 20 jnz $+4 ;abs 0x9504 9502: 1e 53 inc r14 9504: 0b 43 clr r11 9506: 6f 4e mov.b @r14, r15 9508: 8f 11 sxt r15 950a: 3f 50 d0 ff add #-48, r15 ;#0xffd0 950e: 3f 90 0a 00 cmp #10, r15 ;#0x000a 9512: 19 2c jc $+52 ;abs 0x9546 9514: 0d 43 clr r13 9516: 7c 4e mov.b @r14+, r12 9518: 8c 11 sxt r12 951a: 0f 4c mov r12, r15 951c: 3f 50 d0 ff add #-48, r15 ;#0xffd0 9520: 0f 5d add r13, r15 9522: 6d 4e mov.b @r14, r13 9524: 8d 11 sxt r13 9526: 3d 50 d0 ff add #-48, r13 ;#0xffd0 952a: 3d 90 0a 00 cmp #10, r13 ;#0x000a 952e: 06 2c jc $+14 ;abs 0x953c 9530: 0f 5f rla r15 9532: 0d 4f mov r15, r13 9534: 0d 5d rla r13 9536: 0d 5d rla r13 9538: 0d 5f add r15, r13 953a: ed 3f jmp $-36 ;abs 0x9516 953c: 0b 93 tst r11 953e: 04 24 jz $+10 ;abs 0x9548 9540: 3f e3 inv r15 9542: 1f 53 inc r15 9544: 01 3c jmp $+4 ;abs 0x9548 9546: 0f 43 clr r15 9548: 3b 41 pop r11 954a: 30 41 ret 0000954c : 954c: 1e 42 04 02 mov &0x0204,r14 9550: 1e 93 cmp #1, r14 ;r3 As==01 9552: 0b 38 jl $+24 ;abs 0x956a 9554: 1d 42 02 02 mov &0x0202,r13 9558: cd 4f 00 00 mov.b r15, 0(r13) ;0x0000(r13) 955c: 1d 53 inc r13 955e: 82 4d 02 02 mov r13, &0x0202 9562: 3e 53 add #-1, r14 ;r3 As==11 9564: 82 4e 04 02 mov r14, &0x0204 9568: 30 41 ret 956a: 3f 43 mov #-1, r15 ;r3 As==11 956c: 30 41 ret 0000956e : 956e: 0b 12 push r11 9570: 0a 12 push r10 9572: 21 83 decd r1 9574: 81 4e 00 00 mov r14, 0(r1) ;0x0000(r1) 9578: 1a 42 02 02 mov &0x0202,r10 957c: 1b 42 04 02 mov &0x0204,r11 9580: 0d 4e mov r14, r13 9582: 0e 4f mov r15, r14 9584: 3f 40 4c 95 mov #-27316,r15 ;#0x954c 9588: b0 12 a0 97 call #0x97a0 958c: 0f 9b cmp r11, r15 958e: 05 38 jl $+12 ;abs 0x959a 9590: 0e 4a mov r10, r14 9592: 0e 5b add r11, r14 9594: ce 43 ff ff mov.b #0, -1(r14) ;r3 As==00, 0xffff(r14) 9598: 04 3c jmp $+10 ;abs 0x95a2 959a: 1e 42 02 02 mov &0x0202,r14 959e: ce 43 00 00 mov.b #0, 0(r14) ;r3 As==00, 0x0000(r14) 95a2: 21 53 incd r1 95a4: 3a 41 pop r10 95a6: 3b 41 pop r11 95a8: 30 41 ret 000095aa : 95aa: 92 41 02 00 mov 2(r1), &0x0202 ;0x0002(r1) 95ae: 02 02 95b0: b2 40 ff 7f mov #32767, &0x0204 ;#0x7fff 95b4: 04 02 95b6: 0e 41 mov r1, r14 95b8: 3e 50 06 00 add #6, r14 ;#0x0006 95bc: 1f 41 04 00 mov 4(r1), r15 ;0x0004(r1) 95c0: b0 12 6e 95 call #0x956e 95c4: 30 41 ret 000095c6 : 95c6: 92 41 02 00 mov 2(r1), &0x0202 ;0x0002(r1) 95ca: 02 02 95cc: 92 41 04 00 mov 4(r1), &0x0204 ;0x0004(r1) 95d0: 04 02 95d2: 0e 41 mov r1, r14 95d4: 3e 52 add #8, r14 ;r2 As==11 95d6: 1f 41 06 00 mov 6(r1), r15 ;0x0006(r1) 95da: b0 12 6e 95 call #0x956e 95de: 30 41 ret 000095e0 : 95e0: 0c 4e mov r14, r12 95e2: 82 4f 02 02 mov r15, &0x0202 95e6: b2 40 ff 7f mov #32767, &0x0204 ;#0x7fff 95ea: 04 02 95ec: 0e 4d mov r13, r14 95ee: 0f 4c mov r12, r15 95f0: b0 12 6e 95 call #0x956e 95f4: 30 41 ret 000095f6 : 95f6: 82 4f 02 02 mov r15, &0x0202 95fa: 82 4e 04 02 mov r14, &0x0204 95fe: 0e 4c mov r12, r14 9600: 0f 4d mov r13, r15 9602: b0 12 6e 95 call #0x956e 9606: 30 41 ret 00009608 : 9608: 0b 12 push r11 960a: 0a 12 push r10 960c: 09 12 push r9 960e: 08 12 push r8 9610: 07 12 push r7 9612: 06 12 push r6 9614: 05 12 push r5 9616: 04 12 push r4 9618: 31 82 sub #8, r1 ;r2 As==11 961a: 08 4f mov r15, r8 961c: 81 4e 04 00 mov r14, 4(r1) ;0x0004(r1) 9620: 09 4d mov r13, r9 9622: 1f 41 1a 00 mov 26(r1), r15 ;0x001a(r1) 9626: 1d 41 1c 00 mov 28(r1), r13 ;0x001c(r1) 962a: 4c 4d mov.b r13, r12 962c: 04 4d mov r13, r4 962e: 84 10 swpb r4 9630: 45 44 mov.b r4, r5 9632: 4e 4f mov.b r15, r14 9634: 7e b0 40 00 bit.b #64, r14 ;#0x0040 9638: 11 24 jz $+36 ;abs 0x965c 963a: f1 40 30 00 mov.b #48, 0(r1) ;#0x0030, 0x0000(r1) 963e: 00 00 9640: 0e 4f mov r15, r14 9642: 8e 10 swpb r14 9644: 5e f3 and.b #1, r14 ;r3 As==01 9646: 03 24 jz $+8 ;abs 0x964e 9648: 7e 40 58 00 mov.b #88, r14 ;#0x0058 964c: 02 3c jmp $+6 ;abs 0x9652 964e: 7e 40 78 00 mov.b #120, r14 ;#0x0078 9652: c1 4e 01 00 mov.b r14, 1(r1) ;0x0001(r1) 9656: 0c 41 mov r1, r12 9658: 2c 53 incd r12 965a: 0f 3c jmp $+32 ;abs 0x967a 965c: 7e f0 20 00 and.b #32, r14 ;#0x0020 9660: 04 24 jz $+10 ;abs 0x966a 9662: f1 40 30 00 mov.b #48, 0(r1) ;#0x0030, 0x0000(r1) 9666: 00 00 9668: 04 3c jmp $+10 ;abs 0x9672 966a: 4c 93 tst.b r12 966c: 05 24 jz $+12 ;abs 0x9678 966e: c1 4d 00 00 mov.b r13, 0(r1) ;0x0000(r1) 9672: 0c 41 mov r1, r12 9674: 1c 53 inc r12 9676: 01 3c jmp $+4 ;abs 0x967a 9678: 0c 41 mov r1, r12 967a: 0a 4c mov r12, r10 967c: 8c 10 swpb r12 967e: 8c 11 sxt r12 9680: 8c 10 swpb r12 9682: 8c 11 sxt r12 9684: 0b 4c mov r12, r11 9686: 06 41 mov r1, r6 9688: 0c 41 mov r1, r12 968a: 8c 10 swpb r12 968c: 8c 11 sxt r12 968e: 8c 10 swpb r12 9690: 8c 11 sxt r12 9692: 07 4c mov r12, r7 9694: 0a 86 sub r6, r10 9696: 0b 77 subc r7, r11 9698: 0e 4f mov r15, r14 969a: 8e 10 swpb r14 969c: c1 4e 02 00 mov.b r14, 2(r1) ;0x0002(r1) 96a0: 6e f2 and.b #4, r14 ;r2 As==10 96a2: 02 24 jz $+6 ;abs 0x96a8 96a4: 07 45 mov r5, r7 96a6: 01 3c jmp $+4 ;abs 0x96aa 96a8: 37 43 mov #-1, r7 ;r3 As==11 96aa: 4f 4f mov.b r15, r15 96ac: 7f b0 10 00 bit.b #16, r15 ;#0x0010 96b0: 3c 20 jnz $+122 ;abs 0x972a 96b2: 1d 41 04 00 mov 4(r1), r13 ;0x0004(r1) 96b6: 3d 53 add #-1, r13 ;r3 As==11 96b8: 1d 53 inc r13 96ba: cd 93 00 00 tst.b 0(r13) ;0x0000(r13) 96be: fc 23 jnz $-6 ;abs 0x96b8 96c0: 1d 81 04 00 sub 4(r1), r13 ;0x0004(r1) 96c4: 09 9a cmp r10, r9 96c6: 02 28 jnc $+6 ;abs 0x96cc 96c8: 09 8a sub r10, r9 96ca: 01 3c jmp $+4 ;abs 0x96ce 96cc: 09 43 clr r9 96ce: e1 b3 02 00 bit.b #2, 2(r1) ;r3 As==10, 0x0002(r1) 96d2: 05 24 jz $+12 ;abs 0x96de 96d4: 09 95 cmp r5, r9 96d6: 02 28 jnc $+6 ;abs 0x96dc 96d8: 09 85 sub r5, r9 96da: 01 3c jmp $+4 ;abs 0x96de 96dc: 09 43 clr r9 96de: 05 4d mov r13, r5 96e0: 07 9d cmp r13, r7 96e2: 01 2c jc $+4 ;abs 0x96e6 96e4: 05 47 mov r7, r5 96e6: 4f 93 tst.b r15 96e8: 0d 38 jl $+28 ;abs 0x9704 96ea: f1 40 20 00 mov.b #32, 6(r1) ;#0x0020, 0x0006(r1) 96ee: 06 00 96f0: 06 43 clr r6 96f2: 0b 43 clr r11 96f4: 0e 3c jmp $+30 ;abs 0x9712 96f6: 0f 41 mov r1, r15 96f8: 0f 56 add r6, r15 96fa: 6f 4f mov.b @r15, r15 96fc: 8f 11 sxt r15 96fe: 16 53 inc r6 9700: 88 12 call r8 9702: 01 3c jmp $+4 ;abs 0x9706 9704: 06 43 clr r6 9706: 06 9a cmp r10, r6 9708: f6 3b jl $-18 ;abs 0x96f6 970a: 0b 4a mov r10, r11 970c: f1 40 30 00 mov.b #48, 6(r1) ;#0x0030, 0x0006(r1) 9710: 06 00 9712: 05 8b sub r11, r5 9714: 05 3c jmp $+12 ;abs 0x9720 9716: 5f 41 06 00 mov.b 6(r1), r15 ;0x0006(r1) 971a: 8f 11 sxt r15 971c: 88 12 call r8 971e: 1b 53 inc r11 9720: 0f 45 mov r5, r15 9722: 0f 5b add r11, r15 9724: 0f 99 cmp r9, r15 9726: f7 2b jnc $-16 ;abs 0x9716 9728: 0a 3c jmp $+22 ;abs 0x973e 972a: 06 43 clr r6 972c: 0b 43 clr r11 972e: 07 3c jmp $+16 ;abs 0x973e 9730: 1b 53 inc r11 9732: 0f 41 mov r1, r15 9734: 0f 56 add r6, r15 9736: 6f 4f mov.b @r15, r15 9738: 8f 11 sxt r15 973a: 16 53 inc r6 973c: 88 12 call r8 973e: 06 9a cmp r10, r6 9740: f7 3b jl $-16 ;abs 0x9730 9742: e1 b3 02 00 bit.b #2, 2(r1) ;r3 As==10, 0x0002(r1) 9746: 02 24 jz $+6 ;abs 0x974c 9748: 4a 44 mov.b r4, r10 974a: 08 3c jmp $+18 ;abs 0x975c 974c: 1a 41 04 00 mov 4(r1), r10 ;0x0004(r1) 9750: 0a 8b sub r11, r10 9752: 0d 3c jmp $+28 ;abs 0x976e 9754: 3f 40 30 00 mov #48, r15 ;#0x0030 9758: 88 12 call r8 975a: 7a 53 add.b #-1, r10 ;r3 As==11 975c: 4a 93 tst.b r10 975e: fa 23 jnz $-10 ;abs 0x9754 9760: 44 44 mov.b r4, r4 9762: 0b 54 add r4, r11 9764: f3 3f jmp $-24 ;abs 0x974c 9766: 37 53 add #-1, r7 ;r3 As==11 9768: 8f 11 sxt r15 976a: 88 12 call r8 976c: 1b 53 inc r11 976e: 0f 4a mov r10, r15 9770: 0f 5b add r11, r15 9772: 6f 4f mov.b @r15, r15 9774: 4f 93 tst.b r15 9776: 07 24 jz $+16 ;abs 0x9786 9778: 07 93 tst r7 977a: f5 23 jnz $-20 ;abs 0x9766 977c: 04 3c jmp $+10 ;abs 0x9786 977e: 3f 40 20 00 mov #32, r15 ;#0x0020 9782: 88 12 call r8 9784: 1b 53 inc r11 9786: 0b 99 cmp r9, r11 9788: fa 2b jnc $-10 ;abs 0x977e 978a: 0f 4b mov r11, r15 978c: 31 52 add #8, r1 ;r2 As==11 978e: 34 41 pop r4 9790: 35 41 pop r5 9792: 36 41 pop r6 9794: 37 41 pop r7 9796: 38 41 pop r8 9798: 39 41 pop r9 979a: 3a 41 pop r10 979c: 3b 41 pop r11 979e: 30 41 ret 000097a0 : 97a0: 0b 12 push r11 97a2: 0a 12 push r10 97a4: 09 12 push r9 97a6: 08 12 push r8 97a8: 07 12 push r7 97aa: 06 12 push r6 97ac: 05 12 push r5 97ae: 04 12 push r4 97b0: 31 50 b6 ff add #-74, r1 ;#0xffb6 97b4: 81 4f 3a 00 mov r15, 58(r1) ;0x003a(r1) 97b8: 06 4e mov r14, r6 97ba: 05 4d mov r13, r5 97bc: 81 4e 3e 00 mov r14, 62(r1) ;0x003e(r1) 97c0: c1 43 2f 00 mov.b #0, 47(r1) ;r3 As==00, 0x002f(r1) 97c4: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 97c8: c1 43 2e 00 mov.b #0, 46(r1) ;r3 As==00, 0x002e(r1) 97cc: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) 97d0: 81 43 30 00 mov #0, 48(r1) ;r3 As==00, 0x0030(r1) 97d4: 81 43 26 00 mov #0, 38(r1) ;r3 As==00, 0x0026(r1) 97d8: 07 43 clr r7 97da: 81 43 2c 00 mov #0, 44(r1) ;r3 As==00, 0x002c(r1) 97de: 0e 41 mov r1, r14 97e0: 3e 50 1c 00 add #28, r14 ;#0x001c 97e4: 81 4e 1c 00 mov r14, 28(r1) ;0x001c(r1) 97e8: 30 40 1a 9e br #0x9e1a 97ec: 0f 46 mov r6, r15 97ee: 1f 53 inc r15 97f0: 81 4f 40 00 mov r15, 64(r1) ;0x0040(r1) 97f4: 07 93 tst r7 97f6: 1e 20 jnz $+62 ;abs 0x9834 97f8: 7e 90 25 00 cmp.b #37, r14 ;#0x0025 97fc: 13 20 jnz $+40 ;abs 0x9824 97fe: 81 43 00 00 mov #0, 0(r1) ;r3 As==00, 0x0000(r1) 9802: 81 43 02 00 mov #0, 2(r1) ;r3 As==00, 0x0002(r1) 9806: 81 46 3e 00 mov r6, 62(r1) ;0x003e(r1) 980a: c1 43 2f 00 mov.b #0, 47(r1) ;r3 As==00, 0x002f(r1) 980e: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 9812: c1 43 2e 00 mov.b #0, 46(r1) ;r3 As==00, 0x002e(r1) 9816: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) 981a: 81 43 30 00 mov #0, 48(r1) ;r3 As==00, 0x0030(r1) 981e: 30 40 10 9e br #0x9e10 9822: 05 47 mov r7, r5 9824: 8e 11 sxt r14 9826: 0f 4e mov r14, r15 9828: 91 12 3c 00 call 60(r1) ;0x003c(r1) 982c: 91 53 2c 00 inc 44(r1) ;0x002c(r1) 9830: 30 40 f6 9d br #0x9df6 9834: 7e 90 63 00 cmp.b #99, r14 ;#0x0063 9838: c5 24 jz $+396 ;abs 0x99c4 983a: 7e 90 64 00 cmp.b #100, r14 ;#0x0064 983e: 27 34 jge $+80 ;abs 0x988e 9840: 7e 90 30 00 cmp.b #48, r14 ;#0x0030 9844: 94 24 jz $+298 ;abs 0x996e 9846: 7e 90 31 00 cmp.b #49, r14 ;#0x0031 984a: 1a 34 jge $+54 ;abs 0x9880 984c: 7e 90 2a 00 cmp.b #42, r14 ;#0x002a 9850: 77 24 jz $+240 ;abs 0x9940 9852: 7e 90 2b 00 cmp.b #43, r14 ;#0x002b 9856: 0a 34 jge $+22 ;abs 0x986c 9858: 7e 90 23 00 cmp.b #35, r14 ;#0x0023 985c: 42 24 jz $+134 ;abs 0x98e2 985e: 7e 90 25 00 cmp.b #37, r14 ;#0x0025 9862: e0 27 jz $-62 ;abs 0x9824 9864: 7e 90 20 00 cmp.b #32, r14 ;#0x0020 9868: 32 20 jnz $+102 ;abs 0x98ce 986a: 56 3c jmp $+174 ;abs 0x9918 986c: 7e 90 2d 00 cmp.b #45, r14 ;#0x002d 9870: 49 24 jz $+148 ;abs 0x9904 9872: 7e 90 2e 00 cmp.b #46, r14 ;#0x002e 9876: 5b 24 jz $+184 ;abs 0x992e 9878: 7e 90 2b 00 cmp.b #43, r14 ;#0x002b 987c: 28 20 jnz $+82 ;abs 0x98ce 987e: 47 3c jmp $+144 ;abs 0x990e 9880: 7e 90 3a 00 cmp.b #58, r14 ;#0x003a 9884: 8c 38 jl $+282 ;abs 0x999e 9886: 7e 90 58 00 cmp.b #88, r14 ;#0x0058 988a: 21 20 jnz $+68 ;abs 0x98ce 988c: e9 3c jmp $+468 ;abs 0x9a60 988e: 7e 90 6f 00 cmp.b #111, r14 ;#0x006f 9892: 24 24 jz $+74 ;abs 0x98dc 9894: 7e 90 70 00 cmp.b #112, r14 ;#0x0070 9898: 0a 34 jge $+22 ;abs 0x98ae 989a: 7e 90 69 00 cmp.b #105, r14 ;#0x0069 989e: e3 24 jz $+456 ;abs 0x9a66 98a0: 7e 90 6c 00 cmp.b #108, r14 ;#0x006c 98a4: 22 24 jz $+70 ;abs 0x98ea 98a6: 7e 90 64 00 cmp.b #100, r14 ;#0x0064 98aa: 11 20 jnz $+36 ;abs 0x98ce 98ac: dc 3c jmp $+442 ;abs 0x9a66 98ae: 7e 90 73 00 cmp.b #115, r14 ;#0x0073 98b2: 98 24 jz $+306 ;abs 0x99e4 98b4: 7e 90 74 00 cmp.b #116, r14 ;#0x0074 98b8: 04 34 jge $+10 ;abs 0x98c2 98ba: 7e 90 70 00 cmp.b #112, r14 ;#0x0070 98be: 07 20 jnz $+16 ;abs 0x98ce 98c0: b8 3c jmp $+370 ;abs 0x9a32 98c2: 7e 90 75 00 cmp.b #117, r14 ;#0x0075 98c6: d1 24 jz $+420 ;abs 0x9a6a 98c8: 7e 90 78 00 cmp.b #120, r14 ;#0x0078 98cc: d2 24 jz $+422 ;abs 0x9a72 98ce: 19 41 3e 00 mov 62(r1), r9 ;0x003e(r1) 98d2: 18 41 2c 00 mov 44(r1), r8 ;0x002c(r1) 98d6: 08 89 sub r9, r8 98d8: 30 40 e4 9d br #0x9de4 98dc: b1 42 28 00 mov #8, 40(r1) ;r2 As==11, 0x0028(r1) 98e0: cb 3c jmp $+408 ;abs 0x9a78 98e2: f1 d2 00 00 bis.b #8, 0(r1) ;r2 As==11, 0x0000(r1) 98e6: 30 40 14 9e br #0x9e14 98ea: 69 41 mov.b @r1, r9 98ec: 59 f3 and.b #1, r9 ;r3 As==01 98ee: 6e 41 mov.b @r1, r14 98f0: 04 24 jz $+10 ;abs 0x98fa 98f2: 7e f0 fe ff and.b #-2, r14 ;#0xfffe 98f6: 6e d3 bis.b #2, r14 ;r3 As==10 98f8: 01 3c jmp $+4 ;abs 0x98fc 98fa: 5e d3 bis.b #1, r14 ;r3 As==01 98fc: c1 4e 00 00 mov.b r14, 0(r1) ;0x0000(r1) 9900: 30 40 14 9e br #0x9e14 9904: f1 d0 10 00 bis.b #16, 0(r1) ;#0x0010, 0x0000(r1) 9908: 00 00 990a: 30 40 14 9e br #0x9e14 990e: f1 40 2b 00 mov.b #43, 2(r1) ;#0x002b, 0x0002(r1) 9912: 02 00 9914: 30 40 14 9e br #0x9e14 9918: f1 90 2b 00 cmp.b #43, 2(r1) ;#0x002b, 0x0002(r1) 991c: 02 00 991e: 02 20 jnz $+6 ;abs 0x9924 9920: 30 40 14 9e br #0x9e14 9924: f1 40 20 00 mov.b #32, 2(r1) ;#0x0020, 0x0002(r1) 9928: 02 00 992a: 30 40 14 9e br #0x9e14 992e: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 9932: 02 24 jz $+6 ;abs 0x9938 9934: 30 40 fa 9d br #0x9dfa 9938: d1 43 2e 00 mov.b #1, 46(r1) ;r3 As==01, 0x002e(r1) 993c: 30 40 14 9e br #0x9e14 9940: 0e 45 mov r5, r14 9942: 2e 53 incd r14 9944: 2a 45 mov @r5, r10 9946: 0a 93 tst r10 9948: 03 38 jl $+8 ;abs 0x9950 994a: 81 4a 26 00 mov r10, 38(r1) ;0x0026(r1) 994e: 0d 3c jmp $+28 ;abs 0x996a 9950: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 9954: 02 24 jz $+6 ;abs 0x995a 9956: 30 40 0a 9e br #0x9e0a 995a: f1 d0 10 00 bis.b #16, 0(r1) ;#0x0010, 0x0000(r1) 995e: 00 00 9960: 3a e3 inv r10 9962: 81 4a 26 00 mov r10, 38(r1) ;0x0026(r1) 9966: 91 53 26 00 inc 38(r1) ;0x0026(r1) 996a: 05 4e mov r14, r5 996c: 27 3c jmp $+80 ;abs 0x99bc 996e: 81 93 26 00 tst 38(r1) ;0x0026(r1) 9972: 15 20 jnz $+44 ;abs 0x999e 9974: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 9978: 12 20 jnz $+38 ;abs 0x999e 997a: 69 41 mov.b @r1, r9 997c: 79 f0 10 00 and.b #16, r9 ;#0x0010 9980: 5e 43 mov.b #1, r14 ;r3 As==01 9982: 01 24 jz $+4 ;abs 0x9986 9984: 4e 43 clr.b r14 9986: 4e 4e mov.b r14, r14 9988: 0e 11 rra r14 998a: 0e 43 clr r14 998c: 4e 10 rrc.b r14 998e: 6a 41 mov.b @r1, r10 9990: 7a f0 7f 00 and.b #127, r10 ;#0x007f 9994: 4a de bis.b r14, r10 9996: c1 4a 00 00 mov.b r10, 0(r1) ;0x0000(r1) 999a: 30 40 14 9e br #0x9e14 999e: 1a 41 26 00 mov 38(r1), r10 ;0x0026(r1) 99a2: 0a 5a rla r10 99a4: 0c 4a mov r10, r12 99a6: 0c 5c rla r12 99a8: 0c 5c rla r12 99aa: 0a 5c add r12, r10 99ac: 81 4a 26 00 mov r10, 38(r1) ;0x0026(r1) 99b0: b1 50 d0 ff add #-48, 38(r1) ;#0xffd0, 0x0026(r1) 99b4: 26 00 99b6: 8e 11 sxt r14 99b8: 81 5e 26 00 add r14, 38(r1) ;0x0026(r1) 99bc: d1 43 2a 00 mov.b #1, 42(r1) ;r3 As==01, 0x002a(r1) 99c0: 30 40 14 9e br #0x9e14 99c4: 07 45 mov r5, r7 99c6: 27 53 incd r7 99c8: 6e 45 mov.b @r5, r14 99ca: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 99ce: 03 20 jnz $+8 ;abs 0x99d6 99d0: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 99d4: 26 27 jz $-434 ;abs 0x9822 99d6: c1 4e 04 00 mov.b r14, 4(r1) ;0x0004(r1) 99da: c1 43 05 00 mov.b #0, 5(r1) ;r3 As==00, 0x0005(r1) 99de: 0e 41 mov r1, r14 99e0: 2e 52 add #4, r14 ;r2 As==10 99e2: 03 3c jmp $+8 ;abs 0x99ea 99e4: 07 45 mov r5, r7 99e6: 27 53 incd r7 99e8: 2e 45 mov @r5, r14 99ea: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 99ee: 07 24 jz $+16 ;abs 0x99fe 99f0: e1 d2 01 00 bis.b #4, 1(r1) ;r2 As==10, 0x0001(r1) 99f4: 1f 41 26 00 mov 38(r1), r15 ;0x0026(r1) 99f8: c1 4f 03 00 mov.b r15, 3(r1) ;0x0003(r1) 99fc: 06 3c jmp $+14 ;abs 0x9a0a 99fe: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 9a02: 03 24 jz $+8 ;abs 0x9a0a 9a04: 91 41 26 00 mov 38(r1), 48(r1) ;0x0026(r1), 0x0030(r1) 9a08: 30 00 9a0a: 0e 93 tst r14 9a0c: 02 20 jnz $+6 ;abs 0x9a12 9a0e: 3e 40 90 a1 mov #-24176,r14 ;#0xa190 9a12: 11 12 04 00 push 4(r1) ;0x0004(r1) 9a16: 11 12 04 00 push 4(r1) ;0x0004(r1) 9a1a: 1d 41 34 00 mov 52(r1), r13 ;0x0034(r1) 9a1e: 1f 41 3e 00 mov 62(r1), r15 ;0x003e(r1) 9a22: b0 12 08 96 call #0x9608 9a26: 21 52 add #4, r1 ;r2 As==10 9a28: 81 5f 2c 00 add r15, 44(r1) ;0x002c(r1) 9a2c: 05 47 mov r7, r5 9a2e: 30 40 f6 9d br #0x9df6 9a32: 07 45 mov r5, r7 9a34: 27 53 incd r7 9a36: 29 45 mov @r5, r9 9a38: 81 49 1e 00 mov r9, 30(r1) ;0x001e(r1) 9a3c: 5e 43 mov.b #1, r14 ;r3 As==01 9a3e: 09 93 tst r9 9a40: 01 20 jnz $+4 ;abs 0x9a44 9a42: 4e 43 clr.b r14 9a44: 4e 5e rla.b r14 9a46: 4e 5e rla.b r14 9a48: 4e 5e rla.b r14 9a4a: 6a 41 mov.b @r1, r10 9a4c: 7a f0 f7 ff and.b #-9, r10 ;#0xfff7 9a50: 4a de bis.b r14, r10 9a52: c1 4a 00 00 mov.b r10, 0(r1) ;0x0000(r1) 9a56: 05 47 mov r7, r5 9a58: b1 40 10 00 mov #16, 40(r1) ;#0x0010, 0x0028(r1) 9a5c: 28 00 9a5e: 53 3c jmp $+168 ;abs 0x9b06 9a60: d1 d3 01 00 bis.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 9a64: 06 3c jmp $+14 ;abs 0x9a72 9a66: e1 d2 00 00 bis.b #4, 0(r1) ;r2 As==10, 0x0000(r1) 9a6a: b1 40 0a 00 mov #10, 40(r1) ;#0x000a, 0x0028(r1) 9a6e: 28 00 9a70: 03 3c jmp $+8 ;abs 0x9a78 9a72: b1 40 10 00 mov #16, 40(r1) ;#0x0010, 0x0028(r1) 9a76: 28 00 9a78: 6b 41 mov.b @r1, r11 9a7a: 6b b3 bit.b #2, r11 ;r3 As==10 9a7c: 24 24 jz $+74 ;abs 0x9ac6 9a7e: 0c 45 mov r5, r12 9a80: 3c 52 add #8, r12 ;r2 As==11 9a82: 28 45 mov @r5, r8 9a84: 17 45 02 00 mov 2(r5), r7 ;0x0002(r5) 9a88: 16 45 04 00 mov 4(r5), r6 ;0x0004(r5) 9a8c: 1b 45 06 00 mov 6(r5), r11 ;0x0006(r5) 9a90: 81 48 1e 00 mov r8, 30(r1) ;0x001e(r1) 9a94: 81 47 20 00 mov r7, 32(r1) ;0x0020(r1) 9a98: 81 46 22 00 mov r6, 34(r1) ;0x0022(r1) 9a9c: 81 4b 24 00 mov r11, 36(r1) ;0x0024(r1) 9aa0: d1 43 2b 00 mov.b #1, 43(r1) ;r3 As==01, 0x002b(r1) 9aa4: 08 93 tst r8 9aa6: 06 20 jnz $+14 ;abs 0x9ab4 9aa8: 07 93 tst r7 9aaa: 04 20 jnz $+10 ;abs 0x9ab4 9aac: 06 93 tst r6 9aae: 02 20 jnz $+6 ;abs 0x9ab4 9ab0: 0b 93 tst r11 9ab2: 02 24 jz $+6 ;abs 0x9ab8 9ab4: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 9ab8: 0b 5b rla r11 9aba: 0b 43 clr r11 9abc: 0b 6b rlc r11 9abe: c1 4b 2f 00 mov.b r11, 47(r1) ;0x002f(r1) 9ac2: 05 4c mov r12, r5 9ac4: 20 3c jmp $+66 ;abs 0x9b06 9ac6: 5b f3 and.b #1, r11 ;r3 As==01 9ac8: 07 45 mov r5, r7 9aca: 0d 24 jz $+28 ;abs 0x9ae6 9acc: 27 52 add #4, r7 ;r2 As==10 9ace: 28 45 mov @r5, r8 9ad0: 1b 45 02 00 mov 2(r5), r11 ;0x0002(r5) 9ad4: 81 48 1e 00 mov r8, 30(r1) ;0x001e(r1) 9ad8: 81 4b 20 00 mov r11, 32(r1) ;0x0020(r1) 9adc: d1 43 2b 00 mov.b #1, 43(r1) ;r3 As==01, 0x002b(r1) 9ae0: 08 93 tst r8 9ae2: 09 20 jnz $+20 ;abs 0x9af6 9ae4: 06 3c jmp $+14 ;abs 0x9af2 9ae6: 27 53 incd r7 9ae8: 2b 45 mov @r5, r11 9aea: 81 4b 1e 00 mov r11, 30(r1) ;0x001e(r1) 9aee: d1 43 2b 00 mov.b #1, 43(r1) ;r3 As==01, 0x002b(r1) 9af2: 0b 93 tst r11 9af4: 02 24 jz $+6 ;abs 0x9afa 9af6: c1 43 2b 00 mov.b #0, 43(r1) ;r3 As==00, 0x002b(r1) 9afa: 0b 5b rla r11 9afc: 0b 43 clr r11 9afe: 0b 6b rlc r11 9b00: c1 4b 2f 00 mov.b r11, 47(r1) ;0x002f(r1) 9b04: 05 47 mov r7, r5 9b06: f1 b2 00 00 bit.b #8, 0(r1) ;r2 As==11, 0x0000(r1) 9b0a: 12 24 jz $+38 ;abs 0x9b30 9b0c: c1 93 2b 00 tst.b 43(r1) ;0x002b(r1) 9b10: 0f 20 jnz $+32 ;abs 0x9b30 9b12: 68 41 mov.b @r1, r8 9b14: b1 90 10 00 cmp #16, 40(r1) ;#0x0010, 0x0028(r1) 9b18: 28 00 9b1a: 03 20 jnz $+8 ;abs 0x9b22 9b1c: 78 d0 40 00 bis.b #64, r8 ;#0x0040 9b20: 05 3c jmp $+12 ;abs 0x9b2c 9b22: b1 92 28 00 cmp #8, 40(r1) ;r2 As==11, 0x0028(r1) 9b26: 04 20 jnz $+10 ;abs 0x9b30 9b28: 78 d0 20 00 bis.b #32, r8 ;#0x0020 9b2c: c1 48 00 00 mov.b r8, 0(r1) ;0x0000(r1) 9b30: 68 41 mov.b @r1, r8 9b32: 68 b2 bit.b #4, r8 ;r2 As==10 9b34: 30 24 jz $+98 ;abs 0x9b96 9b36: c1 93 2f 00 tst.b 47(r1) ;0x002f(r1) 9b3a: 2d 24 jz $+92 ;abs 0x9b96 9b3c: f1 40 2d 00 mov.b #45, 2(r1) ;#0x002d, 0x0002(r1) 9b40: 02 00 9b42: 68 b3 bit.b #2, r8 ;r3 As==10 9b44: 11 24 jz $+36 ;abs 0x9b68 9b46: b1 e3 1e 00 xor #-1, 30(r1) ;r3 As==11, 0x001e(r1) 9b4a: b1 e3 20 00 xor #-1, 32(r1) ;r3 As==11, 0x0020(r1) 9b4e: b1 e3 22 00 xor #-1, 34(r1) ;r3 As==11, 0x0022(r1) 9b52: b1 e3 24 00 xor #-1, 36(r1) ;r3 As==11, 0x0024(r1) 9b56: 91 53 1e 00 inc 30(r1) ;0x001e(r1) 9b5a: 81 63 20 00 adc 32(r1) ;0x0020(r1) 9b5e: 81 63 22 00 adc 34(r1) ;0x0022(r1) 9b62: 81 63 24 00 adc 36(r1) ;0x0024(r1) 9b66: 17 3c jmp $+48 ;abs 0x9b96 9b68: 58 b3 bit.b #1, r8 ;r3 As==01 9b6a: 0f 24 jz $+32 ;abs 0x9b8a 9b6c: 1a 41 1e 00 mov 30(r1), r10 ;0x001e(r1) 9b70: 1b 41 20 00 mov 32(r1), r11 ;0x0020(r1) 9b74: 3a e3 inv r10 9b76: 3b e3 inv r11 9b78: 0e 4a mov r10, r14 9b7a: 0f 4b mov r11, r15 9b7c: 1e 53 inc r14 9b7e: 0f 63 adc r15 9b80: 81 4e 1e 00 mov r14, 30(r1) ;0x001e(r1) 9b84: 81 4f 20 00 mov r15, 32(r1) ;0x0020(r1) 9b88: 06 3c jmp $+14 ;abs 0x9b96 9b8a: 1a 41 1e 00 mov 30(r1), r10 ;0x001e(r1) 9b8e: 3a e3 inv r10 9b90: 1a 53 inc r10 9b92: 81 4a 1e 00 mov r10, 30(r1) ;0x001e(r1) 9b96: c1 43 1b 00 mov.b #0, 27(r1) ;r3 As==00, 0x001b(r1) 9b9a: 68 b3 bit.b #2, r8 ;r3 As==10 9b9c: 6a 24 jz $+214 ;abs 0x9c72 9b9e: 16 41 1e 00 mov 30(r1), r6 ;0x001e(r1) 9ba2: 91 41 20 00 mov 32(r1), 60(r1) ;0x0020(r1), 0x003c(r1) 9ba6: 3c 00 9ba8: 18 41 22 00 mov 34(r1), r8 ;0x0022(r1) 9bac: 14 41 24 00 mov 36(r1), r4 ;0x0024(r1) 9bb0: 07 41 mov r1, r7 9bb2: 37 50 1a 00 add #26, r7 ;#0x001a 9bb6: 09 46 mov r6, r9 9bb8: 91 41 28 00 mov 40(r1), 50(r1) ;0x0028(r1), 0x0032(r1) 9bbc: 32 00 9bbe: 1b 41 28 00 mov 40(r1), r11 ;0x0028(r1) 9bc2: 8b 10 swpb r11 9bc4: 8b 11 sxt r11 9bc6: 8b 10 swpb r11 9bc8: 8b 11 sxt r11 9bca: 81 4b 34 00 mov r11, 52(r1) ;0x0034(r1) 9bce: 81 4b 36 00 mov r11, 54(r1) ;0x0036(r1) 9bd2: 81 4b 38 00 mov r11, 56(r1) ;0x0038(r1) 9bd6: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9bda: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9bde: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9be2: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9be6: 0c 49 mov r9, r12 9be8: 1d 41 44 00 mov 68(r1), r13 ;0x0044(r1) 9bec: 0e 48 mov r8, r14 9bee: 0f 44 mov r4, r15 9bf0: b0 12 ea 9e call #0x9eea 9bf4: 31 52 add #8, r1 ;r2 As==11 9bf6: 0b 4c mov r12, r11 9bf8: 3c 90 0a 00 cmp #10, r12 ;#0x000a 9bfc: 05 34 jge $+12 ;abs 0x9c08 9bfe: 7b 50 30 00 add.b #48, r11 ;#0x0030 9c02: c7 4b 00 00 mov.b r11, 0(r7) ;0x0000(r7) 9c06: 0c 3c jmp $+26 ;abs 0x9c20 9c08: 4b 4c mov.b r12, r11 9c0a: d1 b3 01 00 bit.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 9c0e: 03 24 jz $+8 ;abs 0x9c16 9c10: 7a 40 37 00 mov.b #55, r10 ;#0x0037 9c14: 02 3c jmp $+6 ;abs 0x9c1a 9c16: 7a 40 57 00 mov.b #87, r10 ;#0x0057 9c1a: 4a 5b add.b r11, r10 9c1c: c7 4a 00 00 mov.b r10, 0(r7) ;0x0000(r7) 9c20: 06 47 mov r7, r6 9c22: 36 53 add #-1, r6 ;r3 As==11 9c24: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9c28: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9c2c: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9c30: 11 12 3a 00 push 58(r1) ;0x003a(r1) 9c34: 0c 49 mov r9, r12 9c36: 1d 41 44 00 mov 68(r1), r13 ;0x0044(r1) 9c3a: 0e 48 mov r8, r14 9c3c: 0f 44 mov r4, r15 9c3e: b0 12 c4 9e call #0x9ec4 9c42: 31 52 add #8, r1 ;r2 As==11 9c44: 09 4c mov r12, r9 9c46: 81 4d 3c 00 mov r13, 60(r1) ;0x003c(r1) 9c4a: 08 4e mov r14, r8 9c4c: 04 4f mov r15, r4 9c4e: 37 53 add #-1, r7 ;r3 As==11 9c50: 0c 93 tst r12 9c52: b2 23 jnz $-154 ;abs 0x9bb8 9c54: 0d 93 tst r13 9c56: b0 23 jnz $-158 ;abs 0x9bb8 9c58: 0e 93 tst r14 9c5a: ae 23 jnz $-162 ;abs 0x9bb8 9c5c: 0f 93 tst r15 9c5e: ac 23 jnz $-166 ;abs 0x9bb8 9c60: 81 43 1e 00 mov #0, 30(r1) ;r3 As==00, 0x001e(r1) 9c64: 81 43 20 00 mov #0, 32(r1) ;r3 As==00, 0x0020(r1) 9c68: 81 43 22 00 mov #0, 34(r1) ;r3 As==00, 0x0022(r1) 9c6c: 81 43 24 00 mov #0, 36(r1) ;r3 As==00, 0x0024(r1) 9c70: 6c 3c jmp $+218 ;abs 0x9d4a 9c72: 58 b3 bit.b #1, r8 ;r3 As==01 9c74: 3e 24 jz $+126 ;abs 0x9cf2 9c76: 14 41 1e 00 mov 30(r1), r4 ;0x001e(r1) 9c7a: 17 41 20 00 mov 32(r1), r7 ;0x0020(r1) 9c7e: 08 41 mov r1, r8 9c80: 38 50 1a 00 add #26, r8 ;#0x001a 9c84: 19 41 28 00 mov 40(r1), r9 ;0x0028(r1) 9c88: 89 10 swpb r9 9c8a: 89 11 sxt r9 9c8c: 89 10 swpb r9 9c8e: 89 11 sxt r9 9c90: 1c 41 28 00 mov 40(r1), r12 ;0x0028(r1) 9c94: 0d 49 mov r9, r13 9c96: 0e 44 mov r4, r14 9c98: 0f 47 mov r7, r15 9c9a: b0 12 d2 8c call #0x8cd2 9c9e: 0b 4e mov r14, r11 9ca0: 3e 90 0a 00 cmp #10, r14 ;#0x000a 9ca4: 05 34 jge $+12 ;abs 0x9cb0 9ca6: 7b 50 30 00 add.b #48, r11 ;#0x0030 9caa: c8 4b 00 00 mov.b r11, 0(r8) ;0x0000(r8) 9cae: 0c 3c jmp $+26 ;abs 0x9cc8 9cb0: 4b 4e mov.b r14, r11 9cb2: d1 b3 01 00 bit.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 9cb6: 03 24 jz $+8 ;abs 0x9cbe 9cb8: 7a 40 37 00 mov.b #55, r10 ;#0x0037 9cbc: 02 3c jmp $+6 ;abs 0x9cc2 9cbe: 7a 40 57 00 mov.b #87, r10 ;#0x0057 9cc2: 4a 5b add.b r11, r10 9cc4: c8 4a 00 00 mov.b r10, 0(r8) ;0x0000(r8) 9cc8: 06 48 mov r8, r6 9cca: 36 53 add #-1, r6 ;r3 As==11 9ccc: 1c 41 28 00 mov 40(r1), r12 ;0x0028(r1) 9cd0: 0d 49 mov r9, r13 9cd2: 0e 44 mov r4, r14 9cd4: 0f 47 mov r7, r15 9cd6: b0 12 9c 8c call #0x8c9c 9cda: 04 4e mov r14, r4 9cdc: 07 4f mov r15, r7 9cde: 38 53 add #-1, r8 ;r3 As==11 9ce0: 0e 93 tst r14 9ce2: d0 23 jnz $-94 ;abs 0x9c84 9ce4: 0f 93 tst r15 9ce6: ce 23 jnz $-98 ;abs 0x9c84 9ce8: 81 43 1e 00 mov #0, 30(r1) ;r3 As==00, 0x001e(r1) 9cec: 81 43 20 00 mov #0, 32(r1) ;r3 As==00, 0x0020(r1) 9cf0: 2c 3c jmp $+90 ;abs 0x9d4a 9cf2: 17 41 1e 00 mov 30(r1), r7 ;0x001e(r1) 9cf6: 08 41 mov r1, r8 9cf8: 38 50 1a 00 add #26, r8 ;#0x001a 9cfc: 1e 41 28 00 mov 40(r1), r14 ;0x0028(r1) 9d00: 0f 47 mov r7, r15 9d02: b0 12 94 8c call #0x8c94 9d06: 0d 4f mov r15, r13 9d08: 3f 90 0a 00 cmp #10, r15 ;#0x000a 9d0c: 05 34 jge $+12 ;abs 0x9d18 9d0e: 7d 50 30 00 add.b #48, r13 ;#0x0030 9d12: c8 4d 00 00 mov.b r13, 0(r8) ;0x0000(r8) 9d16: 0c 3c jmp $+26 ;abs 0x9d30 9d18: 4d 4f mov.b r15, r13 9d1a: d1 b3 01 00 bit.b #1, 1(r1) ;r3 As==01, 0x0001(r1) 9d1e: 03 24 jz $+8 ;abs 0x9d26 9d20: 7c 40 37 00 mov.b #55, r12 ;#0x0037 9d24: 02 3c jmp $+6 ;abs 0x9d2a 9d26: 7c 40 57 00 mov.b #87, r12 ;#0x0057 9d2a: 4c 5d add.b r13, r12 9d2c: c8 4c 00 00 mov.b r12, 0(r8) ;0x0000(r8) 9d30: 06 48 mov r8, r6 9d32: 36 53 add #-1, r6 ;r3 As==11 9d34: 1e 41 28 00 mov 40(r1), r14 ;0x0028(r1) 9d38: 0f 47 mov r7, r15 9d3a: b0 12 7a 8c call #0x8c7a 9d3e: 07 4f mov r15, r7 9d40: 38 53 add #-1, r8 ;r3 As==11 9d42: 0f 93 tst r15 9d44: db 23 jnz $-72 ;abs 0x9cfc 9d46: 81 43 1e 00 mov #0, 30(r1) ;r3 As==00, 0x001e(r1) 9d4a: b1 90 0a 00 cmp #10, 40(r1) ;#0x000a, 0x0028(r1) 9d4e: 28 00 9d50: 02 24 jz $+6 ;abs 0x9d56 9d52: c1 43 02 00 mov.b #0, 2(r1) ;r3 As==00, 0x0002(r1) 9d56: c1 93 2e 00 tst.b 46(r1) ;0x002e(r1) 9d5a: 2a 24 jz $+86 ;abs 0x9db0 9d5c: 0f 41 mov r1, r15 9d5e: 3f 50 1c 00 add #28, r15 ;#0x001c 9d62: 81 4f 42 00 mov r15, 66(r1) ;0x0042(r1) 9d66: 1a 41 1c 00 mov 28(r1), r10 ;0x001c(r1) 9d6a: 8a 10 swpb r10 9d6c: 8a 11 sxt r10 9d6e: 8a 10 swpb r10 9d70: 8a 11 sxt r10 9d72: 81 4a 44 00 mov r10, 68(r1) ;0x0044(r1) 9d76: 81 46 46 00 mov r6, 70(r1) ;0x0046(r1) 9d7a: 0a 46 mov r6, r10 9d7c: 8a 10 swpb r10 9d7e: 8a 11 sxt r10 9d80: 8a 10 swpb r10 9d82: 8a 11 sxt r10 9d84: 81 4a 48 00 mov r10, 72(r1) ;0x0048(r1) 9d88: 1c 41 42 00 mov 66(r1), r12 ;0x0042(r1) 9d8c: 1d 41 44 00 mov 68(r1), r13 ;0x0044(r1) 9d90: 1c 81 46 00 sub 70(r1), r12 ;0x0046(r1) 9d94: 1d 71 48 00 subc 72(r1), r13 ;0x0048(r1) 9d98: 2c 83 decd r12 9d9a: 1c 91 26 00 cmp 38(r1), r12 ;0x0026(r1) 9d9e: 0e 2c jc $+30 ;abs 0x9dbc 9da0: e1 d3 01 00 bis.b #2, 1(r1) ;r3 As==10, 0x0001(r1) 9da4: 5e 41 26 00 mov.b 38(r1), r14 ;0x0026(r1) 9da8: 4e 8c sub.b r12, r14 9daa: c1 4e 03 00 mov.b r14, 3(r1) ;0x0003(r1) 9dae: 06 3c jmp $+14 ;abs 0x9dbc 9db0: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) 9db4: 03 24 jz $+8 ;abs 0x9dbc 9db6: 91 41 26 00 mov 38(r1), 48(r1) ;0x0026(r1), 0x0030(r1) 9dba: 30 00 9dbc: 11 12 04 00 push 4(r1) ;0x0004(r1) 9dc0: 11 12 04 00 push 4(r1) ;0x0004(r1) 9dc4: 1d 41 34 00 mov 52(r1), r13 ;0x0034(r1) 9dc8: 0e 46 mov r6, r14 9dca: 1e 53 inc r14 9dcc: 1f 41 3e 00 mov 62(r1), r15 ;0x003e(r1) 9dd0: b0 12 08 96 call #0x9608 9dd4: 21 52 add #4, r1 ;r2 As==10 9dd6: 81 5f 2c 00 add r15, 44(r1) ;0x002c(r1) 9dda: 0d 3c jmp $+28 ;abs 0x9df6 9ddc: 7f 49 mov.b @r9+, r15 9dde: 8f 11 sxt r15 9de0: 91 12 3c 00 call 60(r1) ;0x003c(r1) 9de4: 0e 49 mov r9, r14 9de6: 0e 58 add r8, r14 9de8: 19 91 40 00 cmp 64(r1), r9 ;0x0040(r1) 9dec: f7 2b jnc $-16 ;abs 0x9ddc 9dee: 81 49 3e 00 mov r9, 62(r1) ;0x003e(r1) 9df2: 81 4e 2c 00 mov r14, 44(r1) ;0x002c(r1) 9df6: 07 43 clr r7 9df8: 0e 3c jmp $+30 ;abs 0x9e16 9dfa: 91 41 26 00 mov 38(r1), 48(r1) ;0x0026(r1), 0x0030(r1) 9dfe: 30 00 9e00: d1 43 2e 00 mov.b #1, 46(r1) ;r3 As==01, 0x002e(r1) 9e04: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) 9e08: 03 3c jmp $+8 ;abs 0x9e10 9e0a: 05 4e mov r14, r5 9e0c: d1 43 2a 00 mov.b #1, 42(r1) ;r3 As==01, 0x002a(r1) 9e10: 81 43 26 00 mov #0, 38(r1) ;r3 As==00, 0x0026(r1) 9e14: 17 43 mov #1, r7 ;r3 As==01 9e16: 16 41 40 00 mov 64(r1), r6 ;0x0040(r1) 9e1a: 6e 46 mov.b @r6, r14 9e1c: 4e 93 tst.b r14 9e1e: 02 24 jz $+6 ;abs 0x9e24 9e20: 30 40 ec 97 br #0x97ec 9e24: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) 9e28: 31 50 4a 00 add #74, r1 ;#0x004a 9e2c: 34 41 pop r4 9e2e: 35 41 pop r5 9e30: 36 41 pop r6 9e32: 37 41 pop r7 9e34: 38 41 pop r8 9e36: 39 41 pop r9 9e38: 3a 41 pop r10 9e3a: 3b 41 pop r11 9e3c: 30 41 ret 00009e3e : 9e3e: 0b 12 push r11 9e40: 0d 93 tst r13 9e42: 0e 24 jz $+30 ;abs 0x9e60 9e44: 6c 4f mov.b @r15, r12 9e46: 7b 4e mov.b @r14+, r11 9e48: 4c 9b cmp.b r11, r12 9e4a: 05 24 jz $+12 ;abs 0x9e56 9e4c: 4f 4c mov.b r12, r15 9e4e: 5e 4e ff ff mov.b -1(r14),r14 ;0xffff(r14) 9e52: 0f 8e sub r14, r15 9e54: 06 3c jmp $+14 ;abs 0x9e62 9e56: 1f 53 inc r15 9e58: 4c 93 tst.b r12 9e5a: 02 24 jz $+6 ;abs 0x9e60 9e5c: 3d 53 add #-1, r13 ;r3 As==11 9e5e: f0 3f jmp $-30 ;abs 0x9e40 9e60: 0f 43 clr r15 9e62: 3b 41 pop r11 9e64: 30 41 ret 00009e66 <__xabi_udivmod64>: 9e66: 07 12 push r7 9e68: 06 12 push r6 9e6a: 05 12 push r5 9e6c: 04 12 push r4 9e6e: 30 12 40 00 push #64 ;#0x0040 9e72: 04 48 mov r8, r4 9e74: 05 49 mov r9, r5 9e76: 06 4a mov r10, r6 9e78: 07 4b mov r11, r7 9e7a: 08 43 clr r8 9e7c: 09 43 clr r9 9e7e: 0a 43 clr r10 9e80: 0b 43 clr r11 9e82: 0c 5c rla r12 9e84: 0d 6d rlc r13 9e86: 0e 6e rlc r14 9e88: 0f 6f rlc r15 9e8a: 08 68 rlc r8 9e8c: 09 69 rlc r9 9e8e: 0a 6a rlc r10 9e90: 0b 6b rlc r11 9e92: 0b 97 cmp r7, r11 9e94: 0e 28 jnc $+30 ;abs 0x9eb2 9e96: 08 20 jnz $+18 ;abs 0x9ea8 9e98: 0a 96 cmp r6, r10 9e9a: 0b 28 jnc $+24 ;abs 0x9eb2 9e9c: 05 20 jnz $+12 ;abs 0x9ea8 9e9e: 09 95 cmp r5, r9 9ea0: 08 28 jnc $+18 ;abs 0x9eb2 9ea2: 02 20 jnz $+6 ;abs 0x9ea8 9ea4: 08 94 cmp r4, r8 9ea6: 05 28 jnc $+12 ;abs 0x9eb2 9ea8: 08 84 sub r4, r8 9eaa: 09 75 subc r5, r9 9eac: 0a 76 subc r6, r10 9eae: 0b 77 subc r7, r11 9eb0: 1c d3 bis #1, r12 ;r3 As==01 9eb2: 91 83 00 00 dec 0(r1) ;0x0000(r1) 9eb6: e5 23 jnz $-52 ;abs 0x9e82 9eb8: 21 53 incd r1 9eba: 34 41 pop r4 9ebc: 35 41 pop r5 9ebe: 36 41 pop r6 9ec0: 37 41 pop r7 9ec2: 30 41 ret 00009ec4 <__udivdi3>: 9ec4: 0b 12 push r11 9ec6: 0a 12 push r10 9ec8: 09 12 push r9 9eca: 08 12 push r8 9ecc: 18 41 0a 00 mov 10(r1), r8 ;0x000a(r1) 9ed0: 19 41 0c 00 mov 12(r1), r9 ;0x000c(r1) 9ed4: 1a 41 0e 00 mov 14(r1), r10 ;0x000e(r1) 9ed8: 1b 41 10 00 mov 16(r1), r11 ;0x0010(r1) 9edc: b0 12 66 9e call #0x9e66 9ee0: 38 41 pop r8 9ee2: 39 41 pop r9 9ee4: 3a 41 pop r10 9ee6: 3b 41 pop r11 9ee8: 30 41 ret 00009eea <__umoddi3>: 9eea: 0b 12 push r11 9eec: 0a 12 push r10 9eee: 09 12 push r9 9ef0: 08 12 push r8 9ef2: 18 41 0a 00 mov 10(r1), r8 ;0x000a(r1) 9ef6: 19 41 0c 00 mov 12(r1), r9 ;0x000c(r1) 9efa: 1a 41 0e 00 mov 14(r1), r10 ;0x000e(r1) 9efe: 1b 41 10 00 mov 16(r1), r11 ;0x0010(r1) 9f02: b0 12 66 9e call #0x9e66 9f06: 0c 48 mov r8, r12 9f08: 0d 49 mov r9, r13 9f0a: 0e 4a mov r10, r14 9f0c: 0f 4b mov r11, r15 9f0e: 38 41 pop r8 9f10: 39 41 pop r9 9f12: 3a 41 pop r10 9f14: 3b 41 pop r11 9f16: 30 41 ret 00009f18 <__udivmoddi4>: 9f18: 0b 12 push r11 9f1a: 0a 12 push r10 9f1c: 09 12 push r9 9f1e: 08 12 push r8 9f20: 07 12 push r7 9f22: 18 41 0c 00 mov 12(r1), r8 ;0x000c(r1) 9f26: 19 41 0e 00 mov 14(r1), r9 ;0x000e(r1) 9f2a: 1a 41 10 00 mov 16(r1), r10 ;0x0010(r1) 9f2e: 1b 41 12 00 mov 18(r1), r11 ;0x0012(r1) 9f32: b0 12 66 9e call #0x9e66 9f36: 17 41 14 00 mov 20(r1), r7 ;0x0014(r1) 9f3a: 87 48 00 00 mov r8, 0(r7) ;0x0000(r7) 9f3e: 87 49 02 00 mov r9, 2(r7) ;0x0002(r7) 9f42: 87 4a 04 00 mov r10, 4(r7) ;0x0004(r7) 9f46: 87 4b 06 00 mov r11, 6(r7) ;0x0006(r7) 9f4a: 37 41 pop r7 9f4c: 38 41 pop r8 9f4e: 39 41 pop r9 9f50: 3a 41 pop r10 9f52: 3b 41 pop r11 9f54: 30 41 ret 00009f56 <_unexpected_>: 9f56: 00 13 reti Disassembly of section .vectors: 0000ffe0 <__ivtbl_16>: ffe0: e2 85 e2 85 e2 85 e6 85 e2 85 08 86 e2 85 e2 85 ................ fff0: 10 86 e2 85 e2 85 e2 85 e2 85 e2 85 e2 85 00 80 ................