alsp_cntrl.elf: file format elf32-msp430 SYMBOL TABLE: 0000e000 l d .text 00000000 .text 00000200 l d .data 00000000 .data 00000202 l d .bss 00000000 .bss 0000ffe0 l d .vectors 00000000 .vectors 00000000 l d .stab 00000000 .stab 00000000 l d .stabstr 00000000 .stabstr 00000070 l *ABS* 00000000 U0CTL 00000071 l *ABS* 00000000 U0TCTL 00000072 l *ABS* 00000000 U0RCTL 00000073 l *ABS* 00000000 U0MCTL 00000074 l *ABS* 00000000 U0BR0 00000075 l *ABS* 00000000 U0BR1 00000076 l *ABS* 00000000 U0RXBUF 00000077 l *ABS* 00000000 U0TXBUF 00000070 l *ABS* 00000000 UCTL 00000071 l *ABS* 00000000 UTCTL 00000072 l *ABS* 00000000 URCTL 00000073 l *ABS* 00000000 UMCTL 00000074 l *ABS* 00000000 UBR0 00000075 l *ABS* 00000000 UBR1 00000076 l *ABS* 00000000 RXBUF 00000077 l *ABS* 00000000 TXBUF 00000070 l *ABS* 00000000 UCTL0 00000071 l *ABS* 00000000 UTCTL0 00000072 l *ABS* 00000000 URCTL0 00000073 l *ABS* 00000000 UMCTL0 00000074 l *ABS* 00000000 UBR00 00000075 l *ABS* 00000000 UBR10 00000076 l *ABS* 00000000 RXBUF0 00000077 l *ABS* 00000000 TXBUF0 00000070 l *ABS* 00000000 UCTL_0 00000071 l *ABS* 00000000 UTCTL_0 00000072 l *ABS* 00000000 URCTL_0 00000073 l *ABS* 00000000 UMCTL_0 00000074 l *ABS* 00000000 UBR0_0 00000075 l *ABS* 00000000 UBR1_0 00000076 l *ABS* 00000000 RXBUF_0 00000077 l *ABS* 00000000 TXBUF_0 00000020 l *ABS* 00000000 P1IN 00000021 l *ABS* 00000000 P1OUT 00000022 l *ABS* 00000000 P1DIR 00000023 l *ABS* 00000000 P1IFG 00000024 l *ABS* 00000000 P1IES 00000025 l *ABS* 00000000 P1IE 00000026 l *ABS* 00000000 P1SEL 00000028 l *ABS* 00000000 P2IN 00000029 l *ABS* 00000000 P2OUT 0000002a l *ABS* 00000000 P2DIR 0000002b l *ABS* 00000000 P2IFG 0000002c l *ABS* 00000000 P2IES 0000002d l *ABS* 00000000 P2IE 0000002e l *ABS* 00000000 P2SEL 00000018 l *ABS* 00000000 P3IN 00000019 l *ABS* 00000000 P3OUT 0000001a l *ABS* 00000000 P3DIR 0000001b l *ABS* 00000000 P3SEL 0000012e l *ABS* 00000000 TA0IV 00000160 l *ABS* 00000000 TA0CTL 00000170 l *ABS* 00000000 TA0R 00000162 l *ABS* 00000000 TA0CCTL0 00000164 l *ABS* 00000000 TA0CCTL1 00000172 l *ABS* 00000000 TA0CCR0 00000174 l *ABS* 00000000 TA0CCR1 00000166 l *ABS* 00000000 TA0CCTL2 00000176 l *ABS* 00000000 TA0CCR2 00000056 l *ABS* 00000000 DCOCTL 00000057 l *ABS* 00000000 BCSCTL1 00000058 l *ABS* 00000000 BCSCTL2 00000128 l *ABS* 00000000 FCTL1 0000012a l *ABS* 00000000 FCTL2 0000012c l *ABS* 00000000 FCTL3 00000048 l *ABS* 00000000 ADC10DTC0 00000049 l *ABS* 00000000 ADC10DTC1 0000004a l *ABS* 00000000 ADC10AE0 000001b0 l *ABS* 00000000 ADC10CTL0 000001b2 l *ABS* 00000000 ADC10CTL1 000001b4 l *ABS* 00000000 ADC10MEM 000001bc l *ABS* 00000000 ADC10SA 00000120 l *ABS* 00000000 WDTCTL 00000000 l *ABS* 00000000 IE1 00000002 l *ABS* 00000000 IFG1 00000001 l *ABS* 00000000 IE2 00000003 l *ABS* 00000000 IFG2 00000005 l *ABS* 00000000 ME2 00000000 l df *ABS* 00000000 main.c 00000200 l O .data 00000001 make_gdb_happy 0000e5ac l .text 00000000 Letext 00000000 l df *ABS* 00000000 spi_hardware.c 0000e6f2 l .text 00000000 Letext 00000000 l df *ABS* 00000000 interchip.c 0000e890 l .text 00000000 Letext 00000000 l df *ABS* 00000000 memcmp.c 0000e8c0 l .text 00000000 Letext 00000000 l df *ABS* 00000000 strstr.c 0000e90e l .text 00000000 Letext 00000000 l df *ABS* 00000000 strncmp.c 0000e93e l .text 00000000 Letext 00000002 g *ABS* 00000000 __data_size 0000e5e2 g F .text 0000005c CCXX_SPI_RDREG 0000e7b8 g F .text 000000d8 send_string 0000e11a g F .text 0000002a init_UART_SPI 0000e940 g .text 00000000 _etext 00000013 g *ABS* 00000000 __bss_size 0000e93e w .text 00000000 __stop_progExec__ 0000e030 g .text 00000000 _unexpected_1_ 0000e030 w .text 00000000 vector_ffe0 0000e0a2 g F .text 00000078 sys_init 0000e036 g F .text 00000020 P2_VEC 0000e5ac g F .text 00000036 CCXX_SPI_STROBE 0000e030 w .text 00000000 vector_ffec 0000e030 w .text 00000000 vector_fff0 0000e940 g *ABS* 00000000 __data_load_start 0000e030 g .text 00000000 __dtors_end 0000e030 w .text 00000000 vector_fffc 0000e63e g F .text 00000048 CCXX_SPI_WRREG 0000e2bc g F .text 0000019e CCXX_WRITE_SPI_RF_SETTINGS 0000e056 g .text 00000000 vector_ffe4 0000e686 g F .text 0000006c CCXX_SPI_BURST_WRREG 00000202 g O .bss 00000001 RSSI_DBM 0000ffe0 g O .vectors 00000020 InterruptVectors 00000204 g O .bss 0000000a RSSIBUF 0000e6f2 g F .text 000000c6 get_string 0000020e g O .bss 00000001 RSSI 0000e01c w .text 00000000 __do_clear_bss 0000e8c0 g F .text 0000004e strstr 0000e90e g F .text 00000030 strncmp 0000e030 w .text 00000000 vector_ffe2 0000e030 w .text 00000000 vector_ffe8 0000e034 w .text 00000000 _unexpected_ 0000e030 w .text 00000000 vector_fffa 0000e890 g F .text 00000030 memcmp 0000e056 g F .text 0000001e P1_VEC 0000e000 w .text 00000000 _reset_vector__ 0000e030 g .text 00000000 __ctors_start 0000e00a w .text 00000000 __do_copy_data 00000202 g .bss 00000000 __bss_start 0000e030 w .text 00000000 vector_ffee 0000e030 w .text 00000000 vector_fff4 0000e156 g F .text 00000166 main 0000e030 w .text 00000000 vector_fff8 0000e030 w .text 00000000 vector_fff2 00010000 g .vectors 00000000 _vectors_end 0000e036 g .text 00000000 vector_ffe6 0000e074 g F .text 0000002e delay 0000e560 g F .text 0000004c TX_STRING 0000020f g O .bss 00000001 LQI 0000e484 g F .text 000000dc RX_STRING 0000e000 w .text 00000000 __init_stack 00000210 g O .bss 00000001 PKTSTATUS 0000e030 g .text 00000000 __dtors_start 0000e030 g .text 00000000 __ctors_end 00000300 g *ABS* 00000000 __stack 00000202 g .data 00000000 _edata 00000215 g .bss 00000000 _end 00000212 g O .bss 00000002 flags 0000e030 w .text 00000000 vector_fff6 0000e45a g F .text 0000002a RX_MODE 0000e004 w .text 00000000 __low_level_init 0000e02c w .text 00000000 __jump_to_main 00000200 g .data 00000000 __data_start 0000e030 w .text 00000000 vector_ffea 00000214 g O .bss 00000001 status Disassembly of section .text: 0000e000 <__init_stack>: e000: 31 40 00 03 mov #768, r1 ;#0x0300 0000e004 <__low_level_init>: e004: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e008: 20 01 0000e00a <__do_copy_data>: e00a: 3f 40 02 00 mov #2, r15 ;#0x0002 e00e: 0f 93 tst r15 e010: 05 24 jz $+12 ;abs 0xe01c e012: 2f 83 decd r15 e014: 9f 4f 40 e9 mov -5824(r15),512(r15);0xe940(r15), 0x0200(r15) e018: 00 02 e01a: fb 23 jnz $-8 ;abs 0xe012 0000e01c <__do_clear_bss>: e01c: 3f 40 13 00 mov #19, r15 ;#0x0013 e020: 0f 93 tst r15 e022: 04 24 jz $+10 ;abs 0xe02c e024: 1f 83 dec r15 e026: cf 43 02 02 mov.b #0, 514(r15);r3 As==00, 0x0202(r15) e02a: fc 23 jnz $-6 ;abs 0xe024 0000e02c <__jump_to_main>: e02c: 30 40 56 e1 br #0xe156 0000e030 <__ctors_end>: e030: 30 40 34 e0 br #0xe034 0000e034 <_unexpected_>: e034: 00 13 reti 0000e036 : These interrupts are caused by external pin events on handshake lines */ // Port 2 interripts : the allspice radio is talking to us interrupt (PORT2_VECTOR) P2_VEC(void) { e036: 0f 12 push r15 dint(); e038: 32 c2 dint if((P2IFG & GDO0) == GDO0) e03a: f2 b0 10 00 bit.b #16, &0x002b ;#0x0010 e03e: 2b 00 e040: 05 24 jz $+12 ;abs 0xe04c { flags |= ALLSPICE_RDY; e042: 92 d3 12 02 bis #1, &0x0212 ;r3 As==01 LPM3_EXIT; e046: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) e04a: 02 00 //We need to grab that byte! } P2IFG=0x00; e04c: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 eint(); e050: 32 d2 eint } e052: 3f 41 pop r15 e054: 00 13 reti 0000e056 : // Port 1 interripts : The arbiter is talking to us interrupt (PORT1_VECTOR) P1_VEC(void) { e056: 0f 12 push r15 dint(); e058: 32 c2 dint if((P1IFG & ARB_RX) == ARB_RX) //The arbiter is sending us a string e05a: e2 b3 23 00 bit.b #2, &0x0023 ;r3 As==10 e05e: 05 24 jz $+12 ;abs 0xe06a { flags |= ARBITER_RDY; e060: a2 d3 12 02 bis #2, &0x0212 ;r3 As==10 LPM3_EXIT; e064: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) e068: 02 00 //We need to grab that byte! } P1IFG=0x00; e06a: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 eint(); e06e: 32 d2 eint } e070: 3f 41 pop r15 e072: 00 13 reti 0000e074 : Delay function. */ void delay(unsigned int d) { int i; for (i = 0; i: Set up the system */ void sys_init() { WDTCTL = WDTCTL_INIT; //Init watchdog timer e0a2: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e0a6: 20 01 P1OUT = P1OUT_INIT; //Init output data of port1 e0a8: f2 40 05 00 mov.b #5, &0x0021 ;#0x0005 e0ac: 21 00 P2OUT = P2OUT_INIT; //Init output data of port2 e0ae: c2 43 29 00 mov.b #0, &0x0029 ;r3 As==00 P3OUT = P3OUT_INIT; e0b2: d2 43 19 00 mov.b #1, &0x0019 ;r3 As==01 P1SEL = P1SEL_INIT; //Select port or module -function on port1 e0b6: c2 43 26 00 mov.b #0, &0x0026 ;r3 As==00 P2SEL = P2SEL_INIT; //Select port or module -function on port2 e0ba: c2 43 2e 00 mov.b #0, &0x002e ;r3 As==00 P3SEL = P3SEL_INIT; e0be: c2 43 1b 00 mov.b #0, &0x001b ;r3 As==00 P1DIR = P1DIR_INIT; //Init port direction register of port1 e0c2: f2 40 f9 ff mov.b #-7, &0x0022 ;#0xfff9 e0c6: 22 00 P2DIR = P2DIR_INIT; //Init port direction register of port2 e0c8: f2 40 ef ff mov.b #-17, &0x002a ;#0xffef e0cc: 2a 00 P3DIR = P3DIR_INIT; e0ce: f2 40 7b 00 mov.b #123, &0x001a ;#0x007b e0d2: 1a 00 P1IES = P1IES_INIT; //init port interrupts e0d4: e2 43 24 00 mov.b #2, &0x0024 ;r3 As==10 P2IES = P2IES_INIT; e0d8: f2 40 10 00 mov.b #16, &0x002c ;#0x0010 e0dc: 2c 00 P1IE = P1IE_INIT; e0de: e2 43 25 00 mov.b #2, &0x0025 ;r3 As==10 P2IE = P2IE_INIT; e0e2: f2 40 10 00 mov.b #16, &0x002d ;#0x0010 e0e6: 2d 00 BCSCTL1 |= RSEL0 | RSEL1 | RSEL2; e0e8: f2 d0 07 00 bis.b #7, &0x0057 ;#0x0007 e0ec: 57 00 DCOCTL |= DCO0 | DCO1 | DCO2; e0ee: f2 d0 e0 ff bis.b #-32, &0x0056 ;#0xffe0 e0f2: 56 00 BCSCTL2 = DCOR; e0f4: d2 43 58 00 mov.b #1, &0x0058 ;r3 As==01 ME2 |= USPIE0; //enable SPI e0f8: d2 d3 05 00 bis.b #1, &0x0005 ;r3 As==01 U0CTL = CHAR | SYNC | MM | SWRST; e0fc: f2 40 17 00 mov.b #23, &0x0070 ;#0x0017 e100: 70 00 U0TCTL = CKPH | STC | SSEL_3; e102: f2 40 b2 ff mov.b #-78, &0x0071 ;#0xffb2 e106: 71 00 U0BR0 = 2; //divide by 5 = 1Mhz e108: e2 43 74 00 mov.b #2, &0x0074 ;r3 As==10 U0BR1 = 0; e10c: c2 43 75 00 mov.b #0, &0x0075 ;r3 As==00 U0MCTL = 0; e110: c2 43 73 00 mov.b #0, &0x0073 ;r3 As==00 U0CTL &= ~SWRST; // Initialize USART state machine e114: d2 c3 70 00 bic.b #1, &0x0070 ;r3 As==01 } e118: 30 41 ret 0000e11a : void init_UART_SPI() { U0CTL |= SWRST; // disable the state machine e11a: d2 d3 70 00 bis.b #1, &0x0070 ;r3 As==01 ME2 &= ~UTXE0; //disable UART e11e: e2 c3 05 00 bic.b #2, &0x0005 ;r3 As==10 ME2 |= USPIE0; //enable SPI e122: d2 d3 05 00 bis.b #1, &0x0005 ;r3 As==01 U0CTL = CHAR | SYNC | MM | SWRST; e126: f2 40 17 00 mov.b #23, &0x0070 ;#0x0017 e12a: 70 00 U0TCTL = CKPH | STC | SSEL_3; e12c: f2 40 b2 ff mov.b #-78, &0x0071 ;#0xffb2 e130: 71 00 U0BR0 = 2; //divide by 5 = 1Mhz e132: e2 43 74 00 mov.b #2, &0x0074 ;r3 As==10 U0BR1 = 0; e136: c2 43 75 00 mov.b #0, &0x0075 ;r3 As==00 U0MCTL = 0; e13a: c2 43 73 00 mov.b #0, &0x0073 ;r3 As==00 U0CTL &= ~SWRST; // Initialize USART state machine e13e: d2 c3 70 00 bic.b #1, &0x0070 ;r3 As==01 } e142: 30 41 ret e144: 50 6f 6e 67 addc.b 26478(r15),r0 ;0x676e(r15) e148: 21 00 .word 0x0021; ???? e14a: 00 43 clr r0 e14c: 54 52 00 72 add.b &0x7200,r4 e150: 65 73 subc.b #2, r5 ;r3 As==10 e152: 65 74 subc.b @r4, r5 ... 0000e156
: /** Main function. */ int main(void) { e156: 31 40 a8 02 mov #680, r1 ;#0x02a8 char i=0; unsigned char interchip[23],rxbuf[64]; unsigned char length=0; sys_init(); e15a: b0 12 a2 e0 call #0xe0a2 init_UART_SPI(); e15e: b0 12 1a e1 call #0xe11a memset(rxbuf, 0, 64); e162: 3e 40 40 00 mov #64, r14 ;#0x0040 e166: 0a 41 mov r1, r10 e168: 3a 50 18 00 add #24, r10 ;#0x0018 e16c: 0f 4a mov r10, r15 e16e: cf 43 00 00 mov.b #0, 0(r15) ;r3 As==00, 0x0000(r15) e172: 1f 53 inc r15 e174: 1e 83 dec r14 e176: fb 23 jnz $-8 ;abs 0xe16e P3OUT &= ~CSn; //power on reset, strobe CSn e178: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 delay(0x00FF); e17c: 3f 40 ff 00 mov #255, r15 ;#0x00ff e180: b0 12 74 e0 call #0xe074 P3OUT |= CSn; e184: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 delay(0xFFFF); e188: 3f 43 mov #-1, r15 ;r3 As==11 e18a: b0 12 74 e0 call #0xe074 //values straight from RF_STUDIO CCXX_SPI_STROBE(CCxxx0_SRES); //reset chip e18e: 7f 40 30 00 mov.b #48, r15 ;#0x0030 e192: b0 12 ac e5 call #0xe5ac //delay(0xFFF); CCXX_WRITE_SPI_RF_SETTINGS(); e196: b0 12 bc e2 call #0xe2bc CCXX_SPI_STROBE(CCxxx0_SIDLE); //flush the buffer, all bytes sent e19a: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e19e: b0 12 ac e5 call #0xe5ac do{ i = CCXX_SPI_RDREG(CCxxx0_MARCSTATE);//wait for IDLE e1a2: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e1a6: b0 12 e2 e5 call #0xe5e2 }while(i != 1); e1aa: 5f 93 cmp.b #1, r15 ;r3 As==01 e1ac: fa 23 jnz $-10 ;abs 0xe1a2 flags=0; e1ae: 82 43 12 02 mov #0, &0x0212 ;r3 As==00 P2IFG=0x00; e1b2: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 P1IFG=0x00; e1b6: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 P3OUT ^= LED_RED; e1ba: f2 e0 10 00 xor.b #16, &0x0019 ;#0x0010 e1be: 19 00 delay(0xFF); //lil bit O delay e1c0: 3f 40 ff 00 mov #255, r15 ;#0x00ff e1c4: b0 12 74 e0 call #0xe074 P3OUT ^= LED_RED; e1c8: f2 e0 10 00 xor.b #16, &0x0019 ;#0x0010 e1cc: 19 00 eint();//enable interrupts! e1ce: 32 d2 eint //CCXX_SPI_WRREG(CCxxx0_CHANNR, CCXX_SPI_RDREG(CCxxx0_CHANNR)+1); //ONLY FOR FREQ TEST RX_MODE(); //set the rad io to RX mode e1d0: b0 12 5a e4 call #0xe45a while (1) //main loop, never ends... { if((flags & ALLSPICE_RDY) == ALLSPICE_RDY) //Allspice node is talking to us e1d4: 92 b3 12 02 bit #1, &0x0212 ;r3 As==01 e1d8: 32 24 jz $+102 ;abs 0xe23e { dint(); e1da: 32 c2 dint P3OUT |= LED_RED; e1dc: f2 d0 10 00 bis.b #16, &0x0019 ;#0x0010 e1e0: 19 00 //memset(rxbuf, 0, 64); length = RX_STRING(rxbuf, 60) + 1; e1e2: 7e 40 3c 00 mov.b #60, r14 ;#0x003c e1e6: 0f 4a mov r10, r15 e1e8: b0 12 84 e4 call #0xe484 e1ec: 4b 4f mov.b r15, r11 e1ee: 5b 53 inc.b r11 if((LQI & bit7) == bit7) //CRC ok! e1f0: c2 93 0f 02 tst.b &0x020f e1f4: 1e 34 jge $+62 ;abs 0xe232 { P3OUT |= LED_GRN; e1f6: f2 d0 20 00 bis.b #32, &0x0019 ;#0x0020 e1fa: 19 00 TX_STRING("Pong!\0",5); //NOT SPECIFIC ENOUGH! Need to place CALLSIGN here e1fc: 7e 40 05 00 mov.b #5, r14 ;#0x0005 e200: 3f 40 44 e1 mov #-7868, r15 ;#0xe144 e204: b0 12 60 e5 call #0xe560 P3OUT &= ~LED_GRN; e208: f2 f0 df ff and.b #-33, &0x0019 ;#0xffdf e20c: 19 00 P2IFG &= ~GDO0; e20e: f2 f0 ef ff and.b #-17, &0x002b ;#0xffef e212: 2b 00 //CCXX_SPI_WRREG(CCxxx0_CHANNR, CCXX_SPI_RDREG(CCxxx0_CHANNR)+1); //ONLY FOR FREQ TEST RX_MODE(); //set the radio back to RX mode so we don't miss any packets! e214: b0 12 5a e4 call #0xe45a //FREQ TEST //length = sprintf(interchip,"%s | RSSI:%ddBm Chan:%d ",rxbuf, RSSI_DBM,(unsigned char)(CCXX_SPI_RDREG(CCxxx0_CHANNR)-1)); //send_string(interchip, length+1); //send byte //END FREQ TEST send_string(rxbuf, length); //send byte e218: 4e 4b mov.b r11, r14 e21a: 0f 4a mov r10, r15 e21c: b0 12 b8 e7 call #0xe7b8 P1IFG &= ~ARB_RX; //and clear the interrupt line for the arbiter e220: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 else { P2IFG &= ~GDO0; RX_MODE(); //set the radio back to RX mode so we don't miss any packets! } P3OUT &= ~LED_RED; e224: f2 f0 ef ff and.b #-17, &0x0019 ;#0xffef e228: 19 00 //clean up flags &= ~ALLSPICE_RDY; // clear the flag e22a: 92 c3 12 02 bic #1, &0x0212 ;r3 As==01 eint(); e22e: 32 d2 eint e230: d1 3f jmp $-92 ;abs 0xe1d4 send_string(rxbuf, length); //send byte P1IFG &= ~ARB_RX; //and clear the interrupt line for the arbiter } else { P2IFG &= ~GDO0; e232: f2 f0 ef ff and.b #-17, &0x002b ;#0xffef e236: 2b 00 RX_MODE(); //set the radio back to RX mode so we don't miss any packets! e238: b0 12 5a e4 call #0xe45a e23c: f3 3f jmp $-24 ;abs 0xe224 //clean up flags &= ~ALLSPICE_RDY; // clear the flag eint(); } else if((flags & ARBITER_RDY) == ARBITER_RDY) //Arbiter has something to say e23e: a2 b3 12 02 bit #2, &0x0212 ;r3 As==10 e242: 35 24 jz $+108 ;abs 0xe2ae { dint(); e244: 32 c2 dint //memset(interchip, 0, 23); P3OUT |= LED_GRN; e246: f2 d0 20 00 bis.b #32, &0x0019 ;#0x0020 e24a: 19 00 status = 0; e24c: c2 43 14 02 mov.b #0, &0x0214 ;r3 As==00 length = get_string(interchip); e250: 0f 41 mov r1, r15 e252: b0 12 f2 e6 call #0xe6f2 e256: 4b 4f mov.b r15, r11 P1IFG &= ~ARB_RX; e258: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 if(!memcmp(CALLSIGN,interchip,3)) e25c: 3d 40 03 00 mov #3, r13 ;#0x0003 e260: 0e 41 mov r1, r14 e262: 3f 40 4b e1 mov #-7861, r15 ;#0xe14b e266: b0 12 90 e8 call #0xe890 e26a: 0f 93 tst r15 e26c: 12 20 jnz $+38 ;abs 0xe292 { if(strstr( interchip, "reset" ) != NULL) e26e: 3e 40 4f e1 mov #-7857, r14 ;#0xe14f e272: 0f 41 mov r1, r15 e274: b0 12 c0 e8 call #0xe8c0 e278: 0f 93 tst r15 e27a: 07 20 jnz $+16 ;abs 0xe28a P2IFG &= ~GDO0; RX_MODE(); } flags &= ~ARBITER_RDY; e27c: a2 c3 12 02 bic #2, &0x0212 ;r3 As==10 P3OUT &= ~LED_GRN; e280: f2 f0 df ff and.b #-33, &0x0019 ;#0xffdf e284: 19 00 eint(); e286: 32 d2 eint e288: a5 3f jmp $-180 ;abs 0xe1d4 if(!memcmp(CALLSIGN,interchip,3)) { if(strstr( interchip, "reset" ) != NULL) { WDTCTL = WDTCNTCL|WDTPW; e28a: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e28e: 20 01 while(1); //wait for timeout e290: ff 3f jmp $+0 ;abs 0xe290 } } else { if(length > 0 && length < 64) e292: 4e 4b mov.b r11, r14 e294: 7e 53 add.b #-1, r14 ;r3 As==11 e296: 7e 90 3f 00 cmp.b #63, r14 ;#0x003f e29a: 03 2c jc $+8 ;abs 0xe2a2 TX_STRING(interchip,length-1); e29c: 0f 41 mov r1, r15 e29e: b0 12 60 e5 call #0xe560 P2IFG &= ~GDO0; e2a2: f2 f0 ef ff and.b #-17, &0x002b ;#0xffef e2a6: 2b 00 RX_MODE(); e2a8: b0 12 5a e4 call #0xe45a e2ac: e7 3f jmp $-48 ;abs 0xe27c flags &= ~ARBITER_RDY; P3OUT &= ~LED_GRN; eint(); } else LPM3; //Go to sleep, when we wake, something has happened e2ae: 32 d0 d0 00 bis #208, r2 ;#0x00d0 e2b2: 90 3f jmp $-222 ;abs 0xe1d4 } } e2b4: 31 50 58 00 add #88, r1 ;#0x0058 e2b8: 30 40 3e e9 br #0xe93e 0000e2bc : void CCXX_WRITE_SPI_RF_SETTINGS() { // Write register settings CCXX_SPI_WRREG(CCxxx0_IOCFG2, P2_IOCFG2); // GDO2 output pin config. e2bc: 7e 40 0b 00 mov.b #11, r14 ;#0x000b e2c0: 4f 43 clr.b r15 e2c2: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_IOCFG0, P2_IOCFG0); // GDO0 output pin config. e2c6: 7e 40 06 00 mov.b #6, r14 ;#0x0006 e2ca: 6f 43 mov.b #2, r15 ;r3 As==10 e2cc: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_PKTLEN, P2_PKTLEN); // Packet length. e2d0: 7e 40 3c 00 mov.b #60, r14 ;#0x003c e2d4: 7f 40 06 00 mov.b #6, r15 ;#0x0006 e2d8: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_PKTCTRL1, P2_PKTCTRL1); // Packet automation control. e2dc: 6e 42 mov.b #4, r14 ;r2 As==10 e2de: 7f 40 07 00 mov.b #7, r15 ;#0x0007 e2e2: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_PKTCTRL0, P2_PKTCTRL0); // Packet automation control. e2e6: 7e 40 05 00 mov.b #5, r14 ;#0x0005 e2ea: 7f 42 mov.b #8, r15 ;r2 As==11 e2ec: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_ADDR, P2_ADDR); // Device address. e2f0: 5e 43 mov.b #1, r14 ;r3 As==01 e2f2: 7f 40 09 00 mov.b #9, r15 ;#0x0009 e2f6: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_CHANNR, P2_CHANNR); // Channel number. e2fa: 7e 40 9a ff mov.b #-102, r14 ;#0xff9a e2fe: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e302: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FSCTRL1, P2_FSCTRL1); // Freq synthesizer control. e306: 7e 40 0a 00 mov.b #10, r14 ;#0x000a e30a: 7f 40 0b 00 mov.b #11, r15 ;#0x000b e30e: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FSCTRL0, P2_FSCTRL0); // Freq synthesizer control. e312: 4e 43 clr.b r14 e314: 7f 40 0c 00 mov.b #12, r15 ;#0x000c e318: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FREQ2, P2_FREQ2); // Freq control word, high byte e31c: 7e 40 5c 00 mov.b #92, r14 ;#0x005c e320: 7f 40 0d 00 mov.b #13, r15 ;#0x000d e324: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FREQ1, P2_FREQ1); // Freq control word, mid byte. e328: 7e 40 4f 00 mov.b #79, r14 ;#0x004f e32c: 7f 40 0e 00 mov.b #14, r15 ;#0x000e e330: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FREQ0, P2_FREQ0); // Freq control word, low byte. e334: 7e 40 c0 ff mov.b #-64, r14 ;#0xffc0 e338: 7f 40 0f 00 mov.b #15, r15 ;#0x000f e33c: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_MDMCFG4, P2_MDMCFG4); // Modem configuration. e340: 7e 40 2d 00 mov.b #45, r14 ;#0x002d e344: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e348: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_MDMCFG3, P2_MDMCFG3); // Modem configuration. e34c: 7e 40 3b 00 mov.b #59, r14 ;#0x003b e350: 7f 40 11 00 mov.b #17, r15 ;#0x0011 e354: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_MDMCFG2, P2_MDMCFG2); // Modem configuration. e358: 7e 40 73 00 mov.b #115, r14 ;#0x0073 e35c: 7f 40 12 00 mov.b #18, r15 ;#0x0012 e360: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_MDMCFG1, P2_MDMCFG1); // Modem configuration. e364: 7e 40 23 00 mov.b #35, r14 ;#0x0023 e368: 7f 40 13 00 mov.b #19, r15 ;#0x0013 e36c: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_MDMCFG0, P2_MDMCFG0); // Modem configuration. e370: 7e 40 b9 ff mov.b #-71, r14 ;#0xffb9 e374: 7f 40 14 00 mov.b #20, r15 ;#0x0014 e378: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_DEVIATN, P2_DEVIATN); // Modem dev (when FSK mod en) e37c: 5e 43 mov.b #1, r14 ;r3 As==01 e37e: 7f 40 15 00 mov.b #21, r15 ;#0x0015 e382: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_MCSM1 , P2_MCSM1 ); //MainRadio Cntrl State Machine e386: 7e 40 33 00 mov.b #51, r14 ;#0x0033 e38a: 7f 40 17 00 mov.b #23, r15 ;#0x0017 e38e: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_MCSM0 , P2_MCSM0 ); //MainRadio Cntrl State Machine e392: 7e 40 18 00 mov.b #24, r14 ;#0x0018 e396: 7f 40 18 00 mov.b #24, r15 ;#0x0018 e39a: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FOCCFG, P2_FOCCFG); // Freq Offset Compens. Config e39e: 7e 40 1d 00 mov.b #29, r14 ;#0x001d e3a2: 7f 40 19 00 mov.b #25, r15 ;#0x0019 e3a6: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_BSCFG, P2_BSCFG); // Bit synchronization config. e3aa: 7e 40 1c 00 mov.b #28, r14 ;#0x001c e3ae: 7f 40 1a 00 mov.b #26, r15 ;#0x001a e3b2: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_AGCCTRL2, P2_AGCCTRL2); // AGC control. e3b6: 7e 40 c7 ff mov.b #-57, r14 ;#0xffc7 e3ba: 7f 40 1b 00 mov.b #27, r15 ;#0x001b e3be: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_AGCCTRL1, P2_AGCCTRL1); // AGC control. e3c2: 4e 43 clr.b r14 e3c4: 7f 40 1c 00 mov.b #28, r15 ;#0x001c e3c8: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_AGCCTRL0, P2_AGCCTRL0); // AGC control. e3cc: 7e 40 b0 ff mov.b #-80, r14 ;#0xffb0 e3d0: 7f 40 1d 00 mov.b #29, r15 ;#0x001d e3d4: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FREND1, P2_FREND1); // Front end RX configuration. e3d8: 7e 40 b6 ff mov.b #-74, r14 ;#0xffb6 e3dc: 7f 40 21 00 mov.b #33, r15 ;#0x0021 e3e0: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FREND0, P2_FREND0); // Front end RX configuration. e3e4: 7e 40 10 00 mov.b #16, r14 ;#0x0010 e3e8: 7f 40 22 00 mov.b #34, r15 ;#0x0022 e3ec: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FSCAL3, P2_FSCAL3); // Frequency synthesizer cal. e3f0: 7e 40 ea ff mov.b #-22, r14 ;#0xffea e3f4: 7f 40 23 00 mov.b #35, r15 ;#0x0023 e3f8: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FSCAL2, P2_FSCAL2); // Frequency synthesizer cal. e3fc: 7e 40 0a 00 mov.b #10, r14 ;#0x000a e400: 7f 40 24 00 mov.b #36, r15 ;#0x0024 e404: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FSCAL1, P2_FSCAL1); // Frequency synthesizer cal. e408: 4e 43 clr.b r14 e40a: 7f 40 25 00 mov.b #37, r15 ;#0x0025 e40e: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FSCAL0, P2_FSCAL0); // Frequency synthesizer cal. e412: 7e 40 11 00 mov.b #17, r14 ;#0x0011 e416: 7f 40 26 00 mov.b #38, r15 ;#0x0026 e41a: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_FSTEST, P2_FSTEST); // Frequency synthesizer cal. e41e: 7e 40 59 00 mov.b #89, r14 ;#0x0059 e422: 7f 40 29 00 mov.b #41, r15 ;#0x0029 e426: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_TEST2, P2_TEST2); // Various test settings. e42a: 7e 40 88 ff mov.b #-120, r14 ;#0xff88 e42e: 7f 40 2c 00 mov.b #44, r15 ;#0x002c e432: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_TEST1, P2_TEST1); // Various test settings. e436: 7e 40 31 00 mov.b #49, r14 ;#0x0031 e43a: 7f 40 2d 00 mov.b #45, r15 ;#0x002d e43e: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_TEST0, P2_TEST0); // Various test settings. e442: 7e 40 0b 00 mov.b #11, r14 ;#0x000b e446: 7f 40 2e 00 mov.b #46, r15 ;#0x002e e44a: b0 12 3e e6 call #0xe63e CCXX_SPI_WRREG(CCxxx0_PATABLE, P2_PATABLE); // Output Power e44e: 7e 43 mov.b #-1, r14 ;r3 As==11 e450: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e454: b0 12 3e e6 call #0xe63e } e458: 30 41 ret 0000e45a : Interrupt driven! yay! */ void RX_MODE() { CCXX_SPI_STROBE(CCxxx0_SIDLE); e45a: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e45e: b0 12 ac e5 call #0xe5ac while(status!=15) //(15)31 for return to TX on complete, see MCSM1 e462: f2 90 0f 00 cmp.b #15, &0x0214 ;#0x000f e466: 14 02 e468: 08 24 jz $+18 ;abs 0xe47a CCXX_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... e46a: 7f 40 3d 00 mov.b #61, r15 ;#0x003d e46e: b0 12 ac e5 call #0xe5ac e472: f2 90 0f 00 cmp.b #15, &0x0214 ;#0x000f e476: 14 02 e478: f8 23 jnz $-14 ;abs 0xe46a CCXX_SPI_STROBE(CCxxx0_SRX);//Recieve Mode e47a: 7f 40 34 00 mov.b #52, r15 ;#0x0034 e47e: b0 12 ac e5 call #0xe5ac } e482: 30 41 ret 0000e484 : char RX_STRING(unsigned char *rxbuf, unsigned char length) { e484: 0b 12 push r11 e486: 0a 12 push r10 e488: 09 12 push r9 e48a: 08 12 push r8 e48c: 07 12 push r7 e48e: 06 12 push r6 e490: 09 4f mov r15, r9 e492: 47 4e mov.b r14, r7 unsigned char i, real_length, pkt_length; RSSI = 0; e494: c2 43 0e 02 mov.b #0, &0x020e ;r3 As==00 LQI = 0; e498: c2 43 0f 02 mov.b #0, &0x020f ;r3 As==00 pkt_length = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet e49c: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf e4a0: b0 12 e2 e5 call #0xe5e2 e4a4: 48 4f mov.b r15, r8 real_length = CCXX_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet e4a6: 7f 40 3b 00 mov.b #59, r15 ;#0x003b e4aa: b0 12 e2 e5 call #0xe5e2 e4ae: 46 4f mov.b r15, r6 for(i=0; i < length && i < pkt_length; i++) e4b0: 4a 43 clr.b r10 e4b2: 4a 97 cmp.b r7, r10 e4b4: 02 2c jc $+6 ;abs 0xe4ba e4b6: 58 93 cmp.b #1, r8 ;r3 As==01 e4b8: 2f 2c jc $+96 ;abs 0xe518 { rxbuf[i] = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the byte //tmpbuf[i] = rxbuf[i]; } rxbuf[i+1] = '\0';//set the NULL terminator e4ba: 4f 4a mov.b r10, r15 e4bc: 09 5f add r15, r9 e4be: c9 43 01 00 mov.b #0, 1(r9) ;r3 As==00, 0x0001(r9) RSSI = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the ESSI e4c2: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf e4c6: b0 12 e2 e5 call #0xe5e2 e4ca: c2 4f 0e 02 mov.b r15, &0x020e LQI = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the CRC e4ce: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf e4d2: b0 12 e2 e5 call #0xe5e2 e4d6: c2 4f 0f 02 mov.b r15, &0x020f PKTSTATUS = CCXX_SPI_RDREG(CCxxx0_PKTSTATUS); e4da: 7f 40 38 00 mov.b #56, r15 ;#0x0038 e4de: b0 12 e2 e5 call #0xe5e2 e4e2: c2 4f 10 02 mov.b r15, &0x0210 if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported e4e6: 4e 46 mov.b r6, r14 e4e8: 4f 48 mov.b r8, r15 e4ea: 2f 53 incd r15 e4ec: 0e 9f cmp r15, r14 e4ee: 03 24 jz $+8 ;abs 0xe4f6 LQI &= ~bit7; //force it to be INVALID! e4f0: f2 f0 7f 00 and.b #127, &0x020f ;#0x007f e4f4: 0f 02 if (RSSI >= 128) e4f6: 5f 42 0e 02 mov.b &0x020e,r15 e4fa: 7f 90 80 00 cmp.b #128, r15 ;#0x0080 e4fe: 09 28 jnc $+20 ;abs 0xe512 RSSI_DBM = (int)((int )(RSSI - 256) / 2) - 72; e500: 4e 4f mov.b r15, r14 e502: 0f 4e mov r14, r15 e504: 3f 50 00 ff add #-256, r15 ;#0xff00 e508: 02 30 jn $+6 ;abs 0xe50e e50a: 0f 11 rra r15 e50c: 14 3c jmp $+42 ;abs 0xe536 e50e: 1f 53 inc r15 e510: fc 3f jmp $-6 ;abs 0xe50a else RSSI_DBM = (RSSI / 2) - 72; e512: 12 c3 clrc e514: 4f 10 rrc.b r15 e516: 0f 3c jmp $+32 ;abs 0xe536 pkt_length = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CCXX_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) { rxbuf[i] = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the byte e518: 4f 4a mov.b r10, r15 e51a: 0b 49 mov r9, r11 e51c: 0b 5f add r15, r11 e51e: 7f 40 bf ff mov.b #-65, r15 ;#0xffbf e522: b0 12 e2 e5 call #0xe5e2 e526: cb 4f 00 00 mov.b r15, 0(r11) ;0x0000(r11) RSSI = 0; LQI = 0; pkt_length = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//length of the packet real_length = CCXX_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) e52a: 5a 53 inc.b r10 e52c: 4a 97 cmp.b r7, r10 e52e: c5 2f jc $-116 ;abs 0xe4ba e530: 4a 98 cmp.b r8, r10 e532: f2 2b jnc $-26 ;abs 0xe518 e534: c2 3f jmp $-122 ;abs 0xe4ba e536: 7f 50 b8 ff add.b #-72, r15 ;#0xffb8 e53a: c2 4f 02 02 mov.b r15, &0x0202 RSSI_DBM = (int)((int )(RSSI - 256) / 2) - 72; else RSSI_DBM = (RSSI / 2) - 72; CCXX_SPI_STROBE(CCxxx0_SFRX); //flush the buffer e53e: 7f 40 3a 00 mov.b #58, r15 ;#0x003a e542: b0 12 ac e5 call #0xe5ac CCXX_SPI_STROBE(CCxxx0_SIDLE); //return to IDLE state e546: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e54a: b0 12 ac e5 call #0xe5ac return i; //i = real length e54e: 4f 4a mov.b r10, r15 e550: 8f 11 sxt r15 } e552: 36 41 pop r6 e554: 37 41 pop r7 e556: 38 41 pop r8 e558: 39 41 pop r9 e55a: 3a 41 pop r10 e55c: 3b 41 pop r11 e55e: 30 41 ret 0000e560 : /** Transmit a string of bytes. */ void TX_STRING(unsigned char *txstring, unsigned char length) { e560: 0b 12 push r11 e562: 0a 12 push r10 e564: 0a 4f mov r15, r10 e566: 4b 4e mov.b r14, r11 //length += 3; do{ CCXX_SPI_STROBE(CCxxx0_SIDLE);//Idle e568: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e56c: b0 12 ac e5 call #0xe5ac }while((status & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle e570: f2 b0 70 00 bit.b #112, &0x0214 ;#0x0070 e574: 14 02 e576: f8 23 jnz $-14 ;abs 0xe568 { if(i < length) CCXX_SPI_WRREG(CCxxx0_TXFIFO, txstring[i]);//Write data to FIFO }*/ CCXX_SPI_BURST_WRREG(CCxxx0_TXFIFO_BURST, txstring, length); e578: 4f 4b mov.b r11, r15 e57a: 0d 4f mov r15, r13 e57c: 0e 4a mov r10, r14 e57e: 3f 40 7f 00 mov #127, r15 ;#0x007f e582: b0 12 86 e6 call #0xe686 CCXX_SPI_STROBE(CCxxx0_STX); // send tx strobe and TX begins, returns to 15 or 31 when complete (depending on MCSM1) e586: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e58a: b0 12 ac e5 call #0xe5ac do { CCXX_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... e58e: 7f 40 3d 00 mov.b #61, r15 ;#0x003d e592: b0 12 ac e5 call #0xe5ac if(status == 31) //fast RX mode yay e596: 5f 42 14 02 mov.b &0x0214,r15 e59a: 7f 90 1f 00 cmp.b #31, r15 ;#0x001f e59e: 03 24 jz $+8 ;abs 0xe5a6 break; }while((status & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //(15)31 for return to TX on complete, see MCSM1 e5a0: 7f f0 70 00 and.b #112, r15 ;#0x0070 e5a4: f4 23 jnz $-22 ;abs 0xe58e } e5a6: 3a 41 pop r10 e5a8: 3b 41 pop r11 e5aa: 30 41 ret 0000e5ac : #include "hardware.h" /** Strobe a command to the CCXX */ void CCXX_SPI_STROBE(char reg) { e5ac: 4e 4f mov.b r15, r14 status=0; e5ae: c2 43 14 02 mov.b #0, &0x0214 ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip e5b2: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e5b6: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 e5ba: fd 23 jnz $-4 ;abs 0xe5b6 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e5bc: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e e5c0: 1b 00 IFG2 &= ~URXIFG0; e5c2: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e5c6: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); e5ca: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e5ce: fd 27 jz $-4 ;abs 0xe5ca status = U0RXBUF; e5d0: d2 42 76 00 mov.b &0x0076,&0x0214 e5d4: 14 02 P3OUT |= CSn; //pull CSn high, we're done with the transfer e5d6: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e5da: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 e5de: 1b 00 } e5e0: 30 41 ret 0000e5e2 : /** Read a register from the CCXX */ char CCXX_SPI_RDREG(char reg) { e5e2: 4e 4f mov.b r15, r14 unsigned char rx=0; if(reg >= 0x30) e5e4: 7f 90 30 00 cmp.b #48, r15 ;#0x0030 e5e8: 1e 38 jl $+62 ;abs 0xe626 reg |= 0xC0; e5ea: 7e d0 c0 ff bis.b #-64, r14 ;#0xffc0 else reg |= 0x80; status=0; e5ee: c2 43 14 02 mov.b #0, &0x0214 ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip e5f2: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e5f6: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 e5fa: fd 23 jnz $-4 ;abs 0xe5f6 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e5fc: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e e600: 1b 00 IFG2 &= ~URXIFG0; e602: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e606: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); e60a: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e60e: fd 27 jz $-4 ;abs 0xe60a status = U0RXBUF; e610: d2 42 76 00 mov.b &0x0076,&0x0214 e614: 14 02 IFG2 &= ~URXIFG0; e616: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = 0; e61a: c2 43 77 00 mov.b #0, &0x0077 ;r3 As==00 while (!(IFG2 & URXIFG0)); e61e: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e622: fd 27 jz $-4 ;abs 0xe61e e624: 03 3c jmp $+8 ;abs 0xe62c { unsigned char rx=0; if(reg >= 0x30) reg |= 0xC0; else reg |= 0x80; e626: 7e d0 80 ff bis.b #-128, r14 ;#0xff80 e62a: e1 3f jmp $-60 ;abs 0xe5ee status = U0RXBUF; IFG2 &= ~URXIFG0; U0TXBUF = 0; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; e62c: 5f 42 76 00 mov.b &0x0076,r15 P3OUT |= CSn; //pull CSn high, we're done with the transfer e630: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e634: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 e638: 1b 00 return rx; e63a: 8f 11 sxt r15 } e63c: 30 41 ret 0000e63e : /** Write a register to the CCXX */ void CCXX_SPI_WRREG(char reg, char byte) { e63e: 4d 4f mov.b r15, r13 unsigned char dummy; status=0; e640: c2 43 14 02 mov.b #0, &0x0214 ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip e644: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e648: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 e64c: fd 23 jnz $-4 ;abs 0xe648 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e64e: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e e652: 1b 00 IFG2 &= ~URXIFG0; e654: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e658: c2 4d 77 00 mov.b r13, &0x0077 while (!(IFG2 & URXIFG0)); e65c: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e660: fd 27 jz $-4 ;abs 0xe65c status = U0RXBUF; e662: d2 42 76 00 mov.b &0x0076,&0x0214 e666: 14 02 IFG2 &= ~URXIFG0; e668: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = byte; e66c: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); e670: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e674: fd 27 jz $-4 ;abs 0xe670 dummy = U0RXBUF; e676: 5f 42 76 00 mov.b &0x0076,r15 P3OUT |= CSn; //pull CSn high, we're done with the transfer e67a: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e67e: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 e682: 1b 00 } e684: 30 41 ret 0000e686 : /** Write many bytes to the CCXX */ void CCXX_SPI_BURST_WRREG(char reg, char *buf, char length) { e686: 4c 4f mov.b r15, r12 unsigned char dummy; unsigned int index; status=0; e688: c2 43 14 02 mov.b #0, &0x0214 ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip e68c: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e690: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 e694: fd 23 jnz $-4 ;abs 0xe690 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e696: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e e69a: 1b 00 IFG2 &= ~URXIFG0; e69c: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e6a0: c2 4c 77 00 mov.b r12, &0x0077 while (!(IFG2 & URXIFG0)); e6a4: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e6a8: fd 27 jz $-4 ;abs 0xe6a4 status = U0RXBUF; e6aa: d2 42 76 00 mov.b &0x0076,&0x0214 e6ae: 14 02 IFG2 &= ~URXIFG0; e6b0: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = length; e6b4: c2 4d 77 00 mov.b r13, &0x0077 while (!(IFG2 & URXIFG0)); e6b8: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e6bc: fd 27 jz $-4 ;abs 0xe6b8 dummy = U0RXBUF; e6be: 5f 42 76 00 mov.b &0x0076,r15 for(index = 0; index < length; index++) e6c2: 0c 43 clr r12 e6c4: 8d 11 sxt r13 e6c6: 0c 9d cmp r13, r12 e6c8: 0e 2c jc $+30 ;abs 0xe6e6 { IFG2 &= ~URXIFG0; e6ca: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = buf[index]; e6ce: 0f 4e mov r14, r15 e6d0: 0f 5c add r12, r15 e6d2: e2 4f 77 00 mov.b @r15, &0x0077 while (!(IFG2 & URXIFG0)); e6d6: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e6da: fd 27 jz $-4 ;abs 0xe6d6 dummy = U0RXBUF; e6dc: 5f 42 76 00 mov.b &0x0076,r15 IFG2 &= ~URXIFG0; U0TXBUF = length; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; for(index = 0; index < length; index++) e6e0: 1c 53 inc r12 e6e2: 0c 9d cmp r13, r12 e6e4: f2 2b jnc $-26 ;abs 0xe6ca U0TXBUF = buf[index]; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; } P3OUT |= CSn; //pull CSn high, we're done with the transfer e6e6: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e6ea: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 e6ee: 1b 00 } e6f0: 30 41 ret 0000e6f2 : #include "hardware.h" /** Strobe a command to the CCXX */ void CCXX_SPI_STROBE(char reg) { e6f2: 0b 12 push r11 e6f4: 0a 12 push r10 e6f6: 09 12 push r9 e6f8: 0a 4f mov r15, r10 status=0; P3OUT &= ~CSn; //pull CSn low to activate chip e6fa: 4d 43 clr.b r13 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e6fc: 0b 43 clr r11 e6fe: 0c 43 clr r12 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e700: e2 c2 22 00 bic.b #4, &0x0022 ;r2 As==10 IFG2 &= ~URXIFG0; e704: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e708: 0b 24 jz $+24 ;abs 0xe720 U0TXBUF = reg; while (!(IFG2 & URXIFG0)); e70a: 1b 53 inc r11 e70c: 0c 63 adc r12 status = U0RXBUF; e70e: 3b 90 20 a1 cmp #-24288,r11 ;#0xa120 e712: 03 20 jnz $+8 ;abs 0xe71a e714: 3c 90 07 00 cmp #7, r12 ;#0x0007 e718: 40 24 jz $+130 ;abs 0xe79a e71a: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e71e: f5 23 jnz $-20 ;abs 0xe70a P3OUT |= CSn; //pull CSn high, we're done with the transfer P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e720: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 } e724: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e728: 20 01 /** e72a: 7e 42 mov.b #8, r14 ;r2 As==11 Read a register from the CCXX */ char CCXX_SPI_RDREG(char reg) e72c: 4d 5d rla.b r13 { e72e: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 e732: fd 23 jnz $-4 ;abs 0xe72e unsigned char rx=0; e734: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e738: 4f 43 clr.b r15 e73a: 4f 63 adc.b r15 e73c: 4d df bis.b r15, r13 if(reg >= 0x30) e73e: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 reg |= 0xC0; e742: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 e746: fd 27 jz $-4 ;abs 0xe742 else e748: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 P3OUT |= CSn; //pull CSn high, we're done with the transfer P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode } /** e74c: 7e 53 add.b #-1, r14 ;r3 As==11 e74e: ee 23 jnz $-34 ;abs 0xe72c if(reg >= 0x30) reg |= 0xC0; else reg |= 0x80; status=0; e750: 49 4d mov.b r13, r9 P3OUT &= ~CSn; //pull CSn low to activate chip e752: 0c 43 clr r12 e754: 4f 4d mov.b r13, r15 e756: 3f 53 add #-1, r15 ;r3 As==11 e758: 0c 9f cmp r15, r12 e75a: 23 2c jc $+72 ;abs 0xe7a2 e75c: 0b 4f mov r15, r11 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e75e: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e762: 20 01 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e764: 7e 42 mov.b #8, r14 ;r2 As==11 IFG2 &= ~URXIFG0; e766: 4d 5d rla.b r13 U0TXBUF = reg; e768: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 e76c: fd 23 jnz $-4 ;abs 0xe768 while (!(IFG2 & URXIFG0)); e76e: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e772: 4f 43 clr.b r15 e774: 4f 63 adc.b r15 e776: 4d df bis.b r15, r13 status = U0RXBUF; e778: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 e77c: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 e780: fd 27 jz $-4 ;abs 0xe77c IFG2 &= ~URXIFG0; e782: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 status=0; P3OUT &= ~CSn; //pull CSn low to activate chip while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e786: 7e 53 add.b #-1, r14 ;r3 As==11 e788: ee 23 jnz $-34 ;abs 0xe766 while (!(IFG2 & URXIFG0)); status = U0RXBUF; IFG2 &= ~URXIFG0; U0TXBUF = 0; while (!(IFG2 & URXIFG0)); e78a: 0f 4a mov r10, r15 e78c: 0f 5c add r12, r15 e78e: cf 4d 00 00 mov.b r13, 0(r15) ;0x0000(r15) else reg |= 0x80; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip e792: 1c 53 inc r12 e794: 0c 9b cmp r11, r12 e796: e3 2b jnc $-56 ;abs 0xe75e e798: 04 3c jmp $+10 ;abs 0xe7a2 IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); status = U0RXBUF; e79a: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e79e: 20 01 e7a0: bc 3f jmp $-134 ;abs 0xe71a IFG2 &= ~URXIFG0; U0TXBUF = 0; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; e7a2: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 P3OUT |= CSn; //pull CSn high, we're done with the transfer P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e7a6: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e7aa: 20 01 return rx; e7ac: 4f 49 mov.b r9, r15 e7ae: 8f 11 sxt r15 } e7b0: 39 41 pop r9 e7b2: 3a 41 pop r10 e7b4: 3b 41 pop r11 e7b6: 30 41 ret 0000e7b8 : /** Write a register to the CCXX */ e7b8: 0b 12 push r11 e7ba: 0a 12 push r10 e7bc: 0a 4f mov r15, r10 void CCXX_SPI_WRREG(char reg, char byte) { unsigned char dummy; e7be: 0c 43 clr r12 e7c0: 0d 43 clr r13 status=0; e7c2: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e7c6: 02 20 jnz $+6 ;abs 0xe7cc P3OUT &= ~CSn; //pull CSn low to activate chip e7c8: 0f 43 clr r15 e7ca: 5f 3c jmp $+192 ;abs 0xe88a while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e7cc: e2 d2 22 00 bis.b #4, &0x0022 ;r2 As==10 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e7d0: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 IFG2 &= ~URXIFG0; e7d4: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e7d8: 0b 24 jz $+24 ;abs 0xe7f0 U0TXBUF = reg; while (!(IFG2 & URXIFG0)); e7da: 1c 53 inc r12 e7dc: 0d 63 adc r13 status = U0RXBUF; e7de: 3c 90 20 a1 cmp #-24288,r12 ;#0xa120 e7e2: 03 20 jnz $+8 ;abs 0xe7ea e7e4: 3d 90 07 00 cmp #7, r13 ;#0x0007 e7e8: 4c 24 jz $+154 ;abs 0xe882 e7ea: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e7ee: f5 23 jnz $-20 ;abs 0xe7da IFG2 &= ~URXIFG0; U0TXBUF = byte; while (!(IFG2 & URXIFG0)); e7f0: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e7f4: 20 01 dummy = U0RXBUF; e7f6: 4d 4e mov.b r14, r13 P3OUT |= CSn; //pull CSn high, we're done with the transfer e7f8: 7c 42 mov.b #8, r12 ;r2 As==11 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode } e7fa: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e7fe: fd 23 jnz $-4 ;abs 0xe7fa e800: 4f 4d mov.b r13, r15 e802: 4f 5f rla.b r15 e804: 4f 43 clr.b r15 e806: 4f 6f rlc.b r15 e808: c2 df 21 00 bis.b r15, &0x0021 /** e80c: e2 c2 21 00 bic.b #4, &0x0021 ;r2 As==10 Write many bytes to the CCXX e810: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e814: fd 27 jz $-4 ;abs 0xe810 */ e816: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 void CCXX_SPI_BURST_WRREG(char reg, char *buf, char length) e81a: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 { e81e: 4d 5d rla.b r13 IFG2 &= ~URXIFG0; U0TXBUF = byte; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; P3OUT |= CSn; //pull CSn high, we're done with the transfer e820: 7c 53 add.b #-1, r12 ;r3 As==11 e822: eb 23 jnz $-40 ;abs 0xe7fa unsigned char dummy; unsigned int index; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip e824: 4b 4e mov.b r14, r11 e826: 0e 43 clr r14 e828: 1b 93 cmp #1, r11 ;r3 As==01 e82a: 21 24 jz $+68 ;abs 0xe86e while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e82c: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e830: 20 01 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e832: 0f 4a mov r10, r15 e834: 0f 5e add r14, r15 e836: 6d 4f mov.b @r15, r13 e838: 7c 42 mov.b #8, r12 ;r2 As==11 IFG2 &= ~URXIFG0; U0TXBUF = reg; e83a: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e83e: fd 23 jnz $-4 ;abs 0xe83a while (!(IFG2 & URXIFG0)); e840: 4f 4d mov.b r13, r15 e842: 4f 5f rla.b r15 e844: 4f 43 clr.b r15 e846: 4f 6f rlc.b r15 e848: c2 df 21 00 bis.b r15, &0x0021 status = U0RXBUF; e84c: e2 c2 21 00 bic.b #4, &0x0021 ;r2 As==10 e850: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e854: fd 27 jz $-4 ;abs 0xe850 IFG2 &= ~URXIFG0; e856: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 U0TXBUF = length; e85a: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 while (!(IFG2 & URXIFG0)); e85e: 4d 5d rla.b r13 P3OUT &= ~CSn; //pull CSn low to activate chip while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e860: 7c 53 add.b #-1, r12 ;r3 As==11 e862: eb 23 jnz $-40 ;abs 0xe83a unsigned char dummy; unsigned int index; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip e864: 1e 53 inc r14 e866: 0f 4b mov r11, r15 e868: 3f 53 add #-1, r15 ;r3 As==11 e86a: 0e 9f cmp r15, r14 e86c: df 2b jnc $-64 ;abs 0xe82c U0TXBUF = length; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; for(index = 0; index < length; index++) { e86e: e2 c2 22 00 bic.b #4, &0x0022 ;r2 As==10 IFG2 &= ~URXIFG0; e872: f2 d0 05 00 bis.b #5, &0x0021 ;#0x0005 e876: 21 00 U0TXBUF = buf[index]; e878: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e87c: 20 01 while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; e87e: 1f 43 mov #1, r15 ;r3 As==01 e880: 04 3c jmp $+10 ;abs 0xe88a IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); status = U0RXBUF; e882: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e886: 20 01 e888: b0 3f jmp $-158 ;abs 0xe7ea { IFG2 &= ~URXIFG0; U0TXBUF = buf[index]; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; } e88a: 3a 41 pop r10 e88c: 3b 41 pop r11 e88e: 30 41 ret 0000e890 : e890: 0b 12 push r11 e892: 0b 4d mov r13, r11 e894: 0d 93 tst r13 e896: 0a 24 jz $+22 ;abs 0xe8ac e898: 0c 4f mov r15, r12 e89a: 0d 4e mov r14, r13 e89c: 6e 4d mov.b @r13, r14 e89e: 1d 53 inc r13 e8a0: 6f 4c mov.b @r12, r15 e8a2: 1c 53 inc r12 e8a4: 4f 9e cmp.b r14, r15 e8a6: 04 20 jnz $+10 ;abs 0xe8b0 e8a8: 3b 53 add #-1, r11 ;r3 As==11 e8aa: f8 23 jnz $-14 ;abs 0xe89c e8ac: 0c 43 clr r12 e8ae: 05 3c jmp $+12 ;abs 0xe8ba e8b0: 5c 4c ff ff mov.b -1(r12),r12 ;0xffff(r12) e8b4: 5f 4d ff ff mov.b -1(r13),r15 ;0xffff(r13) e8b8: 0c 8f sub r15, r12 e8ba: 0f 4c mov r12, r15 e8bc: 3b 41 pop r11 e8be: 30 41 ret 0000e8c0 : e8c0: 0b 12 push r11 e8c2: 0a 12 push r10 e8c4: 09 12 push r9 e8c6: 08 12 push r8 e8c8: 0b 4f mov r15, r11 e8ca: 0a 4e mov r14, r10 e8cc: 69 4e mov.b @r14, r9 e8ce: 1a 53 inc r10 e8d0: 49 93 tst.b r9 e8d2: 15 24 jz $+44 ;abs 0xe8fe e8d4: 08 4a mov r10, r8 e8d6: 18 83 dec r8 e8d8: 18 53 inc r8 e8da: c8 93 00 00 tst.b 0(r8) ;0x0000(r8) e8de: fc 23 jnz $-6 ;abs 0xe8d8 e8e0: 08 8a sub r10, r8 e8e2: 6f 4b mov.b @r11, r15 e8e4: 1b 53 inc r11 e8e6: 4f 93 tst.b r15 e8e8: 0c 24 jz $+26 ;abs 0xe902 e8ea: 4f 99 cmp.b r9, r15 e8ec: fa 23 jnz $-10 ;abs 0xe8e2 e8ee: 0d 48 mov r8, r13 e8f0: 0e 4a mov r10, r14 e8f2: 0f 4b mov r11, r15 e8f4: b0 12 0e e9 call #0xe90e e8f8: 0f 93 tst r15 e8fa: f3 23 jnz $-24 ;abs 0xe8e2 e8fc: 3b 53 add #-1, r11 ;r3 As==11 e8fe: 0f 4b mov r11, r15 e900: 01 3c jmp $+4 ;abs 0xe904 e902: 0f 43 clr r15 e904: 38 41 pop r8 e906: 39 41 pop r9 e908: 3a 41 pop r10 e90a: 3b 41 pop r11 e90c: 30 41 ret 0000e90e : e90e: 0b 12 push r11 e910: 0b 4f mov r15, r11 e912: 0d 93 tst r13 e914: 02 20 jnz $+6 ;abs 0xe91a e916: 0d 43 clr r13 e918: 0f 3c jmp $+32 ;abs 0xe938 e91a: 6f 4e mov.b @r14, r15 e91c: 1e 53 inc r14 e91e: 6c 4b mov.b @r11, r12 e920: 4c 9f cmp.b r15, r12 e922: 06 20 jnz $+14 ;abs 0xe930 e924: 1b 53 inc r11 e926: 4c 93 tst.b r12 e928: f6 27 jz $-18 ;abs 0xe916 e92a: 3d 53 add #-1, r13 ;r3 As==11 e92c: f6 23 jnz $-18 ;abs 0xe91a e92e: f3 3f jmp $-24 ;abs 0xe916 e930: 4d 4c mov.b r12, r13 e932: 5f 4e ff ff mov.b -1(r14),r15 ;0xffff(r14) e936: 0d 8f sub r15, r13 e938: 0f 4d mov r13, r15 e93a: 3b 41 pop r11 e93c: 30 41 ret 0000e93e <__stop_progExec__>: e93e: ff 3f jmp $+0 ;abs 0xe93e Disassembly of section .vectors: 0000ffe0 : ffe0: 30 e0 30 e0 56 e0 36 e0 30 e0 30 e0 30 e0 30 e0 0.0.V.6.0.0.0.0. fff0: 30 e0 30 e0 30 e0 30 e0 30 e0 30 e0 30 e0 00 e0 0.0.0.0.0.0.0...