gng_rx.elf: file format elf32-msp430 SYMBOL TABLE: 0000e000 l d .text 00000000 .text 00000200 l d .data 00000000 .data 00000204 l d .bss 00000000 .bss 0000ffe0 l d .vectors 00000000 .vectors 00000000 l d .stab 00000000 .stab 00000000 l d .stabstr 00000000 .stabstr 00000070 l *ABS* 00000000 U0CTL 00000071 l *ABS* 00000000 U0TCTL 00000072 l *ABS* 00000000 U0RCTL 00000073 l *ABS* 00000000 U0MCTL 00000074 l *ABS* 00000000 U0BR0 00000075 l *ABS* 00000000 U0BR1 00000076 l *ABS* 00000000 U0RXBUF 00000077 l *ABS* 00000000 U0TXBUF 00000070 l *ABS* 00000000 UCTL 00000071 l *ABS* 00000000 UTCTL 00000072 l *ABS* 00000000 URCTL 00000073 l *ABS* 00000000 UMCTL 00000074 l *ABS* 00000000 UBR0 00000075 l *ABS* 00000000 UBR1 00000076 l *ABS* 00000000 RXBUF 00000077 l *ABS* 00000000 TXBUF 00000070 l *ABS* 00000000 UCTL0 00000071 l *ABS* 00000000 UTCTL0 00000072 l *ABS* 00000000 URCTL0 00000073 l *ABS* 00000000 UMCTL0 00000074 l *ABS* 00000000 UBR00 00000075 l *ABS* 00000000 UBR10 00000076 l *ABS* 00000000 RXBUF0 00000077 l *ABS* 00000000 TXBUF0 00000070 l *ABS* 00000000 UCTL_0 00000071 l *ABS* 00000000 UTCTL_0 00000072 l *ABS* 00000000 URCTL_0 00000073 l *ABS* 00000000 UMCTL_0 00000074 l *ABS* 00000000 UBR0_0 00000075 l *ABS* 00000000 UBR1_0 00000076 l *ABS* 00000000 RXBUF_0 00000077 l *ABS* 00000000 TXBUF_0 00000020 l *ABS* 00000000 P1IN 00000021 l *ABS* 00000000 P1OUT 00000022 l *ABS* 00000000 P1DIR 00000023 l *ABS* 00000000 P1IFG 00000024 l *ABS* 00000000 P1IES 00000025 l *ABS* 00000000 P1IE 00000026 l *ABS* 00000000 P1SEL 00000028 l *ABS* 00000000 P2IN 00000029 l *ABS* 00000000 P2OUT 0000002a l *ABS* 00000000 P2DIR 0000002b l *ABS* 00000000 P2IFG 0000002c l *ABS* 00000000 P2IES 0000002d l *ABS* 00000000 P2IE 0000002e l *ABS* 00000000 P2SEL 00000018 l *ABS* 00000000 P3IN 00000019 l *ABS* 00000000 P3OUT 0000001a l *ABS* 00000000 P3DIR 0000001b l *ABS* 00000000 P3SEL 0000012e l *ABS* 00000000 TA0IV 00000160 l *ABS* 00000000 TA0CTL 00000170 l *ABS* 00000000 TA0R 00000162 l *ABS* 00000000 TA0CCTL0 00000164 l *ABS* 00000000 TA0CCTL1 00000172 l *ABS* 00000000 TA0CCR0 00000174 l *ABS* 00000000 TA0CCR1 00000166 l *ABS* 00000000 TA0CCTL2 00000176 l *ABS* 00000000 TA0CCR2 00000056 l *ABS* 00000000 DCOCTL 00000057 l *ABS* 00000000 BCSCTL1 00000058 l *ABS* 00000000 BCSCTL2 00000128 l *ABS* 00000000 FCTL1 0000012a l *ABS* 00000000 FCTL2 0000012c l *ABS* 00000000 FCTL3 00000048 l *ABS* 00000000 ADC10DTC0 00000049 l *ABS* 00000000 ADC10DTC1 0000004a l *ABS* 00000000 ADC10AE0 000001b0 l *ABS* 00000000 ADC10CTL0 000001b2 l *ABS* 00000000 ADC10CTL1 000001b4 l *ABS* 00000000 ADC10MEM 000001bc l *ABS* 00000000 ADC10SA 00000120 l *ABS* 00000000 WDTCTL 00000000 l *ABS* 00000000 IE1 00000002 l *ABS* 00000000 IFG1 00000001 l *ABS* 00000000 IE2 00000003 l *ABS* 00000000 IFG2 00000005 l *ABS* 00000000 ME2 00000000 l df *ABS* 00000000 main.c 00000200 l O .data 00000001 make_gdb_happy 0000e8c0 l .text 00000000 Letext 00000000 l df *ABS* 00000000 spi_hardware.c 0000e99a l .text 00000000 Letext 00000000 l df *ABS* 00000000 interchip.c 0000eb38 l .text 00000000 Letext 00000000 l df *ABS* 00000000 atoi.c 0000ec0c l .text 00000000 Letext 00000000 l df *ABS* 00000000 snprintf.c 0000ec36 l .text 00000000 Letext 00000000 l df *ABS* 00000000 vsnprintf.c 0000ec36 l F .text 00000020 mem_putchar_limited 00000206 l .bss 00000000 max_s_size 00000204 l .bss 00000000 mem 0000ec7e l .text 00000000 Letext 00000000 l df *ABS* 00000000 vuprintf.c 00000202 l O .data 00000002 total_len 0000ec7e l F .text 00000030 PRINT 00000208 l .bss 00000000 __write_char 0000ecae l F .text 00000034 __write_pad 0000f298 l .text 00000000 Letext 00000000 l df *ABS* 00000000 strchr.c 0000f2b2 l .text 00000000 Letext 00000000 l df *ABS* 00000000 memchr.c 0000f2d6 l .text 00000000 Letext 00000000 l df *ABS* 00000000 memcmp.c 0000f306 l .text 00000000 Letext 00000000 l df *ABS* 00000000 strstr.c 0000f354 l .text 00000000 Letext 00000000 l df *ABS* 00000000 strncmp.c 0000f384 l .text 00000000 Letext 00000004 g *ABS* 00000000 __data_size 0000e8f6 g F .text 0000005c CCXX_SPI_RDREG 0000ea60 g F .text 000000d8 send_string 0000e11a g F .text 0000002a init_UART_SPI 0000ec0c g F .text 0000002a snprintf 0000f3b0 g .text 00000000 _etext 0000000d g *ABS* 00000000 __bss_size 0000f3ae w .text 00000000 __stop_progExec__ 0000e030 g .text 00000000 _unexpected_1_ 0000e030 w .text 00000000 vector_ffe0 0000e0a2 g F .text 00000078 sys_init 0000ec56 g F .text 00000028 vsnprintf 0000e036 g F .text 00000020 P2_VEC 0000e8c0 g F .text 00000036 CCXX_SPI_STROBE 0000e030 w .text 00000000 vector_ffec 0000e030 w .text 00000000 vector_fff0 0000f3b0 g *ABS* 00000000 __data_load_start 0000e030 g .text 00000000 __dtors_end 0000e030 w .text 00000000 vector_fffc 0000e952 g F .text 00000048 CCXX_SPI_WRREG 0000e518 g F .text 000002a2 CCXX_WRITE_SPI_RF_SETTINGS 0000e056 g .text 00000000 vector_ffe4 0000020a g O .bss 00000001 RSSI_DBM 0000ffe0 g O .vectors 00000020 InterruptVectors 0000e99a g F .text 000000c6 get_string 0000020b g O .bss 00000001 RSSI 0000f2b2 g F .text 00000024 memchr 0000e01c w .text 00000000 __do_clear_bss 0000f306 g F .text 0000004e strstr 0000f354 g F .text 00000030 strncmp 0000e030 w .text 00000000 vector_ffe2 0000e030 w .text 00000000 vector_ffe8 0000e034 w .text 00000000 _unexpected_ 0000e030 w .text 00000000 vector_fffa 0000ece2 g F .text 000005b6 vuprintf 0000f2d6 g F .text 00000030 memcmp 0000e056 g F .text 0000001e P1_VEC 0000e000 w .text 00000000 _reset_vector__ 0000e030 g .text 00000000 __ctors_start 0000e00a w .text 00000000 __do_copy_data 00000204 g .bss 00000000 __bss_start 0000e030 w .text 00000000 vector_ffee 0000e030 w .text 00000000 vector_fff4 0000e1ea g F .text 0000032e main 0000e030 w .text 00000000 vector_fff8 0000e030 w .text 00000000 vector_fff2 00010000 g .vectors 00000000 _vectors_end 0000e036 g .text 00000000 vector_ffe6 0000e074 g F .text 0000002e delay 0000020c g O .bss 00000001 LQI 0000e7e4 g F .text 000000dc RX_STRING 0000e000 w .text 00000000 __init_stack 0000020d g O .bss 00000001 PKTSTATUS 0000e030 g .text 00000000 __dtors_start 0000e030 g .text 00000000 __ctors_end 00000300 g *ABS* 00000000 __stack 00000204 g .data 00000000 _edata 00000211 g .bss 00000000 _end 0000020e g O .bss 00000002 flags 0000f384 g .text 00000000 __udivmodsi4 0000eb38 g F .text 000000d4 atoi 0000e030 w .text 00000000 vector_fff6 0000e7ba g F .text 0000002a RX_MODE 0000e004 w .text 00000000 __low_level_init 0000e02c w .text 00000000 __jump_to_main 0000f298 g F .text 0000001a strchr 00000200 g .data 00000000 __data_start 0000e030 w .text 00000000 vector_ffea 00000210 g O .bss 00000001 status Disassembly of section .text: 0000e000 <__init_stack>: e000: 31 40 00 03 mov #768, r1 ;#0x0300 0000e004 <__low_level_init>: e004: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e008: 20 01 0000e00a <__do_copy_data>: e00a: 3f 40 04 00 mov #4, r15 ;#0x0004 e00e: 0f 93 tst r15 e010: 05 24 jz $+12 ;abs 0xe01c e012: 2f 83 decd r15 e014: 9f 4f b0 f3 mov -3152(r15),512(r15);0xf3b0(r15), 0x0200(r15) e018: 00 02 e01a: fb 23 jnz $-8 ;abs 0xe012 0000e01c <__do_clear_bss>: e01c: 3f 40 0d 00 mov #13, r15 ;#0x000d e020: 0f 93 tst r15 e022: 04 24 jz $+10 ;abs 0xe02c e024: 1f 83 dec r15 e026: cf 43 04 02 mov.b #0, 516(r15);r3 As==00, 0x0204(r15) e02a: fc 23 jnz $-6 ;abs 0xe024 0000e02c <__jump_to_main>: e02c: 30 40 ea e1 br #0xe1ea 0000e030 <__ctors_end>: e030: 30 40 34 e0 br #0xe034 0000e034 <_unexpected_>: e034: 00 13 reti 0000e036 : These interrupts are caused by external pin events on handshake lines */ // Port 2 interripts : the balloon radio is talking to us interrupt (PORT2_VECTOR) P2_VEC(void) { e036: 0f 12 push r15 dint(); e038: 32 c2 dint if((P2IFG & GDO0) == GDO0) e03a: f2 b0 10 00 bit.b #16, &0x002b ;#0x0010 e03e: 2b 00 e040: 05 24 jz $+12 ;abs 0xe04c { flags |= GND_RDY; e042: 92 d3 0e 02 bis #1, &0x020e ;r3 As==01 LPM3_EXIT; e046: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) e04a: 02 00 //We need to grab that byte! } P2IFG=0x00; e04c: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 eint(); e050: 32 d2 eint } e052: 3f 41 pop r15 e054: 00 13 reti 0000e056 : // Port 1 interripts : The arbiter is talking to us interrupt (PORT1_VECTOR) P1_VEC(void) { e056: 0f 12 push r15 dint(); e058: 32 c2 dint if((P1IFG & ARB_RX) == ARB_RX) //The arbiter is sending us a string e05a: e2 b3 23 00 bit.b #2, &0x0023 ;r3 As==10 e05e: 05 24 jz $+12 ;abs 0xe06a { flags |= ARB_RDY; e060: a2 d3 0e 02 bis #2, &0x020e ;r3 As==10 LPM3_EXIT; e064: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) e068: 02 00 //We need to grab that byte! } P1IFG=0x00; e06a: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 eint(); e06e: 32 d2 eint } e070: 3f 41 pop r15 e072: 00 13 reti 0000e074 : Delay function. */ void delay(unsigned int d) { int i; for (i = 0; i: Set up the system */ void sys_init() { WDTCTL = WDTCTL_INIT; //Init watchdog timer e0a2: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e0a6: 20 01 P1OUT = P1OUT_INIT; //Init output data of port1 e0a8: f2 40 05 00 mov.b #5, &0x0021 ;#0x0005 e0ac: 21 00 P2OUT = P2OUT_INIT; //Init output data of port2 e0ae: c2 43 29 00 mov.b #0, &0x0029 ;r3 As==00 P3OUT = P3OUT_INIT; e0b2: d2 43 19 00 mov.b #1, &0x0019 ;r3 As==01 P1SEL = P1SEL_INIT; //Select port or module -function on port1 e0b6: c2 43 26 00 mov.b #0, &0x0026 ;r3 As==00 P2SEL = P2SEL_INIT; //Select port or module -function on port2 e0ba: c2 43 2e 00 mov.b #0, &0x002e ;r3 As==00 P3SEL = P3SEL_INIT; e0be: c2 43 1b 00 mov.b #0, &0x001b ;r3 As==00 P1DIR = P1DIR_INIT; //Init port direction register of port1 e0c2: f2 40 f9 ff mov.b #-7, &0x0022 ;#0xfff9 e0c6: 22 00 P2DIR = P2DIR_INIT; //Init port direction register of port2 e0c8: f2 40 ef ff mov.b #-17, &0x002a ;#0xffef e0cc: 2a 00 P3DIR = P3DIR_INIT; e0ce: f2 40 7b 00 mov.b #123, &0x001a ;#0x007b e0d2: 1a 00 P1IES = P1IES_INIT; //init port interrupts e0d4: c2 43 24 00 mov.b #0, &0x0024 ;r3 As==00 P2IES = P2IES_INIT; e0d8: f2 40 10 00 mov.b #16, &0x002c ;#0x0010 e0dc: 2c 00 P1IE = P1IE_INIT; e0de: c2 43 25 00 mov.b #0, &0x0025 ;r3 As==00 P2IE = P2IE_INIT; e0e2: f2 40 10 00 mov.b #16, &0x002d ;#0x0010 e0e6: 2d 00 BCSCTL1 |= RSEL0 | RSEL1 | RSEL2; e0e8: f2 d0 07 00 bis.b #7, &0x0057 ;#0x0007 e0ec: 57 00 DCOCTL |= DCO0 | DCO1 | DCO2; e0ee: f2 d0 e0 ff bis.b #-32, &0x0056 ;#0xffe0 e0f2: 56 00 BCSCTL2 = DCOR; e0f4: d2 43 58 00 mov.b #1, &0x0058 ;r3 As==01 ME2 |= USPIE0; //enable SPI e0f8: d2 d3 05 00 bis.b #1, &0x0005 ;r3 As==01 U0CTL = CHAR | SYNC | MM | SWRST; e0fc: f2 40 17 00 mov.b #23, &0x0070 ;#0x0017 e100: 70 00 U0TCTL = CKPH | STC | SSEL_3; e102: f2 40 b2 ff mov.b #-78, &0x0071 ;#0xffb2 e106: 71 00 U0BR0 = 2; //divide by 5 = 1Mhz e108: e2 43 74 00 mov.b #2, &0x0074 ;r3 As==10 U0BR1 = 0; e10c: c2 43 75 00 mov.b #0, &0x0075 ;r3 As==00 U0MCTL = 0; e110: c2 43 73 00 mov.b #0, &0x0073 ;r3 As==00 U0CTL &= ~SWRST; // Initialize USART state machine e114: d2 c3 70 00 bic.b #1, &0x0070 ;r3 As==01 } e118: 30 41 ret 0000e11a : void init_UART_SPI() { U0CTL |= SWRST; // disable the state machine e11a: d2 d3 70 00 bis.b #1, &0x0070 ;r3 As==01 ME2 &= ~UTXE0; //disable UART e11e: e2 c3 05 00 bic.b #2, &0x0005 ;r3 As==10 ME2 |= USPIE0; //enable SPI e122: d2 d3 05 00 bis.b #1, &0x0005 ;r3 As==01 U0CTL = CHAR | SYNC | MM | SWRST; e126: f2 40 17 00 mov.b #23, &0x0070 ;#0x0017 e12a: 70 00 U0TCTL = CKPH | STC | SSEL_3; e12c: f2 40 b2 ff mov.b #-78, &0x0071 ;#0xffb2 e130: 71 00 U0BR0 = 2; //divide by 5 = 1Mhz e132: e2 43 74 00 mov.b #2, &0x0074 ;r3 As==10 U0BR1 = 0; e136: c2 43 75 00 mov.b #0, &0x0075 ;r3 As==00 U0MCTL = 0; e13a: c2 43 73 00 mov.b #0, &0x0073 ;r3 As==00 U0CTL &= ~SWRST; // Initialize USART state machine e13e: d2 c3 70 00 bic.b #1, &0x0070 ;r3 As==01 } e142: 30 41 ret e144: 47 52 add.b r2, r7 e146: 58 00 .word 0x0058; ???? e148: 72 65 addc.b @r5+, r2 e14a: 73 65 .word 0x6573; ???? Illegal as 2-op instr e14c: 74 00 .word 0x0074; ???? e14e: 73 74 .word 0x7473; ???? Illegal as 2-op instr e150: 61 74 subc.b @r4, r1 e152: 75 73 subc.b #-1, r5 ;r3 As==11 e154: 00 47 br r7 e156: 4e 44 mov.b r4, r14 e158: 3a 25 jz $+630 ;abs 0xe3ce e15a: 73 20 jnz $+232 ;abs 0xe242 e15c: 52 53 inc.b r2 e15e: 53 49 .word 0x4953; ???? Illegal as 2-op instr e160: 3a 25 jz $+630 ;abs 0xe3d6 e162: 64 64 addc.b @r4, r4 e164: 42 6d addc.b r13, r2 e166: 20 4c br @r12 e168: 51 49 3a 25 mov.b 9530(r9),r1 ;0x253a(r9) e16c: 64 00 .word 0x0064; ???? e16e: 63 68 .word 0x6863; ???? Illegal as 2-op instr e170: 61 6e addc.b @r14, r1 e172: 00 1b .word 0x1b00; ???? e174: 5b 33 jn $-328 ;abs 0xe02c e176: 32 6d addc @r13+, r2 e178: 47 4e mov.b r14, r7 e17a: 44 3a jl $-886 ;abs 0xde04 e17c: 25 73 subc #2, r5 ;r3 As==10 e17e: 20 63 addc #2, r0 ;r3 As==10 e180: 68 61 addc.b @r1, r8 e182: 6e 20 jnz $+222 ;abs 0xe260 e184: 77 61 addc.b @r1+, r7 e186: 73 20 jnz $+232 ;abs 0xe26e e188: 25 64 addc @r4, r5 e18a: 20 6e addc @r14, r0 e18c: 6f 77 subc.b @r7, r15 e18e: 20 25 jz $+578 ;abs 0xe3d0 e190: 64 1b .word 0x1b64; ???? e192: 5b 33 jn $-328 ;abs 0xe04a e194: 30 6d addc @r13+, r0 e196: 00 47 br r7 e198: 4e 44 mov.b r4, r14 e19a: 3a 25 jz $+630 ;abs 0xe410 e19c: 73 20 jnz $+232 ;abs 0xe284 e19e: 63 68 .word 0x6863; ???? Illegal as 2-op instr e1a0: 61 6e addc.b @r14, r1 e1a2: 20 69 addc @r9, r0 e1a4: 73 20 jnz $+232 ;abs 0xe28c e1a6: 25 64 addc @r4, r5 e1a8: 00 72 subc r2, r0 e1aa: 61 74 subc.b @r4, r1 e1ac: 65 00 .word 0x0065; ???? e1ae: 47 4e mov.b r14, r7 e1b0: 44 3a jl $-886 ;abs 0xde3a e1b2: 25 73 subc #2, r5 ;r3 As==10 e1b4: 20 72 subc #4, r0 ;r2 As==10 e1b6: 61 74 subc.b @r4, r1 e1b8: 65 20 jnz $+204 ;abs 0xe284 e1ba: 69 73 subc.b #2, r9 ;r3 As==10 e1bc: 20 25 jz $+578 ;abs 0xe3fe e1be: 64 1b .word 0x1b64; ???? e1c0: 5b 33 jn $-328 ;abs 0xe078 e1c2: 30 6d addc @r13+, r0 e1c4: 00 47 br r7 e1c6: 4e 44 mov.b r4, r14 e1c8: 3a 25 jz $+630 ;abs 0xe43e e1ca: 73 20 jnz $+232 ;abs 0xe2b2 e1cc: 72 61 addc.b @r1+, r2 e1ce: 74 65 addc.b @r5+, r4 e1d0: 20 69 addc @r9, r0 e1d2: 73 20 jnz $+232 ;abs 0xe2ba e1d4: 6e 6f addc.b @r15, r14 e1d6: 77 20 jnz $+240 ;abs 0xe2c6 e1d8: 25 64 addc @r4, r5 e1da: 00 47 br r7 e1dc: 4e 44 mov.b r4, r14 e1de: 3a 47 mov @r7+, r10 e1e0: 52 58 20 50 add.b 20512(r8),r2 ;0x5020(r8) e1e4: 6f 6e addc.b @r14, r15 e1e6: 67 21 jnz $+720 ;abs 0xe4b6 ... 0000e1ea
: /** Main function. */ int main(void) { e1ea: 31 40 c0 02 mov #704, r1 ;#0x02c0 e1ee: 04 41 mov r1, r4 unsigned int rate=12,i=0; e1f0: 38 40 0c 00 mov #12, r8 ;#0x000c unsigned char loop, cnt=0, length, chan=P2_CHANNR; e1f4: 77 40 26 00 mov.b #38, r7 ;#0x0026 char rxbuf[64]; sys_init(); e1f8: b0 12 a2 e0 call #0xe0a2 init_UART_SPI(); e1fc: b0 12 1a e1 call #0xe11a memset(rxbuf, 0, 64); e200: 3e 40 40 00 mov #64, r14 ;#0x0040 e204: 0f 44 mov r4, r15 e206: cf 43 00 00 mov.b #0, 0(r15) ;r3 As==00, 0x0000(r15) e20a: 1f 53 inc r15 e20c: 1e 83 dec r14 e20e: fb 23 jnz $-8 ;abs 0xe206 P3OUT &= ~CSn; //power on reset, strobe CSn e210: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 delay(0x00FF); e214: 3f 40 ff 00 mov #255, r15 ;#0x00ff e218: b0 12 74 e0 call #0xe074 P3OUT |= CSn; e21c: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 delay(0xFFFF); e220: 3f 43 mov #-1, r15 ;r3 As==11 e222: b0 12 74 e0 call #0xe074 if(CCXX_SPI_RDREG(CCxxx0_CHANNR) == 0) //is this is not zero then the chip has already been programmed and we have rebooted. Don't reprogram chip as it will cut the link! e226: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e22a: b0 12 f6 e8 call #0xe8f6 e22e: 4f 93 tst.b r15 e230: 50 21 jnz $+674 ;abs 0xe4d2 { //values straight from RF_STUDIO CCXX_SPI_STROBE(CCxxx0_SRES); //reset chip e232: 7f 40 30 00 mov.b #48, r15 ;#0x0030 e236: b0 12 c0 e8 call #0xe8c0 CCXX_WRITE_SPI_RF_SETTINGS(rate); e23a: 3f 40 0c 00 mov #12, r15 ;#0x000c e23e: b0 12 18 e5 call #0xe518 CCXX_SPI_WRREG(CCxxx0_CHANNR, P2_CHANNR); // Channel number. e242: 7e 40 26 00 mov.b #38, r14 ;#0x0026 e246: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e24a: b0 12 52 e9 call #0xe952 else if(chan == 0x2D) rate = 2500; chan = CCXX_SPI_RDREG(CCxxx0_CHANNR); } CCXX_SPI_STROBE(CCxxx0_SCAL); //reset chip e24e: 7f 40 33 00 mov.b #51, r15 ;#0x0033 e252: b0 12 c0 e8 call #0xe8c0 do{ i = CCXX_SPI_RDREG(CCxxx0_MARCSTATE);//wait for IDLE e256: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e25a: b0 12 f6 e8 call #0xe8f6 e25e: 4a 4f mov.b r15, r10 e260: 8a 11 sxt r10 }while(i != 1); e262: 1a 93 cmp #1, r10 ;r3 As==01 e264: f8 23 jnz $-14 ;abs 0xe256 flags=0; e266: 82 43 0e 02 mov #0, &0x020e ;r3 As==00 P2IFG=0x00; e26a: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 P1IFG=0x00; e26e: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 P3OUT ^= LED_RED; e272: f2 e0 20 00 xor.b #32, &0x0019 ;#0x0020 e276: 19 00 delay(0xFF); //lil bit O delay e278: 3f 40 ff 00 mov #255, r15 ;#0x00ff e27c: b0 12 74 e0 call #0xe074 P3OUT ^= LED_RED; e280: f2 e0 20 00 xor.b #32, &0x0019 ;#0x0020 e284: 19 00 eint(); e286: 32 d2 eint RX_MODE(); e288: b0 12 ba e7 call #0xe7ba while (1) //main loop, never ends... { loop = 0; e28c: 49 43 clr.b r9 if((flags & GND_RDY) == GND_RDY) //The ground is talking to us! e28e: 92 b3 0e 02 bit #1, &0x020e ;r3 As==01 e292: 58 24 jz $+178 ;abs 0xe344 { dint(); e294: 32 c2 dint loop = 1; e296: 59 43 mov.b #1, r9 ;r3 As==01 memset(rxbuf, 0, 64); e298: 3e 40 40 00 mov #64, r14 ;#0x0040 e29c: 0f 44 mov r4, r15 e29e: cf 43 00 00 mov.b #0, 0(r15) ;r3 As==00, 0x0000(r15) e2a2: 1f 53 inc r15 e2a4: 1e 83 dec r14 e2a6: fb 23 jnz $-8 ;abs 0xe29e P3OUT |= LED_RED; e2a8: f2 d0 20 00 bis.b #32, &0x0019 ;#0x0020 e2ac: 19 00 length = RX_STRING(rxbuf, 60); e2ae: 7e 40 3c 00 mov.b #60, r14 ;#0x003c e2b2: 0f 44 mov r4, r15 e2b4: b0 12 e4 e7 call #0xe7e4 e2b8: 4b 4f mov.b r15, r11 P2IFG &= ~GDO0; e2ba: f2 f0 ef ff and.b #-17, &0x002b ;#0xffef e2be: 2b 00 RX_MODE(); e2c0: b0 12 ba e7 call #0xe7ba if((LQI & bit7) == bit7) //CRC ok! e2c4: c2 93 0c 02 tst.b &0x020c e2c8: 37 34 jge $+112 ;abs 0xe338 { P3OUT |= LED_GRN; e2ca: f2 d0 10 00 bis.b #16, &0x0019 ;#0x0010 e2ce: 19 00 if(!memcmp(CALLSIGN,rxbuf,3)) e2d0: 3d 40 03 00 mov #3, r13 ;#0x0003 e2d4: 0e 44 mov r4, r14 e2d6: 3f 40 44 e1 mov #-7868, r15 ;#0xe144 e2da: b0 12 d6 f2 call #0xf2d6 e2de: 0f 93 tst r15 e2e0: f4 20 jnz $+490 ;abs 0xe4ca { if(strstr( rxbuf, "reset" ) != NULL) e2e2: 3e 40 48 e1 mov #-7864, r14 ;#0xe148 e2e6: 0f 44 mov r4, r15 e2e8: b0 12 06 f3 call #0xf306 e2ec: 0f 93 tst r15 e2ee: e9 20 jnz $+468 ;abs 0xe4c2 { WDTCTL = WDTCNTCL|WDTPW; while(1); //wait for timeout } else if(strstr( rxbuf, "status" ) != NULL) e2f0: 3e 40 4e e1 mov #-7858, r14 ;#0xe14e e2f4: 0f 44 mov r4, r15 e2f6: b0 12 06 f3 call #0xf306 e2fa: 0f 93 tst r15 e2fc: 2c 24 jz $+90 ;abs 0xe356 { length = snprintf(rxbuf,63,"GND:%s RSSI:%ddBm LQI:%d",CALLSIGN, RSSI_DBM, LQI); e2fe: 5f 42 0c 02 mov.b &0x020c,r15 e302: 0f 12 push r15 e304: 5f 42 0a 02 mov.b &0x020a,r15 e308: 8f 11 sxt r15 e30a: 0f 12 push r15 e30c: 30 12 44 e1 push #-7868 ;#0xe144 e310: 30 12 55 e1 push #-7851 ;#0xe155 e314: 30 12 3f 00 push #63 ;#0x003f e318: 04 12 push r4 e31a: b0 12 0c ec call #0xec0c e31e: 4b 4f mov.b r15, r11 send_string(rxbuf,length+1); e320: 5b 53 inc.b r11 e322: 4e 4b mov.b r11, r14 e324: 0f 44 mov r4, r15 e326: b0 12 60 ea call #0xea60 P1IFG &= ~ARB_RX; e32a: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 e32e: 31 50 0c 00 add #12, r1 ;#0x000c else { send_string(rxbuf, length+1); //send byte P1IFG &= ~ARB_RX; } P3OUT &= ~LED_GRN; e332: f2 f0 ef ff and.b #-17, &0x0019 ;#0xffef e336: 19 00 } flags &= ~GND_RDY; e338: 92 c3 0e 02 bic #1, &0x020e ;r3 As==01 P3OUT &= ~LED_RED; e33c: f2 f0 df ff and.b #-33, &0x0019 ;#0xffdf e340: 19 00 eint(); e342: 32 d2 eint } if((flags & ARB_RDY) == ARB_RDY) //The Arbiter is Talking to Us! e344: a2 b3 0e 02 bit #2, &0x020e ;r3 As==10 e348: 01 24 jz $+4 ;abs 0xe34c { loop = 1; e34a: 59 43 mov.b #1, r9 ;r3 As==01 } if(loop == 0) e34c: 49 93 tst.b r9 e34e: 9e 23 jnz $-194 ;abs 0xe28c LPM3; e350: 32 d0 d0 00 bis #208, r2 ;#0x00d0 e354: 9b 3f jmp $-200 ;abs 0xe28c { length = snprintf(rxbuf,63,"GND:%s RSSI:%ddBm LQI:%d",CALLSIGN, RSSI_DBM, LQI); send_string(rxbuf,length+1); P1IFG &= ~ARB_RX; } else if(strstr( rxbuf, "chan" ) != NULL) //interval is in the string! e356: 3e 40 6e e1 mov #-7826, r14 ;#0xe16e e35a: 0f 44 mov r4, r15 e35c: b0 12 06 f3 call #0xf306 e360: 0f 93 tst r15 e362: 59 24 jz $+180 ;abs 0xe416 { i = atoi(strchr(rxbuf, '=' )+1); //The new interval should follow the equals sign e364: 3e 40 3d 00 mov #61, r14 ;#0x003d e368: 0f 44 mov r4, r15 e36a: b0 12 98 f2 call #0xf298 e36e: 1f 53 inc r15 e370: b0 12 38 eb call #0xeb38 e374: 0a 4f mov r15, r10 if(i > 0) e376: 0f 93 tst r15 e378: 34 24 jz $+106 ;abs 0xe3e2 { //length = sprintf(interchip,"GND:%s\e[32m chan is now %d\e[30m",CALLSIGN,i); length = snprintf(rxbuf,63,"\e[32mGND:%s chan was %d now %d\e[30m",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_CHANNR),i); e37a: 0f 12 push r15 e37c: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e380: b0 12 f6 e8 call #0xe8f6 e384: 7f f3 and.b #-1, r15 ;r3 As==11 e386: 0f 12 push r15 e388: 30 12 44 e1 push #-7868 ;#0xe144 e38c: 30 12 73 e1 push #-7821 ;#0xe173 e390: 30 12 3f 00 push #63 ;#0x003f e394: 04 12 push r4 e396: b0 12 0c ec call #0xec0c e39a: 4b 4f mov.b r15, r11 chan=i; e39c: 47 4a mov.b r10, r7 send_string(rxbuf,length+1); e39e: 5b 53 inc.b r11 e3a0: 4e 4b mov.b r11, r14 e3a2: 0f 44 mov r4, r15 e3a4: b0 12 60 ea call #0xea60 P1IFG &= ~ARB_RX; e3a8: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 CCXX_SPI_STROBE(CCxxx0_SRES); //reset chip e3ac: 7f 40 30 00 mov.b #48, r15 ;#0x0030 e3b0: b0 12 c0 e8 call #0xe8c0 //delay(0xFFF); CCXX_WRITE_SPI_RF_SETTINGS(rate); e3b4: 0f 48 mov r8, r15 e3b6: b0 12 18 e5 call #0xe518 CCXX_SPI_WRREG(CCxxx0_CHANNR, chan); // Channel number. e3ba: 4e 4a mov.b r10, r14 e3bc: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e3c0: b0 12 52 e9 call #0xe952 CCXX_SPI_STROBE(CCxxx0_SIDLE); //reset chip e3c4: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e3c8: b0 12 c0 e8 call #0xe8c0 do{ e3cc: 31 50 0c 00 add #12, r1 ;#0x000c i = CCXX_SPI_RDREG(CCxxx0_MARCSTATE);//wait for IDLE e3d0: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e3d4: b0 12 f6 e8 call #0xe8f6 e3d8: 4a 4f mov.b r15, r10 e3da: 8a 11 sxt r10 }while(i != 1); e3dc: 1a 93 cmp #1, r10 ;r3 As==01 e3de: f8 23 jnz $-14 ;abs 0xe3d0 e3e0: a8 3f jmp $-174 ;abs 0xe332 } else { //length = sprintf(interchip,"GND:%s\e[32m chan is %d\e[30m",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_CHANNR)); length = snprintf(rxbuf,63,"GND:%s chan is %d",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_CHANNR)); e3e2: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e3e6: b0 12 f6 e8 call #0xe8f6 e3ea: 7f f3 and.b #-1, r15 ;r3 As==11 e3ec: 0f 12 push r15 e3ee: 30 12 44 e1 push #-7868 ;#0xe144 e3f2: 30 12 97 e1 push #-7785 ;#0xe197 e3f6: 30 12 3f 00 push #63 ;#0x003f e3fa: 04 12 push r4 e3fc: b0 12 0c ec call #0xec0c e400: 4b 4f mov.b r15, r11 } else { //memset(interchip, 0, 64); length = snprintf(rxbuf,63,"GND:%s rate is %d\e[30m",CALLSIGN,rate); send_string(rxbuf,length+1); e402: 5b 53 inc.b r11 e404: 4e 4b mov.b r11, r14 e406: 0f 44 mov r4, r15 e408: b0 12 60 ea call #0xea60 P1IFG &= ~ARB_RX; e40c: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 e410: 31 50 0a 00 add #10, r1 ;#0x000a e414: 8e 3f jmp $-226 ;abs 0xe332 length = snprintf(rxbuf,63,"GND:%s chan is %d",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_CHANNR)); send_string(rxbuf,length+1); P1IFG &= ~ARB_RX; } } else if(strstr( rxbuf, "rate" ) != NULL) //interval is in the string! e416: 3e 40 a9 e1 mov #-7767, r14 ;#0xe1a9 e41a: 0f 44 mov r4, r15 e41c: b0 12 06 f3 call #0xf306 e420: 0f 93 tst r15 e422: 46 24 jz $+142 ;abs 0xe4b0 { i = atoi(strchr(rxbuf, '=' )+1); //The new interval should follow the equals sign e424: 3e 40 3d 00 mov #61, r14 ;#0x003d e428: 0f 44 mov r4, r15 e42a: b0 12 98 f2 call #0xf298 e42e: 1f 53 inc r15 e430: b0 12 38 eb call #0xeb38 e434: 0a 4f mov r15, r10 if(i == 12 || i == 384 || i == 2500) e436: 3f 90 0c 00 cmp #12, r15 ;#0x000c e43a: 0c 24 jz $+26 ;abs 0xe454 e43c: 3f 90 80 01 cmp #384, r15 ;#0x0180 e440: 09 24 jz $+20 ;abs 0xe454 e442: 3f 90 c4 09 cmp #2500, r15 ;#0x09c4 e446: 06 24 jz $+14 ;abs 0xe454 }while(i != 1); } else { //memset(interchip, 0, 64); length = snprintf(rxbuf,63,"GND:%s rate is %d\e[30m",CALLSIGN,rate); e448: 08 12 push r8 e44a: 30 12 44 e1 push #-7868 ;#0xe144 e44e: 30 12 ae e1 push #-7762 ;#0xe1ae e452: d1 3f jmp $-92 ;abs 0xe3f6 else if(strstr( rxbuf, "rate" ) != NULL) //interval is in the string! { i = atoi(strchr(rxbuf, '=' )+1); //The new interval should follow the equals sign if(i == 12 || i == 384 || i == 2500) { rate=i; e454: 08 4a mov r10, r8 //length = sprintf(interchip,"\e[32mGND:%s rate is now %d\e[30m",CALLSIGN,i); length = snprintf(rxbuf,63,"GND:%s rate is now %d",CALLSIGN,rate); e456: 0a 12 push r10 e458: 30 12 44 e1 push #-7868 ;#0xe144 e45c: 30 12 c5 e1 push #-7739 ;#0xe1c5 e460: 30 12 3f 00 push #63 ;#0x003f e464: 04 12 push r4 e466: b0 12 0c ec call #0xec0c e46a: 4b 4f mov.b r15, r11 send_string(rxbuf,length+1); e46c: 5b 53 inc.b r11 e46e: 4e 4b mov.b r11, r14 e470: 0f 44 mov r4, r15 e472: b0 12 60 ea call #0xea60 P1IFG &= ~ARB_RX; e476: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 CCXX_SPI_STROBE(CCxxx0_SRES); //reset chip e47a: 7f 40 30 00 mov.b #48, r15 ;#0x0030 e47e: b0 12 c0 e8 call #0xe8c0 //delay(0xFFF); CCXX_WRITE_SPI_RF_SETTINGS(i); e482: 0f 4a mov r10, r15 e484: b0 12 18 e5 call #0xe518 CCXX_SPI_WRREG(CCxxx0_CHANNR, chan); // Channel number. e488: 4e 47 mov.b r7, r14 e48a: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e48e: b0 12 52 e9 call #0xe952 CCXX_SPI_STROBE(CCxxx0_SIDLE); //flush the buffer, all bytes sent e492: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e496: b0 12 c0 e8 call #0xe8c0 do{ e49a: 31 50 0a 00 add #10, r1 ;#0x000a i = CCXX_SPI_RDREG(CCxxx0_MARCSTATE);//wait for IDLE e49e: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e4a2: b0 12 f6 e8 call #0xe8f6 e4a6: 4a 4f mov.b r15, r10 e4a8: 8a 11 sxt r10 }while(i != 1); e4aa: 1a 93 cmp #1, r10 ;r3 As==01 e4ac: f8 23 jnz $-14 ;abs 0xe49e e4ae: 41 3f jmp $-380 ;abs 0xe332 } } else { send_string("GND:GRX Pong!", 15); //send byte e4b0: 7e 40 0f 00 mov.b #15, r14 ;#0x000f e4b4: 3f 40 db e1 mov #-7717, r15 ;#0xe1db e4b8: b0 12 60 ea call #0xea60 } } else { send_string(rxbuf, length+1); //send byte P1IFG &= ~ARB_RX; e4bc: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 e4c0: 38 3f jmp $-398 ;abs 0xe332 if(!memcmp(CALLSIGN,rxbuf,3)) { if(strstr( rxbuf, "reset" ) != NULL) { WDTCTL = WDTCNTCL|WDTPW; e4c2: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e4c6: 20 01 while(1); //wait for timeout e4c8: ff 3f jmp $+0 ;abs 0xe4c8 P1IFG &= ~ARB_RX; } } else { send_string(rxbuf, length+1); //send byte e4ca: 5b 53 inc.b r11 e4cc: 4e 4b mov.b r11, r14 e4ce: 0f 44 mov r4, r15 e4d0: f3 3f jmp $-24 ;abs 0xe4b8 CCXX_SPI_WRREG(CCxxx0_CHANNR, P2_CHANNR); // Channel number. } else { chan = CCXX_SPI_RDREG(CCxxx0_MDMCFG4); e4d2: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e4d6: b0 12 f6 e8 call #0xe8f6 if(chan == 0xF5) e4da: 7f 90 f5 ff cmp.b #-11, r15 ;#0xfff5 e4de: 09 24 jz $+20 ;abs 0xe4f2 rate = 12; else if(chan == 0xF6) e4e0: 7f 90 f6 ff cmp.b #-10, r15 ;#0xfff6 e4e4: 12 24 jz $+38 ;abs 0xe50a rate = 24; else if(chan == 0xCA) e4e6: 7f 90 ca ff cmp.b #-54, r15 ;#0xffca e4ea: 0c 24 jz $+26 ;abs 0xe504 rate = 384; else if(chan == 0x2D) e4ec: 7f 90 2d 00 cmp.b #45, r15 ;#0x002d e4f0: 06 24 jz $+14 ;abs 0xe4fe rate = 2500; chan = CCXX_SPI_RDREG(CCxxx0_CHANNR); e4f2: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e4f6: b0 12 f6 e8 call #0xe8f6 e4fa: 47 4f mov.b r15, r7 e4fc: a8 3e jmp $-686 ;abs 0xe24e else if(chan == 0xF6) rate = 24; else if(chan == 0xCA) rate = 384; else if(chan == 0x2D) rate = 2500; e4fe: 38 40 c4 09 mov #2500, r8 ;#0x09c4 e502: f7 3f jmp $-16 ;abs 0xe4f2 if(chan == 0xF5) rate = 12; else if(chan == 0xF6) rate = 24; else if(chan == 0xCA) rate = 384; e504: 38 40 80 01 mov #384, r8 ;#0x0180 e508: f4 3f jmp $-22 ;abs 0xe4f2 { chan = CCXX_SPI_RDREG(CCxxx0_MDMCFG4); if(chan == 0xF5) rate = 12; else if(chan == 0xF6) rate = 24; e50a: 38 40 18 00 mov #24, r8 ;#0x0018 e50e: f1 3f jmp $-28 ;abs 0xe4f2 loop = 1; } if(loop == 0) LPM3; } } e510: 31 50 40 00 add #64, r1 ;#0x0040 e514: 30 40 ae f3 br #0xf3ae 0000e518 : void CCXX_WRITE_SPI_RF_SETTINGS(int datarate) { e518: 0b 12 push r11 e51a: 0b 4f mov r15, r11 // Write register settings CCXX_SPI_WRREG(CCxxx0_IOCFG0, P2_IOCFG0); // GDO0 output pin config. e51c: 7e 40 06 00 mov.b #6, r14 ;#0x0006 e520: 6f 43 mov.b #2, r15 ;r3 As==10 e522: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_PKTLEN, P2_PKTLEN); // Packet length. e526: 7e 43 mov.b #-1, r14 ;r3 As==11 e528: 7f 40 06 00 mov.b #6, r15 ;#0x0006 e52c: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_PATABLE, P2_PATABLE); // GDO0 output pin config. e530: 7e 40 c3 ff mov.b #-61, r14 ;#0xffc3 e534: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e538: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_PKTCTRL0, P2_PKTCTRL0); // Packet automation control. e53c: 7e 40 05 00 mov.b #5, r14 ;#0x0005 e540: 7f 42 mov.b #8, r15 ;r2 As==11 e542: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_ADDR, P2_ADDR); // Device address. e546: 5e 43 mov.b #1, r14 ;r3 As==01 e548: 7f 40 09 00 mov.b #9, r15 ;#0x0009 e54c: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FSCTRL0, P2_FSCTRL0); // Freq synthesizer control. e550: 4e 43 clr.b r14 e552: 7f 40 0c 00 mov.b #12, r15 ;#0x000c e556: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FREQ2, P2_FREQ2); // Freq control word, high byte e55a: 7e 40 10 00 mov.b #16, r14 ;#0x0010 e55e: 7f 40 0d 00 mov.b #13, r15 ;#0x000d e562: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FREQ1, P2_FREQ1); // Freq control word, mid byte. e566: 7e 40 27 00 mov.b #39, r14 ;#0x0027 e56a: 7f 40 0e 00 mov.b #14, r15 ;#0x000e e56e: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FREQ0, P2_FREQ0); // Freq control word, low byte. e572: 7e 40 62 00 mov.b #98, r14 ;#0x0062 e576: 7f 40 0f 00 mov.b #15, r15 ;#0x000f e57a: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG2, P2_MDMCFG2); // Modem configuration. e57e: 7e 40 13 00 mov.b #19, r14 ;#0x0013 e582: 7f 40 12 00 mov.b #18, r15 ;#0x0012 e586: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG1, P2_MDMCFG1); // Modem configuration. e58a: 7e 40 22 00 mov.b #34, r14 ;#0x0022 e58e: 7f 40 13 00 mov.b #19, r15 ;#0x0013 e592: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG0, P2_MDMCFG0); // Modem configuration. e596: 7e 40 f8 ff mov.b #-8, r14 ;#0xfff8 e59a: 7f 40 14 00 mov.b #20, r15 ;#0x0014 e59e: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MCSM1 , P2_MCSM1 ); //MainRadio Cntrl State Machine e5a2: 7e 40 3f 00 mov.b #63, r14 ;#0x003f e5a6: 7f 40 17 00 mov.b #23, r15 ;#0x0017 e5aa: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MCSM0 , P2_MCSM0 ); //MainRadio Cntrl State Machine e5ae: 7e 40 18 00 mov.b #24, r14 ;#0x0018 e5b2: 7f 40 18 00 mov.b #24, r15 ;#0x0018 e5b6: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FREND0, P2_FREND0); // Front end RX configuration. e5ba: 7e 40 10 00 mov.b #16, r14 ;#0x0010 e5be: 7f 40 22 00 mov.b #34, r15 ;#0x0022 e5c2: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FSCAL2, P2_FSCAL2); // Frequency synthesizer cal. e5c6: 7e 40 2a 00 mov.b #42, r14 ;#0x002a e5ca: 7f 40 24 00 mov.b #36, r15 ;#0x0024 e5ce: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FSCAL1, P2_FSCAL1); // Frequency synthesizer cal. e5d2: 4e 43 clr.b r14 e5d4: 7f 40 25 00 mov.b #37, r15 ;#0x0025 e5d8: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FSCAL0, P2_FSCAL0); // Frequency synthesizer cal. e5dc: 7e 40 1f 00 mov.b #31, r14 ;#0x001f e5e0: 7f 40 26 00 mov.b #38, r15 ;#0x0026 e5e4: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FSTEST, P2_FSTEST); // Frequency synthesizer cal. e5e8: 7e 40 59 00 mov.b #89, r14 ;#0x0059 e5ec: 7f 40 29 00 mov.b #41, r15 ;#0x0029 e5f0: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_TEST0, P2_TEST0); // Various test settings. e5f4: 7e 40 0b 00 mov.b #11, r14 ;#0x000b e5f8: 7f 40 2e 00 mov.b #46, r15 ;#0x002e e5fc: b0 12 52 e9 call #0xe952 if(datarate == 12) e600: 3b 90 0c 00 cmp #12, r11 ;#0x000c e604: ab 24 jz $+344 ;abs 0xe75c CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_1200); // Frequency synthesizer cal. CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_1200); // Various test settings. } else if(datarate == 384) e606: 3b 90 80 01 cmp #384, r11 ;#0x0180 e60a: 57 24 jz $+176 ;abs 0xe6ba CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_38k4); // Frequency synthesizer cal. CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_38k4); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_38k4); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_38k4); // Various test settings. } else if(datarate == 2500) e60c: 3b 90 c4 09 cmp #2500, r11 ;#0x09c4 e610: d2 20 jnz $+422 ;abs 0xe7b6 { CCXX_SPI_WRREG(CCxxx0_FSCTRL1, FSCTRL1_250k); // Freq synthesizer control. e612: 7e 40 0c 00 mov.b #12, r14 ;#0x000c e616: 7f 40 0b 00 mov.b #11, r15 ;#0x000b e61a: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG4, MDMCFG4_250k); // Modem configuration. e61e: 7e 40 2d 00 mov.b #45, r14 ;#0x002d e622: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e626: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG3, MDMCFG3_250k); // Modem configuration. e62a: 7e 40 3b 00 mov.b #59, r14 ;#0x003b e62e: 7f 40 11 00 mov.b #17, r15 ;#0x0011 e632: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_DEVIATN, DEVIATN_250k); // Modem dev (when FSK mod en e636: 7e 40 62 00 mov.b #98, r14 ;#0x0062 e63a: 7f 40 15 00 mov.b #21, r15 ;#0x0015 e63e: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FREND1, FREND1_250k); // Front end RX configuration. e642: 7e 40 b6 ff mov.b #-74, r14 ;#0xffb6 e646: 7f 40 21 00 mov.b #33, r15 ;#0x0021 e64a: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FOCCFG, FOCCFG_250k); // Freq offset compensation e64e: 7e 40 1d 00 mov.b #29, r14 ;#0x001d e652: 7f 40 19 00 mov.b #25, r15 ;#0x0019 e656: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_BSCFG, BSCFG_250k); // bit sync config e65a: 7e 40 1c 00 mov.b #28, r14 ;#0x001c e65e: 7f 40 1a 00 mov.b #26, r15 ;#0x001a e662: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_AGCCTRL2, AGCCTRL2_250k); // AGC control e666: 7e 40 c7 ff mov.b #-57, r14 ;#0xffc7 e66a: 7f 40 1b 00 mov.b #27, r15 ;#0x001b e66e: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_AGCCTRL1, AGCCTRL1_250k); // AGC control e672: 4e 43 clr.b r14 e674: 7f 40 1c 00 mov.b #28, r15 ;#0x001c e678: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_AGCCTRL0, AGCCTRL0_250k); // AGC control e67c: 7e 40 b0 ff mov.b #-80, r14 ;#0xffb0 e680: 7f 40 1d 00 mov.b #29, r15 ;#0x001d e684: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_250k); // Frequency synthesizer cal. e688: 7e 40 ea ff mov.b #-22, r14 ;#0xffea e68c: 7f 40 23 00 mov.b #35, r15 ;#0x0023 e690: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_250k); // Various test settings. e694: 7e 40 88 ff mov.b #-120, r14 ;#0xff88 e698: 7f 40 2c 00 mov.b #44, r15 ;#0x002c e69c: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_250k); // Various test settings. e6a0: 7e 40 31 00 mov.b #49, r14 ;#0x0031 e6a4: 7f 40 2d 00 mov.b #45, r15 ;#0x002d e6a8: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_250k); // Various test settings. e6ac: 7e 40 07 00 mov.b #7, r14 ;#0x0007 e6b0: 7f 40 03 00 mov.b #3, r15 ;#0x0003 e6b4: b0 12 52 e9 call #0xe952 e6b8: 7e 3c jmp $+254 ;abs 0xe7b6 CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_1200); // Various test settings. } else if(datarate == 384) { CCXX_SPI_WRREG(CCxxx0_FSCTRL1, FSCTRL1_38k4); // Freq synthesizer control. e6ba: 7e 40 06 00 mov.b #6, r14 ;#0x0006 e6be: 7f 40 0b 00 mov.b #11, r15 ;#0x000b e6c2: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG4, MDMCFG4_38k4); // Modem configuration. e6c6: 7e 40 ca ff mov.b #-54, r14 ;#0xffca e6ca: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e6ce: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG3, MDMCFG3_38k4); // Modem configuration. e6d2: 7e 40 83 ff mov.b #-125, r14 ;#0xff83 e6d6: 7f 40 11 00 mov.b #17, r15 ;#0x0011 e6da: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_DEVIATN, DEVIATN_38k4); // Modem dev (when FSK mod en e6de: 7e 40 34 00 mov.b #52, r14 ;#0x0034 e6e2: 7f 40 15 00 mov.b #21, r15 ;#0x0015 e6e6: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FREND1, FREND1_38k4); // Front end RX configuration. e6ea: 7e 40 56 00 mov.b #86, r14 ;#0x0056 e6ee: 7f 40 21 00 mov.b #33, r15 ;#0x0021 e6f2: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FOCCFG, FOCCFG_38k4); // Freq offset compensation e6f6: 7e 40 16 00 mov.b #22, r14 ;#0x0016 e6fa: 7f 40 19 00 mov.b #25, r15 ;#0x0019 e6fe: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_BSCFG, BSCFG_38k4); // bit sync config e702: 7e 40 6c 00 mov.b #108, r14 ;#0x006c e706: 7f 40 1a 00 mov.b #26, r15 ;#0x001a e70a: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_AGCCTRL2, AGCCTRL2_38k4); // AGC control e70e: 7e 40 43 00 mov.b #67, r14 ;#0x0043 e712: 7f 40 1b 00 mov.b #27, r15 ;#0x001b e716: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_AGCCTRL1, AGCCTRL1_38k4); // AGC control e71a: 7e 40 40 00 mov.b #64, r14 ;#0x0040 e71e: 7f 40 1c 00 mov.b #28, r15 ;#0x001c e722: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_AGCCTRL0, AGCCTRL0_38k4); // AGC control e726: 7e 40 91 ff mov.b #-111, r14 ;#0xff91 e72a: 7f 40 1d 00 mov.b #29, r15 ;#0x001d e72e: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_38k4); // Frequency synthesizer cal. e732: 7e 40 e9 ff mov.b #-23, r14 ;#0xffe9 e736: 7f 40 23 00 mov.b #35, r15 ;#0x0023 e73a: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_38k4); // Various test settings. e73e: 7e 40 81 ff mov.b #-127, r14 ;#0xff81 e742: 7f 40 2c 00 mov.b #44, r15 ;#0x002c e746: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_38k4); // Various test settings. e74a: 7e 40 35 00 mov.b #53, r14 ;#0x0035 e74e: 7f 40 2d 00 mov.b #45, r15 ;#0x002d e752: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_38k4); // Various test settings. e756: 7e 40 47 00 mov.b #71, r14 ;#0x0047 e75a: aa 3f jmp $-170 ;abs 0xe6b0 CCXX_SPI_WRREG(CCxxx0_FSTEST, P2_FSTEST); // Frequency synthesizer cal. CCXX_SPI_WRREG(CCxxx0_TEST0, P2_TEST0); // Various test settings. if(datarate == 12) { CCXX_SPI_WRREG(CCxxx0_FSCTRL1, FSCTRL1_1200); // Freq synthesizer control. e75c: 7e 40 06 00 mov.b #6, r14 ;#0x0006 e760: 7f 40 0b 00 mov.b #11, r15 ;#0x000b e764: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG4, MDMCFG4_1200); // Modem configuration. e768: 7e 40 f5 ff mov.b #-11, r14 ;#0xfff5 e76c: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e770: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_MDMCFG3, MDMCFG3_1200); // Modem configuration. e774: 7e 40 83 ff mov.b #-125, r14 ;#0xff83 e778: 7f 40 11 00 mov.b #17, r15 ;#0x0011 e77c: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_DEVIATN, DEVIATN_1200); // Modem dev (when FSK mod en e780: 7e 40 15 00 mov.b #21, r14 ;#0x0015 e784: 7f 40 15 00 mov.b #21, r15 ;#0x0015 e788: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FREND1, FREND1_1200); // Front end RX configuration. e78c: 7e 40 56 00 mov.b #86, r14 ;#0x0056 e790: 7f 40 21 00 mov.b #33, r15 ;#0x0021 e794: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_FOCCFG, FOCCFG_1200); // Freq offset compensation e798: 7e 40 16 00 mov.b #22, r14 ;#0x0016 e79c: 7f 40 19 00 mov.b #25, r15 ;#0x0019 e7a0: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_BSCFG, BSCFG_1200); // bit sync config e7a4: 7e 40 6c 00 mov.b #108, r14 ;#0x006c e7a8: 7f 40 1a 00 mov.b #26, r15 ;#0x001a e7ac: b0 12 52 e9 call #0xe952 CCXX_SPI_WRREG(CCxxx0_AGCCTRL2, AGCCTRL2_1200); // AGC control e7b0: 7e 40 03 00 mov.b #3, r14 ;#0x0003 CCXX_SPI_WRREG(CCxxx0_AGCCTRL1, AGCCTRL1_1200); // AGC control CCXX_SPI_WRREG(CCxxx0_AGCCTRL0, AGCCTRL0_1200); // AGC control CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_1200); // Frequency synthesizer cal. CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_1200); // Various test settings. e7b4: ae 3f jmp $-162 ;abs 0xe712 CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_250k); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_250k); // Various test settings. } } e7b6: 3b 41 pop r11 e7b8: 30 41 ret 0000e7ba : Interrupt driven! yay! */ void RX_MODE() { CCXX_SPI_STROBE(CCxxx0_SIDLE); e7ba: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e7be: b0 12 c0 e8 call #0xe8c0 while(status!=15) //(15)31 for return to TX on complete, see MCSM1 e7c2: f2 90 0f 00 cmp.b #15, &0x0210 ;#0x000f e7c6: 10 02 e7c8: 08 24 jz $+18 ;abs 0xe7da CCXX_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... e7ca: 7f 40 3d 00 mov.b #61, r15 ;#0x003d e7ce: b0 12 c0 e8 call #0xe8c0 e7d2: f2 90 0f 00 cmp.b #15, &0x0210 ;#0x000f e7d6: 10 02 e7d8: f8 23 jnz $-14 ;abs 0xe7ca CCXX_SPI_STROBE(CCxxx0_SRX);//Recieve Mode e7da: 7f 40 34 00 mov.b #52, r15 ;#0x0034 e7de: b0 12 c0 e8 call #0xe8c0 } e7e2: 30 41 ret 0000e7e4 : char RX_STRING(unsigned char *rxbuf, unsigned char length) { e7e4: 0b 12 push r11 e7e6: 0a 12 push r10 e7e8: 09 12 push r9 e7ea: 08 12 push r8 e7ec: 07 12 push r7 e7ee: 06 12 push r6 e7f0: 09 4f mov r15, r9 e7f2: 47 4e mov.b r14, r7 unsigned char i, real_length=23, pkt_length, tmp; RSSI = 0; e7f4: c2 43 0b 02 mov.b #0, &0x020b ;r3 As==00 LQI = 0; e7f8: c2 43 0c 02 mov.b #0, &0x020c ;r3 As==00 pkt_length = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//length of the buffer e7fc: 7f 40 3f 00 mov.b #63, r15 ;#0x003f e800: b0 12 f6 e8 call #0xe8f6 e804: 48 4f mov.b r15, r8 real_length = CCXX_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet e806: 7f 40 3b 00 mov.b #59, r15 ;#0x003b e80a: b0 12 f6 e8 call #0xe8f6 e80e: 46 4f mov.b r15, r6 for(i=0; i < length && i < pkt_length; i++) e810: 4a 43 clr.b r10 e812: 4a 97 cmp.b r7, r10 e814: 02 2c jc $+6 ;abs 0xe81a e816: 58 93 cmp.b #1, r8 ;r3 As==01 e818: 2f 2c jc $+96 ;abs 0xe878 { rxbuf[i] = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the byte } rxbuf[i] = '\0';//set the NULL terminator e81a: 4f 4a mov.b r10, r15 e81c: 09 5f add r15, r9 e81e: c9 43 00 00 mov.b #0, 0(r9) ;r3 As==00, 0x0000(r9) RSSI = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the ESSI e822: 7f 40 3f 00 mov.b #63, r15 ;#0x003f e826: b0 12 f6 e8 call #0xe8f6 e82a: c2 4f 0b 02 mov.b r15, &0x020b LQI = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the CRC e82e: 7f 40 3f 00 mov.b #63, r15 ;#0x003f e832: b0 12 f6 e8 call #0xe8f6 e836: c2 4f 0c 02 mov.b r15, &0x020c PKTSTATUS = CCXX_SPI_RDREG(CCxxx0_PKTSTATUS); e83a: 7f 40 38 00 mov.b #56, r15 ;#0x0038 e83e: b0 12 f6 e8 call #0xe8f6 e842: c2 4f 0d 02 mov.b r15, &0x020d if(real_length != (pkt_length + 2)) //packets lengths dont match, LQI mis-reported e846: 4e 46 mov.b r6, r14 e848: 4f 48 mov.b r8, r15 e84a: 2f 53 incd r15 e84c: 0e 9f cmp r15, r14 e84e: 03 24 jz $+8 ;abs 0xe856 LQI &= ~bit7; //force it to be INVALID! e850: f2 f0 7f 00 and.b #127, &0x020c ;#0x007f e854: 0c 02 if (RSSI >= 128) e856: 5f 42 0b 02 mov.b &0x020b,r15 e85a: 7f 90 80 00 cmp.b #128, r15 ;#0x0080 e85e: 09 28 jnc $+20 ;abs 0xe872 RSSI_DBM = (int)((int )(RSSI - 256) / 2) - 74; e860: 4e 4f mov.b r15, r14 e862: 0f 4e mov r14, r15 e864: 3f 50 00 ff add #-256, r15 ;#0xff00 e868: 02 30 jn $+6 ;abs 0xe86e e86a: 0f 11 rra r15 e86c: 14 3c jmp $+42 ;abs 0xe896 e86e: 1f 53 inc r15 e870: fc 3f jmp $-6 ;abs 0xe86a else RSSI_DBM = (RSSI / 2) - 74; e872: 12 c3 clrc e874: 4f 10 rrc.b r15 e876: 0f 3c jmp $+32 ;abs 0xe896 pkt_length = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//length of the buffer real_length = CCXX_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) { rxbuf[i] = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//get the byte e878: 4f 4a mov.b r10, r15 e87a: 0b 49 mov r9, r11 e87c: 0b 5f add r15, r11 e87e: 7f 40 3f 00 mov.b #63, r15 ;#0x003f e882: b0 12 f6 e8 call #0xe8f6 e886: cb 4f 00 00 mov.b r15, 0(r11) ;0x0000(r11) RSSI = 0; LQI = 0; pkt_length = CCXX_SPI_RDREG(CCxxx0_RXFIFO);//length of the buffer real_length = CCXX_SPI_RDREG(CCxxx0_RXBYTES);//length of the packet for(i=0; i < length && i < pkt_length; i++) e88a: 5a 53 inc.b r10 e88c: 4a 97 cmp.b r7, r10 e88e: c5 2f jc $-116 ;abs 0xe81a e890: 4a 98 cmp.b r8, r10 e892: f2 2b jnc $-26 ;abs 0xe878 e894: c2 3f jmp $-122 ;abs 0xe81a e896: 7f 50 b6 ff add.b #-74, r15 ;#0xffb6 e89a: c2 4f 0a 02 mov.b r15, &0x020a RSSI_DBM = (int)((int )(RSSI - 256) / 2) - 74; else RSSI_DBM = (RSSI / 2) - 74; CCXX_SPI_STROBE(CCxxx0_SFRX); //flush the buffer e89e: 7f 40 3a 00 mov.b #58, r15 ;#0x003a e8a2: b0 12 c0 e8 call #0xe8c0 CCXX_SPI_STROBE(CCxxx0_SIDLE); //return to IDLE state e8a6: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e8aa: b0 12 c0 e8 call #0xe8c0 return i; //i = real length e8ae: 4f 4a mov.b r10, r15 e8b0: 8f 11 sxt r15 } e8b2: 36 41 pop r6 e8b4: 37 41 pop r7 e8b6: 38 41 pop r8 e8b8: 39 41 pop r9 e8ba: 3a 41 pop r10 e8bc: 3b 41 pop r11 e8be: 30 41 ret 0000e8c0 : #include "hardware.h" /** Strobe a command to the CCXX */ void CCXX_SPI_STROBE(char reg) { e8c0: 4e 4f mov.b r15, r14 status=0; e8c2: c2 43 10 02 mov.b #0, &0x0210 ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip e8c6: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e8ca: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 e8ce: fd 23 jnz $-4 ;abs 0xe8ca P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e8d0: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e e8d4: 1b 00 IFG2 &= ~URXIFG0; e8d6: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e8da: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); e8de: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e8e2: fd 27 jz $-4 ;abs 0xe8de status = U0RXBUF; e8e4: d2 42 76 00 mov.b &0x0076,&0x0210 e8e8: 10 02 P3OUT |= CSn; //pull CSn high, we're done with the transfer e8ea: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e8ee: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 e8f2: 1b 00 } e8f4: 30 41 ret 0000e8f6 : /** Read a register from the CCXX */ char CCXX_SPI_RDREG(char reg) { e8f6: 4e 4f mov.b r15, r14 char rx=0; if(reg >= 0x30) e8f8: 7f 90 30 00 cmp.b #48, r15 ;#0x0030 e8fc: 1e 38 jl $+62 ;abs 0xe93a reg |= 0xC0; e8fe: 7e d0 c0 ff bis.b #-64, r14 ;#0xffc0 else reg |= 0x80; status=0; e902: c2 43 10 02 mov.b #0, &0x0210 ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip e906: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e90a: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 e90e: fd 23 jnz $-4 ;abs 0xe90a P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e910: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e e914: 1b 00 IFG2 &= ~URXIFG0; e916: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e91a: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); e91e: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e922: fd 27 jz $-4 ;abs 0xe91e status = U0RXBUF; e924: d2 42 76 00 mov.b &0x0076,&0x0210 e928: 10 02 IFG2 &= ~URXIFG0; e92a: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e92e: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); e932: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e936: fd 27 jz $-4 ;abs 0xe932 e938: 03 3c jmp $+8 ;abs 0xe940 { char rx=0; if(reg >= 0x30) reg |= 0xC0; else reg |= 0x80; e93a: 7e d0 80 ff bis.b #-128, r14 ;#0xff80 e93e: e1 3f jmp $-60 ;abs 0xe902 status = U0RXBUF; IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; e940: 5f 42 76 00 mov.b &0x0076,r15 P3OUT |= CSn; //pull CSn high, we're done with the transfer e944: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e948: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 e94c: 1b 00 return rx; e94e: 8f 11 sxt r15 } e950: 30 41 ret 0000e952 : /** Write a register to the CCXX */ void CCXX_SPI_WRREG(char reg, char byte) { e952: 4d 4f mov.b r15, r13 unsigned int dummy; status=0; e954: c2 43 10 02 mov.b #0, &0x0210 ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip e958: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e95c: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 e960: fd 23 jnz $-4 ;abs 0xe95c P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e962: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e e966: 1b 00 IFG2 &= ~URXIFG0; e968: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; e96c: c2 4d 77 00 mov.b r13, &0x0077 while (!(IFG2 & URXIFG0)); e970: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e974: fd 27 jz $-4 ;abs 0xe970 status = U0RXBUF; e976: d2 42 76 00 mov.b &0x0076,&0x0210 e97a: 10 02 IFG2 &= ~URXIFG0; e97c: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = byte; e980: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); e984: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 e988: fd 27 jz $-4 ;abs 0xe984 dummy = U0RXBUF; e98a: 5f 42 76 00 mov.b &0x0076,r15 P3OUT |= CSn; //pull CSn high, we're done with the transfer e98e: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode e992: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 e996: 1b 00 } e998: 30 41 ret 0000e99a : /** Strobe a command to the CCXX */ void CCXX_SPI_STROBE(char reg) { status=0; e99a: 0b 12 push r11 e99c: 0a 12 push r10 e99e: 09 12 push r9 e9a0: 0a 4f mov r15, r10 P3OUT &= ~CSn; //pull CSn low to activate chip e9a2: 4d 43 clr.b r13 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e9a4: 0b 43 clr r11 e9a6: 0c 43 clr r12 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high e9a8: e2 c2 22 00 bic.b #4, &0x0022 ;r2 As==10 IFG2 &= ~URXIFG0; U0TXBUF = reg; e9ac: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e9b0: 0b 24 jz $+24 ;abs 0xe9c8 while (!(IFG2 & URXIFG0)); status = U0RXBUF; e9b2: 1b 53 inc r11 e9b4: 0c 63 adc r12 e9b6: 3b 90 20 a1 cmp #-24288,r11 ;#0xa120 e9ba: 03 20 jnz $+8 ;abs 0xe9c2 e9bc: 3c 90 07 00 cmp #7, r12 ;#0x0007 e9c0: 40 24 jz $+130 ;abs 0xea42 e9c2: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e9c6: f5 23 jnz $-20 ;abs 0xe9b2 P3OUT |= CSn; //pull CSn high, we're done with the transfer P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode } e9c8: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 /** e9cc: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e9d0: 20 01 Read a register from the CCXX e9d2: 7e 42 mov.b #8, r14 ;r2 As==11 */ char CCXX_SPI_RDREG(char reg) { e9d4: 4d 5d rla.b r13 char rx=0; e9d6: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 e9da: fd 23 jnz $-4 ;abs 0xe9d6 if(reg >= 0x30) e9dc: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 e9e0: 4f 43 clr.b r15 e9e2: 4f 63 adc.b r15 e9e4: 4d df bis.b r15, r13 reg |= 0xC0; e9e6: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 else e9ea: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 e9ee: fd 27 jz $-4 ;abs 0xe9ea reg |= 0x80; e9f0: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode } /** Read a register from the CCXX e9f4: 7e 53 add.b #-1, r14 ;r3 As==11 e9f6: ee 23 jnz $-34 ;abs 0xe9d4 reg |= 0xC0; else reg |= 0x80; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip e9f8: 49 4d mov.b r13, r9 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low e9fa: 0c 43 clr r12 e9fc: 4f 4d mov.b r13, r15 e9fe: 3f 53 add #-1, r15 ;r3 As==11 ea00: 0c 9f cmp r15, r12 ea02: 23 2c jc $+72 ;abs 0xea4a ea04: 0b 4f mov r15, r11 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ea06: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ea0a: 20 01 ea0c: 7e 42 mov.b #8, r14 ;r2 As==11 IFG2 &= ~URXIFG0; U0TXBUF = reg; ea0e: 4d 5d rla.b r13 while (!(IFG2 & URXIFG0)); ea10: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 ea14: fd 23 jnz $-4 ;abs 0xea10 status = U0RXBUF; ea16: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ea1a: 4f 43 clr.b r15 ea1c: 4f 63 adc.b r15 ea1e: 4d df bis.b r15, r13 ea20: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 IFG2 &= ~URXIFG0; ea24: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 ea28: fd 27 jz $-4 ;abs 0xea24 U0TXBUF = reg; ea2a: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 P3OUT &= ~CSn; //pull CSn low to activate chip while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ea2e: 7e 53 add.b #-1, r14 ;r3 As==11 ea30: ee 23 jnz $-34 ;abs 0xea0e status = U0RXBUF; IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; ea32: 0f 4a mov r10, r15 ea34: 0f 5c add r12, r15 ea36: cf 4d 00 00 mov.b r13, 0(r15) ;0x0000(r15) reg |= 0x80; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low ea3a: 1c 53 inc r12 ea3c: 0c 9b cmp r11, r12 ea3e: e3 2b jnc $-56 ;abs 0xea06 ea40: 04 3c jmp $+10 ;abs 0xea4a IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); status = U0RXBUF; P3OUT |= CSn; //pull CSn high, we're done with the transfer ea42: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ea46: 20 01 ea48: bc 3f jmp $-134 ;abs 0xe9c2 IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; P3OUT |= CSn; //pull CSn high, we're done with the transfer ea4a: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode return rx; ea4e: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 ea52: 20 01 } ea54: 4f 49 mov.b r9, r15 ea56: 8f 11 sxt r15 ea58: 39 41 pop r9 ea5a: 3a 41 pop r10 ea5c: 3b 41 pop r11 ea5e: 30 41 ret 0000ea60 : /** Write a register to the CCXX */ void CCXX_SPI_WRREG(char reg, char byte) ea60: 0b 12 push r11 ea62: 0a 12 push r10 ea64: 0a 4f mov r15, r10 { unsigned int dummy; ea66: 0c 43 clr r12 ea68: 0d 43 clr r13 status=0; P3OUT &= ~CSn; //pull CSn low to activate chip ea6a: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ea6e: 02 20 jnz $+6 ;abs 0xea74 ea70: 0f 43 clr r15 ea72: 5f 3c jmp $+192 ;abs 0xeb32 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ea74: e2 d2 22 00 bis.b #4, &0x0022 ;r2 As==10 ea78: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 IFG2 &= ~URXIFG0; U0TXBUF = reg; ea7c: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ea80: 0b 24 jz $+24 ;abs 0xea98 while (!(IFG2 & URXIFG0)); status = U0RXBUF; ea82: 1c 53 inc r12 ea84: 0d 63 adc r13 ea86: 3c 90 20 a1 cmp #-24288,r12 ;#0xa120 ea8a: 03 20 jnz $+8 ;abs 0xea92 ea8c: 3d 90 07 00 cmp #7, r13 ;#0x0007 ea90: 4c 24 jz $+154 ;abs 0xeb2a ea92: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ea96: f5 23 jnz $-20 ;abs 0xea82 IFG2 &= ~URXIFG0; U0TXBUF = byte; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; ea98: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ea9c: 20 01 P3OUT |= CSn; //pull CSn high, we're done with the transfer ea9e: 4d 4e mov.b r14, r13 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode eaa0: 7c 42 mov.b #8, r12 ;r2 As==11 } eaa2: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 eaa6: fd 23 jnz $-4 ;abs 0xeaa2 eaa8: 4f 4d mov.b r13, r15 eaaa: 4f 5f rla.b r15 eaac: 4f 43 clr.b r15 eaae: 4f 6f rlc.b r15 eab0: c2 df 21 00 bis.b r15, &0x0021 eab4: e2 c2 21 00 bic.b #4, &0x0021 ;r2 As==10 eab8: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 eabc: fd 27 jz $-4 ;abs 0xeab8 eabe: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 eac2: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 eac6: 4d 5d rla.b r13 U0TXBUF = byte; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; P3OUT |= CSn; //pull CSn high, we're done with the transfer P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode eac8: 7c 53 add.b #-1, r12 ;r3 As==11 eaca: eb 23 jnz $-40 ;abs 0xeaa2 eacc: 4b 4e mov.b r14, r11 eace: 0e 43 clr r14 ead0: 1b 93 cmp #1, r11 ;r3 As==01 ead2: 21 24 jz $+68 ;abs 0xeb16 ead4: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ead8: 20 01 eada: 0f 4a mov r10, r15 eadc: 0f 5e add r14, r15 eade: 6d 4f mov.b @r15, r13 eae0: 7c 42 mov.b #8, r12 ;r2 As==11 eae2: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 eae6: fd 23 jnz $-4 ;abs 0xeae2 eae8: 4f 4d mov.b r13, r15 eaea: 4f 5f rla.b r15 eaec: 4f 43 clr.b r15 eaee: 4f 6f rlc.b r15 eaf0: c2 df 21 00 bis.b r15, &0x0021 eaf4: e2 c2 21 00 bic.b #4, &0x0021 ;r2 As==10 eaf8: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 eafc: fd 27 jz $-4 ;abs 0xeaf8 eafe: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 eb02: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 eb06: 4d 5d rla.b r13 eb08: 7c 53 add.b #-1, r12 ;r3 As==11 eb0a: eb 23 jnz $-40 ;abs 0xeae2 eb0c: 1e 53 inc r14 eb0e: 0f 4b mov r11, r15 eb10: 3f 53 add #-1, r15 ;r3 As==11 eb12: 0e 9f cmp r15, r14 eb14: df 2b jnc $-64 ;abs 0xead4 eb16: e2 c2 22 00 bic.b #4, &0x0022 ;r2 As==10 eb1a: f2 d0 05 00 bis.b #5, &0x0021 ;#0x0005 eb1e: 21 00 eb20: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 eb24: 20 01 eb26: 1f 43 mov #1, r15 ;r3 As==01 eb28: 04 3c jmp $+10 ;abs 0xeb32 IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); status = U0RXBUF; IFG2 &= ~URXIFG0; eb2a: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 eb2e: 20 01 eb30: b0 3f jmp $-158 ;abs 0xea92 eb32: 3a 41 pop r10 eb34: 3b 41 pop r11 eb36: 30 41 ret 0000eb38 : eb38: 0b 12 push r11 eb3a: 0a 12 push r10 eb3c: 0c 4f mov r15, r12 eb3e: 0a 43 clr r10 eb40: 0b 43 clr r11 eb42: 6d 4f mov.b @r15, r13 eb44: 7d 90 20 00 cmp.b #32, r13 ;#0x0020 eb48: 49 24 jz $+148 ;abs 0xebdc eb4a: 7d 90 09 00 cmp.b #9, r13 ;#0x0009 eb4e: 46 24 jz $+142 ;abs 0xebdc eb50: 7d 90 0a 00 cmp.b #10, r13 ;#0x000a eb54: 43 24 jz $+136 ;abs 0xebdc eb56: 7d 90 0c 00 cmp.b #12, r13 ;#0x000c eb5a: 40 24 jz $+130 ;abs 0xebdc eb5c: 7d 90 0d 00 cmp.b #13, r13 ;#0x000d eb60: 3d 24 jz $+124 ;abs 0xebdc eb62: 7d 90 0b 00 cmp.b #11, r13 ;#0x000b eb66: 3a 24 jz $+118 ;abs 0xebdc eb68: 7d 90 2d 00 cmp.b #45, r13 ;#0x002d eb6c: 35 24 jz $+108 ;abs 0xebd8 eb6e: 7d 90 2b 00 cmp.b #43, r13 ;#0x002b eb72: 2f 24 jz $+96 ;abs 0xebd2 eb74: 4f 4d mov.b r13, r15 eb76: 8f 11 sxt r15 eb78: 0e 43 clr r14 eb7a: 3f 50 d0 ff add #-48, r15 ;#0xffd0 eb7e: 3f 90 0a 00 cmp #10, r15 ;#0x000a eb82: 01 2c jc $+4 ;abs 0xeb86 eb84: 1e 43 mov #1, r14 ;r3 As==01 eb86: 0e 93 tst r14 eb88: 02 20 jnz $+6 ;abs 0xeb8e eb8a: 0f 43 clr r15 eb8c: 3c 3c jmp $+122 ;abs 0xec06 eb8e: 4f 4d mov.b r13, r15 eb90: 8f 11 sxt r15 eb92: 0b 5f add r15, r11 eb94: 3b 50 d0 ff add #-48, r11 ;#0xffd0 eb98: 1c 53 inc r12 eb9a: 6f 4c mov.b @r12, r15 eb9c: 4d 4f mov.b r15, r13 eb9e: 8f 11 sxt r15 eba0: 0e 43 clr r14 eba2: 3f 50 d0 ff add #-48, r15 ;#0xffd0 eba6: 3f 90 0a 00 cmp #10, r15 ;#0x000a ebaa: 01 2c jc $+4 ;abs 0xebae ebac: 1e 43 mov #1, r14 ;r3 As==01 ebae: 0e 93 tst r14 ebb0: 0a 24 jz $+22 ;abs 0xebc6 ebb2: 0f 4b mov r11, r15 ebb4: 0f 5f rla r15 ebb6: 0f 5f rla r15 ebb8: 0e 4b mov r11, r14 ebba: 0e 5e rla r14 ebbc: 0b 4f mov r15, r11 ebbe: 0b 5e add r14, r11 ebc0: 0b 5e add r14, r11 ebc2: 0b 5e add r14, r11 ebc4: e4 3f jmp $-54 ;abs 0xeb8e ebc6: 0a 93 tst r10 ebc8: 02 24 jz $+6 ;abs 0xebce ebca: 3b e3 inv r11 ebcc: 1b 53 inc r11 ebce: 0f 4b mov r11, r15 ebd0: 1a 3c jmp $+54 ;abs 0xec06 ebd2: 1c 53 inc r12 ebd4: 6d 4c mov.b @r12, r13 ebd6: ce 3f jmp $-98 ;abs 0xeb74 ebd8: 1a 43 mov #1, r10 ;r3 As==01 ebda: fb 3f jmp $-8 ;abs 0xebd2 ebdc: 1c 53 inc r12 ebde: 6d 4c mov.b @r12, r13 ebe0: 7d 90 20 00 cmp.b #32, r13 ;#0x0020 ebe4: fb 27 jz $-8 ;abs 0xebdc ebe6: 7d 90 09 00 cmp.b #9, r13 ;#0x0009 ebea: f8 27 jz $-14 ;abs 0xebdc ebec: 7d 90 0a 00 cmp.b #10, r13 ;#0x000a ebf0: f5 27 jz $-20 ;abs 0xebdc ebf2: 7d 90 0c 00 cmp.b #12, r13 ;#0x000c ebf6: f2 27 jz $-26 ;abs 0xebdc ebf8: 7d 90 0d 00 cmp.b #13, r13 ;#0x000d ebfc: ef 27 jz $-32 ;abs 0xebdc ebfe: 7d 90 0b 00 cmp.b #11, r13 ;#0x000b ec02: ec 27 jz $-38 ;abs 0xebdc ec04: b1 3f jmp $-156 ;abs 0xeb68 ec06: 3a 41 pop r10 ec08: 3b 41 pop r11 ec0a: 30 41 ret 0000ec0c : ec0c: 0b 12 push r11 ec0e: 0a 12 push r10 ec10: 3f 40 06 00 mov #6, r15 ;#0x0006 ec14: 0f 51 add r1, r15 ec16: 2a 4f mov @r15, r10 ec18: 1b 4f 02 00 mov 2(r15), r11 ;0x0002(r15) ec1c: 1e 4f 04 00 mov 4(r15), r14 ;0x0004(r15) ec20: 3f 50 06 00 add #6, r15 ;#0x0006 ec24: 0c 4f mov r15, r12 ec26: 0d 4e mov r14, r13 ec28: 0e 4b mov r11, r14 ec2a: 0f 4a mov r10, r15 ec2c: b0 12 56 ec call #0xec56 ec30: 3a 41 pop r10 ec32: 3b 41 pop r11 ec34: 30 41 ret 0000ec36 : ec36: 0e 4f mov r15, r14 ec38: a2 93 06 02 cmp #2, &0x0206 ;r3 As==10 ec3c: 0a 28 jnc $+22 ;abs 0xec52 ec3e: 1f 42 04 02 mov &0x0204,r15 ec42: cf 4e 00 00 mov.b r14, 0(r15) ;0x0000(r15) ec46: 92 53 04 02 inc &0x0204 ec4a: b2 53 06 02 add #-1, &0x0206 ;r3 As==11 ec4e: 4f 4e mov.b r14, r15 ec50: 30 41 ret ec52: 3f 43 mov #-1, r15 ;r3 As==11 ec54: 30 41 ret 0000ec56 : ec56: 0b 12 push r11 ec58: 0a 12 push r10 ec5a: 0b 4f mov r15, r11 ec5c: 0a 4d mov r13, r10 ec5e: 82 4b 04 02 mov r11, &0x0204 ec62: 82 4e 06 02 mov r14, &0x0206 ec66: 0d 4c mov r12, r13 ec68: 0e 4a mov r10, r14 ec6a: 3f 40 36 ec mov #-5066, r15 ;#0xec36 ec6e: b0 12 e2 ec call #0xece2 ec72: 0b 5f add r15, r11 ec74: cb 43 00 00 mov.b #0, 0(r11) ;r3 As==00, 0x0000(r11) ec78: 3a 41 pop r10 ec7a: 3b 41 pop r11 ec7c: 30 41 ret 0000ec7e : ec7e: 0b 12 push r11 ec80: 0a 12 push r10 ec82: 0a 4f mov r15, r10 ec84: 0b 4e mov r14, r11 ec86: 0e 93 tst r14 ec88: 02 20 jnz $+6 ;abs 0xec8e ec8a: 1f 43 mov #1, r15 ;r3 As==01 ec8c: 0d 3c jmp $+28 ;abs 0xeca8 ec8e: 6f 4a mov.b @r10, r15 ec90: 8f 11 sxt r15 ec92: 1a 53 inc r10 ec94: 92 12 08 02 call &0x0208 ec98: 0f 93 tst r15 ec9a: 05 38 jl $+12 ;abs 0xeca6 ec9c: 92 53 02 02 inc &0x0202 eca0: 3b 53 add #-1, r11 ;r3 As==11 eca2: f5 23 jnz $-20 ;abs 0xec8e eca4: f2 3f jmp $-26 ;abs 0xec8a eca6: 3f 43 mov #-1, r15 ;r3 As==11 eca8: 3a 41 pop r10 ecaa: 3b 41 pop r11 ecac: 30 41 ret 0000ecae <__write_pad>: ecae: 0b 12 push r11 ecb0: 0a 12 push r10 ecb2: 09 12 push r9 ecb4: 49 4f mov.b r15, r9 ecb6: 4b 4e mov.b r14, r11 ecb8: 5e 93 cmp.b #1, r14 ;r3 As==01 ecba: 0c 38 jl $+26 ;abs 0xecd4 ecbc: 4a 4f mov.b r15, r10 ecbe: 8a 11 sxt r10 ecc0: 0f 4a mov r10, r15 ecc2: 92 12 08 02 call &0x0208 ecc6: 0f 93 tst r15 ecc8: 07 38 jl $+16 ;abs 0xecd8 ecca: 92 53 02 02 inc &0x0202 ecce: 7b 53 add.b #-1, r11 ;r3 As==11 ecd0: 5b 93 cmp.b #1, r11 ;r3 As==01 ecd2: f6 37 jge $-18 ;abs 0xecc0 ecd4: 4f 49 mov.b r9, r15 ecd6: 01 3c jmp $+4 ;abs 0xecda ecd8: 3f 43 mov #-1, r15 ;r3 As==11 ecda: 39 41 pop r9 ecdc: 3a 41 pop r10 ecde: 3b 41 pop r11 ece0: 30 41 ret 0000ece2 : ece2: 0b 12 push r11 ece4: 0a 12 push r10 ece6: 09 12 push r9 ece8: 08 12 push r8 ecea: 07 12 push r7 ecec: 06 12 push r6 ecee: 05 12 push r5 ecf0: 04 12 push r4 ecf2: 31 80 3c 00 sub #60, r1 ;#0x003c ecf6: 05 4d mov r13, r5 ecf8: 81 43 30 00 mov #0, 48(r1) ;r3 As==00, 0x0030(r1) ecfc: 81 43 32 00 mov #0, 50(r1) ;r3 As==00, 0x0032(r1) ed00: 82 43 02 02 mov #0, &0x0202 ;r3 As==00 ed04: 82 4f 08 02 mov r15, &0x0208 ed08: 06 4e mov r14, r6 ed0a: 0f 46 mov r6, r15 ed0c: 67 46 mov.b @r6, r7 ed0e: 47 93 tst.b r7 ed10: 0a 24 jz $+22 ;abs 0xed26 ed12: 77 90 25 00 cmp.b #37, r7 ;#0x0025 ed16: 07 24 jz $+16 ;abs 0xed26 ed18: 16 53 inc r6 ed1a: 67 46 mov.b @r6, r7 ed1c: 47 93 tst.b r7 ed1e: 03 24 jz $+8 ;abs 0xed26 ed20: 77 90 25 00 cmp.b #37, r7 ;#0x0025 ed24: f9 23 jnz $-12 ;abs 0xed18 ed26: 0d 46 mov r6, r13 ed28: 0d 8f sub r15, r13 ed2a: 02 24 jz $+6 ;abs 0xed30 ed2c: 30 40 70 f2 br #0xf270 ed30: 47 93 tst.b r7 ed32: 02 20 jnz $+6 ;abs 0xed38 ed34: 30 40 7e f2 br #0xf27e ed38: 16 53 inc r6 ed3a: c1 43 2e 00 mov.b #0, 46(r1) ;r3 As==00, 0x002e(r1) ed3e: c1 43 35 00 mov.b #0, 53(r1) ;r3 As==00, 0x0035(r1) ed42: c1 43 2f 00 mov.b #0, 47(r1) ;r3 As==00, 0x002f(r1) ed46: 7b 43 mov.b #-1, r11 ;r3 As==11 ed48: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) ed4c: 67 46 mov.b @r6, r7 ed4e: 16 53 inc r6 ed50: 77 90 75 00 cmp.b #117, r7 ;#0x0075 ed54: 02 20 jnz $+6 ;abs 0xed5a ed56: 30 40 4a f2 br #0xf24a ed5a: 4f 47 mov.b r7, r15 ed5c: 7f d0 20 00 bis.b #32, r15 ;#0x0020 ed60: 7f 90 78 00 cmp.b #120, r15 ;#0x0078 ed64: 02 20 jnz $+6 ;abs 0xed6a ed66: 30 40 4a f2 br #0xf24a ed6a: 77 90 20 00 cmp.b #32, r7 ;#0x0020 ed6e: 02 20 jnz $+6 ;abs 0xed74 ed70: 30 40 36 f2 br #0xf236 ed74: 77 90 23 00 cmp.b #35, r7 ;#0x0023 ed78: 02 20 jnz $+6 ;abs 0xed7e ed7a: 30 40 2e f2 br #0xf22e ed7e: 77 90 2a 00 cmp.b #42, r7 ;#0x002a ed82: 02 20 jnz $+6 ;abs 0xed88 ed84: 30 40 12 f2 br #0xf212 ed88: 77 90 2d 00 cmp.b #45, r7 ;#0x002d ed8c: 02 20 jnz $+6 ;abs 0xed92 ed8e: 30 40 02 f2 br #0xf202 ed92: 77 90 2b 00 cmp.b #43, r7 ;#0x002b ed96: 02 20 jnz $+6 ;abs 0xed9c ed98: 30 40 f8 f1 br #0xf1f8 ed9c: 77 90 2e 00 cmp.b #46, r7 ;#0x002e eda0: 02 20 jnz $+6 ;abs 0xeda6 eda2: 30 40 92 f1 br #0xf192 eda6: 77 90 30 00 cmp.b #48, r7 ;#0x0030 edaa: 02 20 jnz $+6 ;abs 0xedb0 edac: 30 40 7c f1 br #0xf17c edb0: 4f 47 mov.b r7, r15 edb2: 7f 50 cf ff add.b #-49, r15 ;#0xffcf edb6: 7f 90 09 00 cmp.b #9, r15 ;#0x0009 edba: 1a 2c jc $+54 ;abs 0xedf0 edbc: 0d 43 clr r13 edbe: 0f 4d mov r13, r15 edc0: 0f 5f rla r15 edc2: 0f 5f rla r15 edc4: 0e 4d mov r13, r14 edc6: 0e 5e rla r14 edc8: 0d 4f mov r15, r13 edca: 0d 5e add r14, r13 edcc: 0d 5e add r14, r13 edce: 0d 5e add r14, r13 edd0: 4f 47 mov.b r7, r15 edd2: 8f 11 sxt r15 edd4: 0d 5f add r15, r13 edd6: 3d 50 d0 ff add #-48, r13 ;#0xffd0 edda: 67 46 mov.b @r6, r7 eddc: 16 53 inc r6 edde: 4f 47 mov.b r7, r15 ede0: 7f 50 d0 ff add.b #-48, r15 ;#0xffd0 ede4: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a ede8: ea 2b jnc $-42 ;abs 0xedbe edea: c1 4d 2f 00 mov.b r13, 47(r1) ;0x002f(r1) edee: b0 3f jmp $-158 ;abs 0xed50 edf0: 77 90 68 00 cmp.b #104, r7 ;#0x0068 edf4: bf 25 jz $+896 ;abs 0xf174 edf6: 77 90 6c 00 cmp.b #108, r7 ;#0x006c edfa: 03 20 jnz $+8 ;abs 0xee02 edfc: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) ee00: a5 3f jmp $-180 ;abs 0xed4c ee02: 77 90 63 00 cmp.b #99, r7 ;#0x0063 ee06: af 25 jz $+864 ;abs 0xf166 ee08: 77 90 44 00 cmp.b #68, r7 ;#0x0044 ee0c: a9 25 jz $+852 ;abs 0xf160 ee0e: 77 90 64 00 cmp.b #100, r7 ;#0x0064 ee12: 7a 25 jz $+758 ;abs 0xf108 ee14: 77 90 69 00 cmp.b #105, r7 ;#0x0069 ee18: 77 25 jz $+752 ;abs 0xf108 ee1a: 77 90 4f 00 cmp.b #79, r7 ;#0x004f ee1e: 71 25 jz $+740 ;abs 0xf102 ee20: 77 90 6f 00 cmp.b #111, r7 ;#0x006f ee24: 6b 25 jz $+728 ;abs 0xf0fc ee26: 77 90 70 00 cmp.b #112, r7 ;#0x0070 ee2a: 59 25 jz $+692 ;abs 0xf0de ee2c: 77 90 73 00 cmp.b #115, r7 ;#0x0073 ee30: 1a 25 jz $+566 ;abs 0xf066 ee32: 77 90 55 00 cmp.b #85, r7 ;#0x0055 ee36: 14 25 jz $+554 ;abs 0xf060 ee38: 77 90 75 00 cmp.b #117, r7 ;#0x0075 ee3c: 0d 25 jz $+540 ;abs 0xf058 ee3e: 77 90 58 00 cmp.b #88, r7 ;#0x0058 ee42: 8a 24 jz $+278 ;abs 0xef58 ee44: 77 90 78 00 cmp.b #120, r7 ;#0x0078 ee48: 87 24 jz $+272 ;abs 0xef58 ee4a: 47 93 tst.b r7 ee4c: 02 20 jnz $+6 ;abs 0xee52 ee4e: 30 40 7e f2 br #0xf27e ee52: 81 41 2c 00 mov r1, 44(r1) ;0x002c(r1) ee56: c1 47 00 00 mov.b r7, 0(r1) ;0x0000(r1) ee5a: 59 43 mov.b #1, r9 ;r3 As==01 ee5c: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) ee60: 4b 49 mov.b r9, r11 ee62: 5a 41 35 00 mov.b 53(r1), r10 ;0x0035(r1) ee66: 4a 89 sub.b r9, r10 ee68: 75 30 jn $+236 ;abs 0xef54 ee6a: 5e 41 2a 00 mov.b 42(r1), r14 ;0x002a(r1) ee6e: 4e 93 tst.b r14 ee70: 6b 24 jz $+216 ;abs 0xef48 ee72: 5b 53 inc.b r11 ee74: 4b 5a add.b r10, r11 ee76: 58 41 2e 00 mov.b 46(r1), r8 ;0x002e(r1) ee7a: 78 f0 30 00 and.b #48, r8 ;#0x0030 ee7e: 13 20 jnz $+40 ;abs 0xeea6 ee80: 5d 41 2f 00 mov.b 47(r1), r13 ;0x002f(r1) ee84: 8d 11 sxt r13 ee86: 4f 4b mov.b r11, r15 ee88: 8f 11 sxt r15 ee8a: 0d 8f sub r15, r13 ee8c: 1d 93 cmp #1, r13 ;r3 As==01 ee8e: 0b 38 jl $+24 ;abs 0xeea6 ee90: 4e 4d mov.b r13, r14 ee92: 7f 40 20 00 mov.b #32, r15 ;#0x0020 ee96: b0 12 ae ec call #0xecae ee9a: 0f 93 tst r15 ee9c: 02 34 jge $+6 ;abs 0xeea2 ee9e: 30 40 7e f2 br #0xf27e eea2: 5e 41 2a 00 mov.b 42(r1), r14 ;0x002a(r1) eea6: 4e 93 tst.b r14 eea8: 4a 20 jnz $+150 ;abs 0xef3e eeaa: f1 b0 40 00 bit.b #64, 46(r1) ;#0x0040, 0x002e(r1) eeae: 2e 00 eeb0: 0f 24 jz $+32 ;abs 0xeed0 eeb2: f1 40 30 00 mov.b #48, 40(r1) ;#0x0030, 0x0028(r1) eeb6: 28 00 eeb8: c1 47 29 00 mov.b r7, 41(r1) ;0x0029(r1) eebc: 2e 43 mov #2, r14 ;r3 As==10 eebe: 0f 41 mov r1, r15 eec0: 3f 50 28 00 add #40, r15 ;#0x0028 eec4: b0 12 7e ec call #0xec7e eec8: 0f 93 tst r15 eeca: 02 34 jge $+6 ;abs 0xeed0 eecc: 30 40 7e f2 br #0xf27e eed0: 78 90 20 00 cmp.b #32, r8 ;#0x0020 eed4: 24 24 jz $+74 ;abs 0xef1e eed6: 4e 4a mov.b r10, r14 eed8: 7f 40 30 00 mov.b #48, r15 ;#0x0030 eedc: b0 12 ae ec call #0xecae eee0: 0f 93 tst r15 eee2: cd 39 jl $+924 ;abs 0xf27e eee4: 4f 49 mov.b r9, r15 eee6: 8f 11 sxt r15 eee8: 0e 4f mov r15, r14 eeea: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) eeee: b0 12 7e ec call #0xec7e eef2: 0f 93 tst r15 eef4: c4 39 jl $+906 ;abs 0xf27e eef6: f1 b0 10 00 bit.b #16, 46(r1) ;#0x0010, 0x002e(r1) eefa: 2e 00 eefc: 06 27 jz $-498 ;abs 0xed0a eefe: 5d 41 2f 00 mov.b 47(r1), r13 ;0x002f(r1) ef02: 8d 11 sxt r13 ef04: 4f 4b mov.b r11, r15 ef06: 8f 11 sxt r15 ef08: 0d 8f sub r15, r13 ef0a: 1d 93 cmp #1, r13 ;r3 As==01 ef0c: fe 3a jl $-514 ;abs 0xed0a ef0e: 4e 4d mov.b r13, r14 ef10: 7f 40 20 00 mov.b #32, r15 ;#0x0020 ef14: b0 12 ae ec call #0xecae ef18: 0f 93 tst r15 ef1a: f7 36 jge $-528 ;abs 0xed0a ef1c: b0 3d jmp $+866 ;abs 0xf27e ef1e: 5d 41 2f 00 mov.b 47(r1), r13 ;0x002f(r1) ef22: 8d 11 sxt r13 ef24: 4f 4b mov.b r11, r15 ef26: 8f 11 sxt r15 ef28: 0d 8f sub r15, r13 ef2a: 1d 93 cmp #1, r13 ;r3 As==01 ef2c: d4 3b jl $-86 ;abs 0xeed6 ef2e: 4e 4d mov.b r13, r14 ef30: 7f 40 30 00 mov.b #48, r15 ;#0x0030 ef34: b0 12 ae ec call #0xecae ef38: 0f 93 tst r15 ef3a: cd 37 jge $-100 ;abs 0xeed6 ef3c: a0 3d jmp $+834 ;abs 0xf27e ef3e: 1e 43 mov #1, r14 ;r3 As==01 ef40: 0f 41 mov r1, r15 ef42: 3f 50 2a 00 add #42, r15 ;#0x002a ef46: be 3f jmp $-130 ;abs 0xeec4 ef48: f1 b0 40 00 bit.b #64, 46(r1) ;#0x0040, 0x002e(r1) ef4c: 2e 00 ef4e: 92 27 jz $-218 ;abs 0xee74 ef50: 6b 53 incd.b r11 ef52: 90 3f jmp $-222 ;abs 0xee74 ef54: 4a 43 clr.b r10 ef56: 89 3f jmp $-236 ;abs 0xee6a ef58: f1 40 10 00 mov.b #16, 52(r1) ;#0x0010, 0x0034(r1) ef5c: 34 00 ef5e: f1 b2 2e 00 bit.b #8, 46(r1) ;r2 As==11, 0x002e(r1) ef62: 09 24 jz $+20 ;abs 0xef76 ef64: 81 93 30 00 tst 48(r1) ;0x0030(r1) ef68: 03 20 jnz $+8 ;abs 0xef70 ef6a: 81 93 32 00 tst 50(r1) ;0x0032(r1) ef6e: 03 24 jz $+8 ;abs 0xef76 ef70: f1 d0 40 00 bis.b #64, 46(r1) ;#0x0040, 0x002e(r1) ef74: 2e 00 ef76: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) ef7a: c1 4b 35 00 mov.b r11, 53(r1) ;0x0035(r1) ef7e: 4b 93 tst.b r11 ef80: 03 38 jl $+8 ;abs 0xef88 ef82: f1 f0 df ff and.b #-33, 46(r1) ;#0xffdf, 0x002e(r1) ef86: 2e 00 ef88: 0f 41 mov r1, r15 ef8a: 3f 50 28 00 add #40, r15 ;#0x0028 ef8e: 81 4f 2c 00 mov r15, 44(r1) ;0x002c(r1) ef92: 81 93 30 00 tst 48(r1) ;0x0030(r1) ef96: 06 20 jnz $+14 ;abs 0xefa4 ef98: 81 93 32 00 tst 50(r1) ;0x0032(r1) ef9c: 03 20 jnz $+8 ;abs 0xefa4 ef9e: c1 93 35 00 tst.b 53(r1) ;0x0035(r1) efa2: 3e 24 jz $+126 ;abs 0xf020 efa4: d1 41 34 00 mov.b 52(r1), 56(r1) ;0x0034(r1), 0x0038(r1) efa8: 38 00 efaa: c1 43 39 00 mov.b #0, 57(r1) ;r3 As==00, 0x0039(r1) efae: 81 43 3a 00 mov #0, 58(r1) ;r3 As==00, 0x003a(r1) efb2: c1 43 36 00 mov.b #0, 54(r1) ;r3 As==00, 0x0036(r1) efb6: 1e 41 30 00 mov 48(r1), r14 ;0x0030(r1) efba: 1f 41 32 00 mov 50(r1), r15 ;0x0032(r1) efbe: 1e 81 38 00 sub 56(r1), r14 ;0x0038(r1) efc2: 1f 71 3a 00 subc 58(r1), r15 ;0x003a(r1) efc6: 02 28 jnc $+6 ;abs 0xefcc efc8: d1 43 36 00 mov.b #1, 54(r1) ;r3 As==01, 0x0036(r1) efcc: 1c 41 30 00 mov 48(r1), r12 ;0x0030(r1) efd0: 1d 41 32 00 mov 50(r1), r13 ;0x0032(r1) efd4: 1a 41 38 00 mov 56(r1), r10 ;0x0038(r1) efd8: 1b 41 3a 00 mov 58(r1), r11 ;0x003a(r1) efdc: b0 12 84 f3 call #0xf384 efe0: 44 4e mov.b r14, r4 efe2: 7e 90 0a 00 cmp.b #10, r14 ;#0x000a efe6: 30 2c jc $+98 ;abs 0xf048 efe8: 74 50 30 00 add.b #48, r4 ;#0x0030 efec: b1 53 2c 00 add #-1, 44(r1) ;r3 As==11, 0x002c(r1) eff0: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) eff4: cf 44 00 00 mov.b r4, 0(r15) ;0x0000(r15) eff8: 1c 41 30 00 mov 48(r1), r12 ;0x0030(r1) effc: 1d 41 32 00 mov 50(r1), r13 ;0x0032(r1) f000: 1a 41 38 00 mov 56(r1), r10 ;0x0038(r1) f004: 1b 41 3a 00 mov 58(r1), r11 ;0x003a(r1) f008: b0 12 84 f3 call #0xf384 f00c: 81 4c 30 00 mov r12, 48(r1) ;0x0030(r1) f010: 81 4d 32 00 mov r13, 50(r1) ;0x0032(r1) f014: c1 93 36 00 tst.b 54(r1) ;0x0036(r1) f018: cc 23 jnz $-102 ;abs 0xefb2 f01a: f1 92 34 00 cmp.b #8, 52(r1) ;r2 As==11, 0x0034(r1) f01e: 06 24 jz $+14 ;abs 0xf02c f020: 49 41 mov.b r1, r9 f022: 59 81 2c 00 sub.b 44(r1), r9 ;0x002c(r1) f026: 79 50 28 00 add.b #40, r9 ;#0x0028 f02a: 1a 3f jmp $-458 ;abs 0xee60 f02c: f1 b2 2e 00 bit.b #8, 46(r1) ;r2 As==11, 0x002e(r1) f030: f7 27 jz $-16 ;abs 0xf020 f032: 74 90 30 00 cmp.b #48, r4 ;#0x0030 f036: f4 27 jz $-22 ;abs 0xf020 f038: b1 53 2c 00 add #-1, 44(r1) ;r3 As==11, 0x002c(r1) f03c: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f040: ff 40 30 00 mov.b #48, 0(r15) ;#0x0030, 0x0000(r15) f044: 00 00 f046: ec 3f jmp $-38 ;abs 0xf020 f048: 74 50 57 00 add.b #87, r4 ;#0x0057 f04c: 77 90 58 00 cmp.b #88, r7 ;#0x0058 f050: cd 23 jnz $-100 ;abs 0xefec f052: 74 f0 df ff and.b #-33, r4 ;#0xffdf f056: ca 3f jmp $-106 ;abs 0xefec f058: f1 40 0a 00 mov.b #10, 52(r1) ;#0x000a, 0x0034(r1) f05c: 34 00 f05e: 8b 3f jmp $-232 ;abs 0xef76 f060: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f064: f9 3f jmp $-12 ;abs 0xf058 f066: 0f 45 mov r5, r15 f068: 25 53 incd r5 f06a: a1 4f 2c 00 mov @r15, 44(r1) ;0x002c(r1) f06e: 81 93 2c 00 tst 44(r1) ;0x002c(r1) f072: 1e 24 jz $+62 ;abs 0xf0b0 f074: 4b 93 tst.b r11 f076: 11 38 jl $+36 ;abs 0xf09a f078: 4f 4b mov.b r11, r15 f07a: 8f 11 sxt r15 f07c: 0d 4f mov r15, r13 f07e: 0e 43 clr r14 f080: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f084: b0 12 b2 f2 call #0xf2b2 f088: 0f 93 tst r15 f08a: 05 24 jz $+12 ;abs 0xf096 f08c: 49 4f mov.b r15, r9 f08e: 59 81 2c 00 sub.b 44(r1), r9 ;0x002c(r1) f092: 4b 99 cmp.b r9, r11 f094: e3 36 jge $-568 ;abs 0xee5c f096: 49 4b mov.b r11, r9 f098: e1 3e jmp $-572 ;abs 0xee5c f09a: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f09e: 1f 83 dec r15 f0a0: 1f 53 inc r15 f0a2: cf 93 00 00 tst.b 0(r15) ;0x0000(r15) f0a6: fc 23 jnz $-6 ;abs 0xf0a0 f0a8: 49 4f mov.b r15, r9 f0aa: 59 81 2c 00 sub.b 44(r1), r9 ;0x002c(r1) f0ae: d6 3e jmp $-594 ;abs 0xee5c f0b0: 81 41 2c 00 mov r1, 44(r1) ;0x002c(r1) f0b4: f1 40 28 00 mov.b #40, 0(r1) ;#0x0028, 0x0000(r1) f0b8: 00 00 f0ba: f1 40 6e 00 mov.b #110, 1(r1) ;#0x006e, 0x0001(r1) f0be: 01 00 f0c0: f1 40 75 00 mov.b #117, 2(r1) ;#0x0075, 0x0002(r1) f0c4: 02 00 f0c6: f1 40 6c 00 mov.b #108, 3(r1) ;#0x006c, 0x0003(r1) f0ca: 03 00 f0cc: f1 40 6c 00 mov.b #108, 4(r1) ;#0x006c, 0x0004(r1) f0d0: 04 00 f0d2: f1 40 29 00 mov.b #41, 5(r1) ;#0x0029, 0x0005(r1) f0d6: 05 00 f0d8: c1 43 06 00 mov.b #0, 6(r1) ;r3 As==00, 0x0006(r1) f0dc: cb 3f jmp $-104 ;abs 0xf074 f0de: 0f 45 mov r5, r15 f0e0: 25 53 incd r5 f0e2: a1 4f 30 00 mov @r15, 48(r1) ;0x0030(r1) f0e6: 81 43 32 00 mov #0, 50(r1) ;r3 As==00, 0x0032(r1) f0ea: f1 40 10 00 mov.b #16, 52(r1) ;#0x0010, 0x0034(r1) f0ee: 34 00 f0f0: f1 d0 40 00 bis.b #64, 46(r1) ;#0x0040, 0x002e(r1) f0f4: 2e 00 f0f6: 77 40 78 00 mov.b #120, r7 ;#0x0078 f0fa: 3d 3f jmp $-388 ;abs 0xef76 f0fc: f1 42 34 00 mov.b #8, 52(r1) ;r2 As==11, 0x0034(r1) f100: 3a 3f jmp $-394 ;abs 0xef76 f102: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f106: fa 3f jmp $-10 ;abs 0xf0fc f108: d1 b3 2e 00 bit.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f10c: 19 24 jz $+52 ;abs 0xf140 f10e: 0f 45 mov r5, r15 f110: 25 52 add #4, r5 ;r2 As==10 f112: b1 4f 30 00 mov @r15+, 48(r1) ;0x0030(r1) f116: b1 4f 32 00 mov @r15+, 50(r1) ;0x0032(r1) f11a: 81 93 32 00 tst 50(r1) ;0x0032(r1) f11e: 04 38 jl $+10 ;abs 0xf128 f120: f1 40 0a 00 mov.b #10, 52(r1) ;#0x000a, 0x0034(r1) f124: 34 00 f126: 29 3f jmp $-428 ;abs 0xef7a f128: b1 e3 30 00 xor #-1, 48(r1) ;r3 As==11, 0x0030(r1) f12c: b1 e3 32 00 xor #-1, 50(r1) ;r3 As==11, 0x0032(r1) f130: 91 53 30 00 inc 48(r1) ;0x0030(r1) f134: 81 63 32 00 adc 50(r1) ;0x0032(r1) f138: f1 40 2d 00 mov.b #45, 42(r1) ;#0x002d, 0x002a(r1) f13c: 2a 00 f13e: f0 3f jmp $-30 ;abs 0xf120 f140: 0f 45 mov r5, r15 f142: 25 53 incd r5 f144: a1 4f 30 00 mov @r15, 48(r1) ;0x0030(r1) f148: 91 41 30 00 mov 48(r1), 50(r1) ;0x0030(r1), 0x0032(r1) f14c: 32 00 f14e: 91 51 32 00 rla 50(r1) ;0x0032(r1) f152: 32 00 f154: 91 71 32 00 subc 50(r1), 50(r1) ;0x0032(r1), 0x0032(r1) f158: 32 00 f15a: b1 e3 32 00 xor #-1, 50(r1) ;r3 As==11, 0x0032(r1) f15e: dd 3f jmp $-68 ;abs 0xf11a f160: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f164: d1 3f jmp $-92 ;abs 0xf108 f166: 81 41 2c 00 mov r1, 44(r1) ;0x002c(r1) f16a: 0f 45 mov r5, r15 f16c: 25 53 incd r5 f16e: e1 4f 00 00 mov.b @r15, 0(r1) ;0x0000(r1) f172: 73 3e jmp $-792 ;abs 0xee5a f174: e1 d2 2e 00 bis.b #4, 46(r1) ;r2 As==10, 0x002e(r1) f178: 30 40 4c ed br #0xed4c f17c: f1 b0 10 00 bit.b #16, 46(r1) ;#0x0010, 0x002e(r1) f180: 2e 00 f182: 02 24 jz $+6 ;abs 0xf188 f184: 30 40 4c ed br #0xed4c f188: f1 d0 20 00 bis.b #32, 46(r1) ;#0x0020, 0x002e(r1) f18c: 2e 00 f18e: 30 40 4c ed br #0xed4c f192: 67 46 mov.b @r6, r7 f194: 16 53 inc r6 f196: 77 90 2a 00 cmp.b #42, r7 ;#0x002a f19a: 24 24 jz $+74 ;abs 0xf1e4 f19c: 0d 43 clr r13 f19e: 4f 47 mov.b r7, r15 f1a0: 7f 50 d0 ff add.b #-48, r15 ;#0xffd0 f1a4: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a f1a8: 16 2c jc $+46 ;abs 0xf1d6 f1aa: 0f 4d mov r13, r15 f1ac: 0f 5f rla r15 f1ae: 0f 5f rla r15 f1b0: 0e 4d mov r13, r14 f1b2: 0e 5e rla r14 f1b4: 0d 4f mov r15, r13 f1b6: 0d 5e add r14, r13 f1b8: 0d 5e add r14, r13 f1ba: 0d 5e add r14, r13 f1bc: 4f 47 mov.b r7, r15 f1be: 8f 11 sxt r15 f1c0: 0d 5f add r15, r13 f1c2: 3d 50 d0 ff add #-48, r13 ;#0xffd0 f1c6: 67 46 mov.b @r6, r7 f1c8: 16 53 inc r6 f1ca: 4f 47 mov.b r7, r15 f1cc: 7f 50 d0 ff add.b #-48, r15 ;#0xffd0 f1d0: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a f1d4: ea 2b jnc $-42 ;abs 0xf1aa f1d6: 0f 4d mov r13, r15 f1d8: 3d 93 cmp #-1, r13 ;r3 As==11 f1da: 01 34 jge $+4 ;abs 0xf1de f1dc: 3f 43 mov #-1, r15 ;r3 As==11 f1de: 4b 4f mov.b r15, r11 f1e0: 30 40 50 ed br #0xed50 f1e4: 0f 45 mov r5, r15 f1e6: 25 53 incd r5 f1e8: 2d 4f mov @r15, r13 f1ea: 0f 4d mov r13, r15 f1ec: 3d 93 cmp #-1, r13 ;r3 As==11 f1ee: 01 34 jge $+4 ;abs 0xf1f2 f1f0: 3f 43 mov #-1, r15 ;r3 As==11 f1f2: 4b 4f mov.b r15, r11 f1f4: 30 40 4c ed br #0xed4c f1f8: f1 40 2b 00 mov.b #43, 42(r1) ;#0x002b, 0x002a(r1) f1fc: 2a 00 f1fe: 30 40 4c ed br #0xed4c f202: f1 d0 10 00 bis.b #16, 46(r1) ;#0x0010, 0x002e(r1) f206: 2e 00 f208: f1 f0 df ff and.b #-33, 46(r1) ;#0xffdf, 0x002e(r1) f20c: 2e 00 f20e: 30 40 4c ed br #0xed4c f212: 0f 45 mov r5, r15 f214: 25 53 incd r5 f216: e1 4f 2f 00 mov.b @r15, 47(r1) ;0x002f(r1) f21a: c1 93 2f 00 tst.b 47(r1) ;0x002f(r1) f21e: 02 38 jl $+6 ;abs 0xf224 f220: 30 40 4c ed br #0xed4c f224: f1 e3 2f 00 xor.b #-1, 47(r1) ;r3 As==11, 0x002f(r1) f228: d1 53 2f 00 inc.b 47(r1) ;0x002f(r1) f22c: ea 3f jmp $-42 ;abs 0xf202 f22e: f1 d2 2e 00 bis.b #8, 46(r1) ;r2 As==11, 0x002e(r1) f232: 30 40 4c ed br #0xed4c f236: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) f23a: 02 24 jz $+6 ;abs 0xf240 f23c: 30 40 4c ed br #0xed4c f240: f1 40 20 00 mov.b #32, 42(r1) ;#0x0020, 0x002a(r1) f244: 2a 00 f246: 30 40 4c ed br #0xed4c f24a: d1 b3 2e 00 bit.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f24e: 08 24 jz $+18 ;abs 0xf260 f250: 0f 45 mov r5, r15 f252: 25 52 add #4, r5 ;r2 As==10 f254: b1 4f 30 00 mov @r15+, 48(r1) ;0x0030(r1) f258: b1 4f 32 00 mov @r15+, 50(r1) ;0x0032(r1) f25c: 30 40 6a ed br #0xed6a f260: 0f 45 mov r5, r15 f262: 25 53 incd r5 f264: a1 4f 30 00 mov @r15, 48(r1) ;0x0030(r1) f268: 81 43 32 00 mov #0, 50(r1) ;r3 As==00, 0x0032(r1) f26c: 30 40 6a ed br #0xed6a f270: 0e 4d mov r13, r14 f272: b0 12 7e ec call #0xec7e f276: 0f 93 tst r15 f278: 02 38 jl $+6 ;abs 0xf27e f27a: 30 40 30 ed br #0xed30 f27e: 1f 42 02 02 mov &0x0202,r15 f282: 31 50 3c 00 add #60, r1 ;#0x003c f286: 34 41 pop r4 f288: 35 41 pop r5 f28a: 36 41 pop r6 f28c: 37 41 pop r7 f28e: 38 41 pop r8 f290: 39 41 pop r9 f292: 3a 41 pop r10 f294: 3b 41 pop r11 f296: 30 41 ret 0000f298 : f298: 0d 4f mov r15, r13 f29a: 0f 4e mov r14, r15 f29c: 6e 4d mov.b @r13, r14 f29e: 4e 9f cmp.b r15, r14 f2a0: 06 24 jz $+14 ;abs 0xf2ae f2a2: 4e 93 tst.b r14 f2a4: 02 24 jz $+6 ;abs 0xf2aa f2a6: 1d 53 inc r13 f2a8: f9 3f jmp $-12 ;abs 0xf29c f2aa: 0f 43 clr r15 f2ac: 30 41 ret f2ae: 0f 4d mov r13, r15 f2b0: 30 41 ret 0000f2b2 : f2b2: 0b 12 push r11 f2b4: 0b 4f mov r15, r11 f2b6: 4c 4e mov.b r14, r12 f2b8: 0d 93 tst r13 f2ba: 07 24 jz $+16 ;abs 0xf2ca f2bc: 0e 4b mov r11, r14 f2be: 6f 4e mov.b @r14, r15 f2c0: 1e 53 inc r14 f2c2: 4f 9c cmp.b r12, r15 f2c4: 04 24 jz $+10 ;abs 0xf2ce f2c6: 3d 53 add #-1, r13 ;r3 As==11 f2c8: fa 23 jnz $-10 ;abs 0xf2be f2ca: 0f 43 clr r15 f2cc: 02 3c jmp $+6 ;abs 0xf2d2 f2ce: 0f 4e mov r14, r15 f2d0: 3f 53 add #-1, r15 ;r3 As==11 f2d2: 3b 41 pop r11 f2d4: 30 41 ret 0000f2d6 : f2d6: 0b 12 push r11 f2d8: 0b 4d mov r13, r11 f2da: 0d 93 tst r13 f2dc: 0a 24 jz $+22 ;abs 0xf2f2 f2de: 0c 4f mov r15, r12 f2e0: 0d 4e mov r14, r13 f2e2: 6e 4d mov.b @r13, r14 f2e4: 1d 53 inc r13 f2e6: 6f 4c mov.b @r12, r15 f2e8: 1c 53 inc r12 f2ea: 4f 9e cmp.b r14, r15 f2ec: 04 20 jnz $+10 ;abs 0xf2f6 f2ee: 3b 53 add #-1, r11 ;r3 As==11 f2f0: f8 23 jnz $-14 ;abs 0xf2e2 f2f2: 0c 43 clr r12 f2f4: 05 3c jmp $+12 ;abs 0xf300 f2f6: 5c 4c ff ff mov.b -1(r12),r12 ;0xffff(r12) f2fa: 5f 4d ff ff mov.b -1(r13),r15 ;0xffff(r13) f2fe: 0c 8f sub r15, r12 f300: 0f 4c mov r12, r15 f302: 3b 41 pop r11 f304: 30 41 ret 0000f306 : f306: 0b 12 push r11 f308: 0a 12 push r10 f30a: 09 12 push r9 f30c: 08 12 push r8 f30e: 0b 4f mov r15, r11 f310: 0a 4e mov r14, r10 f312: 69 4e mov.b @r14, r9 f314: 1a 53 inc r10 f316: 49 93 tst.b r9 f318: 15 24 jz $+44 ;abs 0xf344 f31a: 08 4a mov r10, r8 f31c: 18 83 dec r8 f31e: 18 53 inc r8 f320: c8 93 00 00 tst.b 0(r8) ;0x0000(r8) f324: fc 23 jnz $-6 ;abs 0xf31e f326: 08 8a sub r10, r8 f328: 6f 4b mov.b @r11, r15 f32a: 1b 53 inc r11 f32c: 4f 93 tst.b r15 f32e: 0c 24 jz $+26 ;abs 0xf348 f330: 4f 99 cmp.b r9, r15 f332: fa 23 jnz $-10 ;abs 0xf328 f334: 0d 48 mov r8, r13 f336: 0e 4a mov r10, r14 f338: 0f 4b mov r11, r15 f33a: b0 12 54 f3 call #0xf354 f33e: 0f 93 tst r15 f340: f3 23 jnz $-24 ;abs 0xf328 f342: 3b 53 add #-1, r11 ;r3 As==11 f344: 0f 4b mov r11, r15 f346: 01 3c jmp $+4 ;abs 0xf34a f348: 0f 43 clr r15 f34a: 38 41 pop r8 f34c: 39 41 pop r9 f34e: 3a 41 pop r10 f350: 3b 41 pop r11 f352: 30 41 ret 0000f354 : f354: 0b 12 push r11 f356: 0b 4f mov r15, r11 f358: 0d 93 tst r13 f35a: 02 20 jnz $+6 ;abs 0xf360 f35c: 0d 43 clr r13 f35e: 0f 3c jmp $+32 ;abs 0xf37e f360: 6f 4e mov.b @r14, r15 f362: 1e 53 inc r14 f364: 6c 4b mov.b @r11, r12 f366: 4c 9f cmp.b r15, r12 f368: 06 20 jnz $+14 ;abs 0xf376 f36a: 1b 53 inc r11 f36c: 4c 93 tst.b r12 f36e: f6 27 jz $-18 ;abs 0xf35c f370: 3d 53 add #-1, r13 ;r3 As==11 f372: f6 23 jnz $-18 ;abs 0xf360 f374: f3 3f jmp $-24 ;abs 0xf35c f376: 4d 4c mov.b r12, r13 f378: 5f 4e ff ff mov.b -1(r14),r15 ;0xffff(r14) f37c: 0d 8f sub r15, r13 f37e: 0f 4d mov r13, r15 f380: 3b 41 pop r11 f382: 30 41 ret 0000f384 <__udivmodsi4>: f384: 0f ef xor r15, r15 f386: 0e ee xor r14, r14 f388: 39 40 21 00 mov #33, r9 ;#0x0021 f38c: 0a 3c jmp $+22 ;abs 0xf3a2 f38e: 08 10 rrc r8 f390: 0e 6e rlc r14 f392: 0f 6f rlc r15 f394: 0f 9b cmp r11, r15 f396: 05 28 jnc $+12 ;abs 0xf3a2 f398: 02 20 jnz $+6 ;abs 0xf39e f39a: 0e 9a cmp r10, r14 f39c: 02 28 jnc $+6 ;abs 0xf3a2 f39e: 0e 8a sub r10, r14 f3a0: 0f 7b subc r11, r15 f3a2: 0c 6c rlc r12 f3a4: 0d 6d rlc r13 f3a6: 08 68 rlc r8 f3a8: 19 83 dec r9 f3aa: f1 23 jnz $-28 ;abs 0xf38e f3ac: 30 41 ret 0000f3ae <__stop_progExec__>: f3ae: ff 3f jmp $+0 ;abs 0xf3ae Disassembly of section .vectors: 0000ffe0 : ffe0: 30 e0 30 e0 56 e0 36 e0 30 e0 30 e0 30 e0 30 e0 0.0.V.6.0.0.0.0. fff0: 30 e0 30 e0 30 e0 30 e0 30 e0 30 e0 30 e0 00 e0 0.0.0.0.0.0.0...