gng_tx.elf: file format elf32-msp430 SYMBOL TABLE: 0000e000 l d .text 00000000 .text 00000200 l d .data 00000000 .data 00000204 l d .bss 00000000 .bss 0000ffe0 l d .vectors 00000000 .vectors 00000000 l d .stab 00000000 .stab 00000000 l d .stabstr 00000000 .stabstr 00000070 l *ABS* 00000000 U0CTL 00000071 l *ABS* 00000000 U0TCTL 00000072 l *ABS* 00000000 U0RCTL 00000073 l *ABS* 00000000 U0MCTL 00000074 l *ABS* 00000000 U0BR0 00000075 l *ABS* 00000000 U0BR1 00000076 l *ABS* 00000000 U0RXBUF 00000077 l *ABS* 00000000 U0TXBUF 00000070 l *ABS* 00000000 UCTL 00000071 l *ABS* 00000000 UTCTL 00000072 l *ABS* 00000000 URCTL 00000073 l *ABS* 00000000 UMCTL 00000074 l *ABS* 00000000 UBR0 00000075 l *ABS* 00000000 UBR1 00000076 l *ABS* 00000000 RXBUF 00000077 l *ABS* 00000000 TXBUF 00000070 l *ABS* 00000000 UCTL0 00000071 l *ABS* 00000000 UTCTL0 00000072 l *ABS* 00000000 URCTL0 00000073 l *ABS* 00000000 UMCTL0 00000074 l *ABS* 00000000 UBR00 00000075 l *ABS* 00000000 UBR10 00000076 l *ABS* 00000000 RXBUF0 00000077 l *ABS* 00000000 TXBUF0 00000070 l *ABS* 00000000 UCTL_0 00000071 l *ABS* 00000000 UTCTL_0 00000072 l *ABS* 00000000 URCTL_0 00000073 l *ABS* 00000000 UMCTL_0 00000074 l *ABS* 00000000 UBR0_0 00000075 l *ABS* 00000000 UBR1_0 00000076 l *ABS* 00000000 RXBUF_0 00000077 l *ABS* 00000000 TXBUF_0 00000020 l *ABS* 00000000 P1IN 00000021 l *ABS* 00000000 P1OUT 00000022 l *ABS* 00000000 P1DIR 00000023 l *ABS* 00000000 P1IFG 00000024 l *ABS* 00000000 P1IES 00000025 l *ABS* 00000000 P1IE 00000026 l *ABS* 00000000 P1SEL 00000028 l *ABS* 00000000 P2IN 00000029 l *ABS* 00000000 P2OUT 0000002a l *ABS* 00000000 P2DIR 0000002b l *ABS* 00000000 P2IFG 0000002c l *ABS* 00000000 P2IES 0000002d l *ABS* 00000000 P2IE 0000002e l *ABS* 00000000 P2SEL 00000018 l *ABS* 00000000 P3IN 00000019 l *ABS* 00000000 P3OUT 0000001a l *ABS* 00000000 P3DIR 0000001b l *ABS* 00000000 P3SEL 0000012e l *ABS* 00000000 TA0IV 00000160 l *ABS* 00000000 TA0CTL 00000170 l *ABS* 00000000 TA0R 00000162 l *ABS* 00000000 TA0CCTL0 00000164 l *ABS* 00000000 TA0CCTL1 00000172 l *ABS* 00000000 TA0CCR0 00000174 l *ABS* 00000000 TA0CCR1 00000166 l *ABS* 00000000 TA0CCTL2 00000176 l *ABS* 00000000 TA0CCR2 00000056 l *ABS* 00000000 DCOCTL 00000057 l *ABS* 00000000 BCSCTL1 00000058 l *ABS* 00000000 BCSCTL2 00000128 l *ABS* 00000000 FCTL1 0000012a l *ABS* 00000000 FCTL2 0000012c l *ABS* 00000000 FCTL3 00000048 l *ABS* 00000000 ADC10DTC0 00000049 l *ABS* 00000000 ADC10DTC1 0000004a l *ABS* 00000000 ADC10AE0 000001b0 l *ABS* 00000000 ADC10CTL0 000001b2 l *ABS* 00000000 ADC10CTL1 000001b4 l *ABS* 00000000 ADC10MEM 000001bc l *ABS* 00000000 ADC10SA 00000120 l *ABS* 00000000 WDTCTL 00000000 l *ABS* 00000000 IE1 00000002 l *ABS* 00000000 IFG1 00000001 l *ABS* 00000000 IE2 00000003 l *ABS* 00000000 IFG2 00000005 l *ABS* 00000000 ME2 00000000 l df *ABS* 00000000 main.c 00000200 l O .data 00000001 make_gdb_happy 0000ea24 l .text 00000000 Letext 00000000 l df *ABS* 00000000 spi_hardware.c 0000eb6a l .text 00000000 Letext 00000000 l df *ABS* 00000000 interchip.c 0000ed08 l .text 00000000 Letext 00000000 l df *ABS* 00000000 atoi.c 0000eddc l .text 00000000 Letext 00000000 l df *ABS* 00000000 snprintf.c 0000ee06 l .text 00000000 Letext 00000000 l df *ABS* 00000000 vsnprintf.c 0000ee06 l F .text 00000020 mem_putchar_limited 00000206 l .bss 00000000 max_s_size 00000204 l .bss 00000000 mem 0000ee4e l .text 00000000 Letext 00000000 l df *ABS* 00000000 vuprintf.c 00000202 l O .data 00000002 total_len 0000ee4e l F .text 00000030 PRINT 00000208 l .bss 00000000 __write_char 0000ee7e l F .text 00000034 __write_pad 0000f468 l .text 00000000 Letext 00000000 l df *ABS* 00000000 strchr.c 0000f482 l .text 00000000 Letext 00000000 l df *ABS* 00000000 memchr.c 0000f4a6 l .text 00000000 Letext 00000000 l df *ABS* 00000000 memcmp.c 0000f4d6 l .text 00000000 Letext 00000000 l df *ABS* 00000000 strstr.c 0000f524 l .text 00000000 Letext 00000000 l df *ABS* 00000000 strncmp.c 0000f554 l .text 00000000 Letext 00000004 g *ABS* 00000000 __data_size 0000ea5a g F .text 0000005c CCXX_SPI_RDREG 0000ec30 g F .text 000000d8 send_string 0000e120 g F .text 0000002a init_UART_SPI 0000eddc g F .text 0000002a snprintf 0000f596 g .text 00000000 _etext 0000e106 g F .text 0000001a sample_adc 00000009 g *ABS* 00000000 __bss_size 0000f594 w .text 00000000 __stop_progExec__ 0000e030 g .text 00000000 _unexpected_1_ 0000e030 w .text 00000000 vector_ffe0 0000e082 g F .text 00000076 sys_init 0000ee26 g F .text 00000028 vsnprintf 0000ea24 g F .text 00000036 CCXX_SPI_STROBE 0000e030 w .text 00000000 vector_ffec 0000e030 w .text 00000000 vector_fff0 0000f596 g *ABS* 00000000 __data_load_start 0000e030 g .text 00000000 __dtors_end 0000e030 w .text 00000000 vector_fffc 0000eab6 g F .text 00000048 CCXX_SPI_WRREG 0000e716 g F .text 000002b8 CCXX_WRITE_SPI_RF_SETTINGS 0000f554 g .text 00000000 __mulhi3 0000e036 g .text 00000000 vector_ffe4 0000eafe g F .text 0000006c CCXX_SPI_BURST_WRREG 0000ffe0 g O .vectors 00000020 InterruptVectors 0000eb6a g F .text 000000c6 get_string 0000f482 g F .text 00000024 memchr 0000e01c w .text 00000000 __do_clear_bss 0000f4d6 g F .text 0000004e strstr 0000f524 g F .text 00000030 strncmp 0000e030 w .text 00000000 vector_ffe2 0000e030 w .text 00000000 vector_ffe8 0000e034 w .text 00000000 _unexpected_ 0000e030 w .text 00000000 vector_fffa 0000eeb2 g F .text 000005b6 vuprintf 0000f4a6 g F .text 00000030 memcmp 0000e0f8 g F .text 0000000e init_adc 0000e036 g F .text 0000001e P1_VEC 0000e000 w .text 00000000 _reset_vector__ 0000e030 g .text 00000000 __ctors_start 0000e00a w .text 00000000 __do_copy_data 00000204 g .bss 00000000 __bss_start 0000e030 w .text 00000000 vector_ffee 0000e030 w .text 00000000 vector_fff4 0000e2e0 g F .text 00000436 main 0000e030 w .text 00000000 vector_fff8 0000e030 w .text 00000000 vector_fff2 00010000 g .vectors 00000000 _vectors_end 0000e030 w .text 00000000 vector_ffe6 0000e054 g F .text 0000002e delay 0000e9ce g F .text 00000056 TX_STRING 0000e000 w .text 00000000 __init_stack 0000e030 g .text 00000000 __dtors_start 0000e030 g .text 00000000 __ctors_end 00000300 g *ABS* 00000000 __stack 00000204 g .data 00000000 _edata 0000020d g .bss 00000000 _end 0000020a g O .bss 00000002 flags 0000f56a g .text 00000000 __udivmodsi4 0000ed08 g F .text 000000d4 atoi 0000e030 w .text 00000000 vector_fff6 0000e004 w .text 00000000 __low_level_init 0000e02c w .text 00000000 __jump_to_main 0000f468 g F .text 0000001a strchr 00000200 g .data 00000000 __data_start 0000e030 w .text 00000000 vector_ffea 0000020c g O .bss 00000001 status Disassembly of section .text: 0000e000 <__init_stack>: e000: 31 40 00 03 mov #768, r1 ;#0x0300 0000e004 <__low_level_init>: e004: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e008: 20 01 0000e00a <__do_copy_data>: e00a: 3f 40 04 00 mov #4, r15 ;#0x0004 e00e: 0f 93 tst r15 e010: 05 24 jz $+12 ;abs 0xe01c e012: 2f 83 decd r15 e014: 9f 4f 96 f5 mov -2666(r15),512(r15);0xf596(r15), 0x0200(r15) e018: 00 02 e01a: fb 23 jnz $-8 ;abs 0xe012 0000e01c <__do_clear_bss>: e01c: 3f 40 09 00 mov #9, r15 ;#0x0009 e020: 0f 93 tst r15 e022: 04 24 jz $+10 ;abs 0xe02c e024: 1f 83 dec r15 e026: cf 43 04 02 mov.b #0, 516(r15);r3 As==00, 0x0204(r15) e02a: fc 23 jnz $-6 ;abs 0xe024 0000e02c <__jump_to_main>: e02c: 30 40 e0 e2 br #0xe2e0 0000e030 <__ctors_end>: e030: 30 40 34 e0 br #0xe034 0000e034 <_unexpected_>: e034: 00 13 reti 0000e036 : unsigned char status; volatile int flags; // Port 1 interripts : The arbiter is talking to us interrupt (PORT1_VECTOR) P1_VEC(void) { e036: 0f 12 push r15 dint(); e038: 32 c2 dint if((P1IFG & ARB_RX) == ARB_RX) //The arbiter is sending us a string e03a: e2 b3 23 00 bit.b #2, &0x0023 ;r3 As==10 e03e: 05 24 jz $+12 ;abs 0xe04a { flags |= ARBITER_RDY; e040: a2 d3 0a 02 bis #2, &0x020a ;r3 As==10 LPM3_EXIT; e044: b1 c0 d0 00 bic #208, 2(r1) ;#0x00d0, 0x0002(r1) e048: 02 00 //We need to send that byte! } P1IFG=0x00; e04a: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 eint(); e04e: 32 d2 eint } e050: 3f 41 pop r15 e052: 00 13 reti 0000e054 : Delay function. */ void delay(unsigned int d) { int i; for (i = 0; i: Set up the system */ void sys_init() { WDTCTL = WDTCTL_INIT; //Init watchdog timer e082: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 e086: 20 01 P1OUT = P1OUT_INIT; //Init output data of port1 e088: f2 40 05 00 mov.b #5, &0x0021 ;#0x0005 e08c: 21 00 P2OUT = P2OUT_INIT; //Init output data of port2 e08e: c2 43 29 00 mov.b #0, &0x0029 ;r3 As==00 P3OUT = P3OUT_INIT; e092: d2 43 19 00 mov.b #1, &0x0019 ;r3 As==01 P1SEL = P1SEL_INIT; //Select port or module -function on port1 e096: c2 43 26 00 mov.b #0, &0x0026 ;r3 As==00 P2SEL = P2SEL_INIT; //Select port or module -function on port2 e09a: f2 40 03 00 mov.b #3, &0x002e ;#0x0003 e09e: 2e 00 P3SEL = P3SEL_INIT; e0a0: c2 43 1b 00 mov.b #0, &0x001b ;r3 As==00 P1DIR = P1DIR_INIT; //Init port direction register of port1 e0a4: f2 40 f9 ff mov.b #-7, &0x0022 ;#0xfff9 e0a8: 22 00 P2DIR = P2DIR_INIT; //Init port direction register of port2 e0aa: f2 40 ec ff mov.b #-20, &0x002a ;#0xffec e0ae: 2a 00 P3DIR = P3DIR_INIT; e0b0: f2 40 7b 00 mov.b #123, &0x001a ;#0x007b e0b4: 1a 00 P1IES = P1IES_INIT; //init port interrupts e0b6: e2 43 24 00 mov.b #2, &0x0024 ;r3 As==10 P2IES = P2IES_INIT; e0ba: c2 43 2c 00 mov.b #0, &0x002c ;r3 As==00 P1IE = P1IE_INIT; e0be: e2 43 25 00 mov.b #2, &0x0025 ;r3 As==10 P2IE = P2IE_INIT; e0c2: c2 43 2d 00 mov.b #0, &0x002d ;r3 As==00 BCSCTL1 |= RSEL0 | RSEL1 | RSEL2; e0c6: f2 d0 07 00 bis.b #7, &0x0057 ;#0x0007 e0ca: 57 00 DCOCTL |= DCO0 | DCO1 | DCO2; e0cc: f2 d0 e0 ff bis.b #-32, &0x0056 ;#0xffe0 e0d0: 56 00 BCSCTL2 = DCOR; e0d2: d2 43 58 00 mov.b #1, &0x0058 ;r3 As==01 ME2 |= USPIE0; //enable SPI e0d6: d2 d3 05 00 bis.b #1, &0x0005 ;r3 As==01 U0CTL = CHAR | SYNC | MM | SWRST; e0da: f2 40 17 00 mov.b #23, &0x0070 ;#0x0017 e0de: 70 00 U0TCTL = CKPH | STC | SSEL_3; e0e0: f2 40 b2 ff mov.b #-78, &0x0071 ;#0xffb2 e0e4: 71 00 U0BR0 = 2; //divide by 2 = 4Mhz e0e6: e2 43 74 00 mov.b #2, &0x0074 ;r3 As==10 U0BR1 = 0; e0ea: c2 43 75 00 mov.b #0, &0x0075 ;r3 As==00 U0MCTL = 0; e0ee: c2 43 73 00 mov.b #0, &0x0073 ;r3 As==00 U0CTL &= ~SWRST; // Initialize USART state machine e0f2: d2 c3 70 00 bic.b #1, &0x0070 ;r3 As==01 //delay(0xffff); } e0f6: 30 41 ret 0000e0f8 : /**init the ADC10 */ void init_adc() { //ADC10AE = ADC_IN; ADC10CTL0 = SREF_VREF_AVSS | ADC10SR | ADC10ON | REFON | ADC10SHT_DIV64; //ref mode Vref for temp sense, 50kbps reduced power mode, ADC on, 16 clocks per sample window e0f8: b2 40 30 3c mov #15408, &0x01b0 ;#0x3c30 e0fc: b0 01 //ADC10CTL1 = ADC10SSEL_ACLK | INCH_A2; //ACLK sourced, A2 input ADC10CTL1 = ADC10DIV_7 | ADC10SSEL_ADC10OSC | INCH_TEMP; //ACLK sourced, A2 input e0fe: b2 40 e0 a0 mov #-24352,&0x01b2 ;#0xa0e0 e102: b2 01 } e104: 30 41 ret 0000e106 : //get a reading from the ADC10MEM int sample_adc(int chan) { ADC10CTL0 &= ~ENC; // have to disable ADC10 to change channel e106: a2 c3 b0 01 bic #2, &0x01b0 ;r3 As==10 ADC10CTL1 = chan; // A2 input e10a: 82 4f b2 01 mov r15, &0x01b2 ADC10CTL0 |= ENC | ADC10SC; // Sampling and conversion start e10e: b2 d0 03 00 bis #3, &0x01b0 ;#0x0003 e112: b0 01 while(ADC10CTL1 & ADC10BUSY); e114: 92 b3 b2 01 bit #1, &0x01b2 ;r3 As==01 e118: fd 23 jnz $-4 ;abs 0xe114 return ADC10MEM; e11a: 1f 42 b4 01 mov &0x01b4,r15 } e11e: 30 41 ret 0000e120 : void init_UART_SPI() { U0CTL |= SWRST; // disable the state machine e120: d2 d3 70 00 bis.b #1, &0x0070 ;r3 As==01 ME2 &= ~UTXE0; //disable UART e124: e2 c3 05 00 bic.b #2, &0x0005 ;r3 As==10 ME2 |= USPIE0; //enable SPI e128: d2 d3 05 00 bis.b #1, &0x0005 ;r3 As==01 U0CTL = CHAR | SYNC | MM | SWRST; e12c: f2 40 17 00 mov.b #23, &0x0070 ;#0x0017 e130: 70 00 U0TCTL = CKPH | STC | SSEL_3; e132: f2 40 b2 ff mov.b #-78, &0x0071 ;#0xffb2 e136: 71 00 U0BR0 = 2; //divide by 5 = 1Mhz e138: e2 43 74 00 mov.b #2, &0x0074 ;r3 As==10 U0BR1 = 0; e13c: c2 43 75 00 mov.b #0, &0x0075 ;r3 As==00 U0MCTL = 0; e140: c2 43 73 00 mov.b #0, &0x0073 ;r3 As==00 U0CTL &= ~SWRST; // Initialize USART state machine e144: d2 c3 70 00 bic.b #1, &0x0070 ;r3 As==01 } e148: 30 41 ret e14a: 47 54 add.b r4, r7 e14c: 58 00 .word 0x0058; ???? e14e: 72 65 addc.b @r5+, r2 e150: 73 65 .word 0x6573; ???? Illegal as 2-op instr e152: 74 00 .word 0x0074; ???? e154: 70 6f addc.b @r15+, r0 e156: 77 65 addc.b @r5+, r7 e158: 72 00 .word 0x0072; ???? e15a: 1b 5b 33 32 add 12851(r11),r11 ;0x3233(r11) e15e: 6d 47 mov.b @r7, r13 e160: 4e 44 mov.b r4, r14 e162: 3a 25 jz $+630 ;abs 0xe3d8 e164: 73 20 jnz $+232 ;abs 0xe24c e166: 70 6f addc.b @r15+, r0 e168: 77 65 addc.b @r5+, r7 e16a: 72 20 jnz $+230 ;abs 0xe250 e16c: 69 73 subc.b #2, r9 ;r3 As==10 e16e: 20 6e addc @r14, r0 e170: 6f 77 subc.b @r7, r15 e172: 20 25 jz $+578 ;abs 0xe3b4 e174: 64 1b .word 0x1b64; ???? e176: 5b 33 jn $-328 ;abs 0xe02e e178: 30 6d addc @r13+, r0 e17a: 00 47 br r7 e17c: 4e 44 mov.b r4, r14 e17e: 3a 47 mov @r7+, r10 e180: 54 58 20 57 add.b 22304(r8),r4 ;0x5720(r8) e184: 61 72 subc.b #4, r1 ;r2 As==10 e186: 6e 69 addc.b @r9, r14 e188: 6e 67 addc.b @r7, r14 e18a: 20 39 jl $+578 ;abs 0xe3cc e18c: 30 43 br #-1 ;r3 As==11 e18e: 2b 20 jnz $+88 ;abs 0xe1e6 e190: 61 6d addc.b @r13, r1 e192: 70 20 jnz $+226 ;abs 0xe274 e194: 64 69 addc.b @r9, r4 e196: 73 61 .word 0x6173; ???? Illegal as 2-op instr e198: 62 6c addc.b @r12, r2 e19a: 65 64 addc.b @r4, r5 e19c: 00 47 br r7 e19e: 4e 44 mov.b r4, r14 e1a0: 3a 47 mov @r7+, r10 e1a2: 54 58 20 57 add.b 22304(r8),r4 ;0x5720(r8) e1a6: 61 72 subc.b #4, r1 ;r2 As==10 e1a8: 6e 69 addc.b @r9, r14 e1aa: 6e 67 addc.b @r7, r14 e1ac: 20 38 jl $+66 ;abs 0xe1ee e1ae: 30 43 br #-1 ;r3 As==11 e1b0: 2b 20 jnz $+88 ;abs 0xe208 e1b2: 54 58 20 70 add.b 28704(r8),r4 ;0x7020(r8) e1b6: 6f 77 subc.b @r7, r15 e1b8: 65 72 subc.b #4, r5 ;r2 As==10 e1ba: 20 68 addc @r8, r0 e1bc: 61 6c addc.b @r12, r1 e1be: 76 65 addc.b @r5+, r6 e1c0: 64 21 jnz $+714 ;abs 0xe48a e1c2: 00 47 br r7 e1c4: 4e 44 mov.b r4, r14 e1c6: 3a 47 mov @r7+, r10 e1c8: 54 58 20 57 add.b 22304(r8),r4 ;0x5720(r8) e1cc: 61 72 subc.b #4, r1 ;r2 As==10 e1ce: 6e 69 addc.b @r9, r14 e1d0: 6e 67 addc.b @r7, r14 e1d2: 20 37 jge $-446 ;abs 0xe014 e1d4: 30 43 br #-1 ;r3 As==11 e1d6: 2b 21 jnz $+600 ;abs 0xe42e e1d8: 00 47 br r7 e1da: 4e 44 mov.b r4, r14 e1dc: 3a 47 mov @r7+, r10 e1de: 54 58 20 54 add.b 21536(r8),r4 ;0x5420(r8) e1e2: 65 6d addc.b @r13, r5 e1e4: 70 20 jnz $+226 ;abs 0xe2c6 e1e6: 62 65 addc.b @r5, r2 e1e8: 6c 6f addc.b @r15, r12 e1ea: 77 20 jnz $+240 ;abs 0xe2da e1ec: 37 30 jn $+112 ;abs 0xe25c e1ee: 43 20 jnz $+136 ;abs 0xe276 e1f0: 70 6f addc.b @r15+, r0 e1f2: 77 65 addc.b @r5+, r7 e1f4: 72 20 jnz $+230 ;abs 0xe2da e1f6: 72 65 addc.b @r5+, r2 e1f8: 73 74 .word 0x7473; ???? Illegal as 2-op instr e1fa: 6f 72 subc.b #4, r15 ;r2 As==10 e1fc: 65 64 addc.b @r4, r5 e1fe: 00 1b .word 0x1b00; ???? e200: 5b 33 jn $-328 ;abs 0xe0b8 e202: 32 6d addc @r13+, r2 e204: 47 4e mov.b r14, r7 e206: 44 3a jl $-886 ;abs 0xde90 e208: 25 73 subc #2, r5 ;r3 As==10 e20a: 20 70 subc @r0, r0 e20c: 6f 77 subc.b @r7, r15 e20e: 65 72 subc.b #4, r5 ;r2 As==10 e210: 20 69 addc @r9, r0 e212: 73 20 jnz $+232 ;abs 0xe2fa e214: 28 25 jz $+594 ;abs 0xe466 e216: 64 2f jc $-310 ;abs 0xe0e0 e218: 31 39 jl $+612 ;abs 0xe47c e21a: 35 29 jnc $+620 ;abs 0xe486 e21c: 1b 5b 33 30 add 12339(r11),r11 ;0x3033(r11) e220: 6d 00 .word 0x006d; ???? e222: 63 68 .word 0x6863; ???? Illegal as 2-op instr e224: 61 6e addc.b @r14, r1 e226: 00 1b .word 0x1b00; ???? e228: 5b 33 jn $-328 ;abs 0xe0e0 e22a: 32 6d addc @r13+, r2 e22c: 47 4e mov.b r14, r7 e22e: 44 3a jl $-886 ;abs 0xdeb8 e230: 25 73 subc #2, r5 ;r3 As==10 e232: 20 63 addc #2, r0 ;r3 As==10 e234: 68 61 addc.b @r1, r8 e236: 6e 20 jnz $+222 ;abs 0xe314 e238: 77 61 addc.b @r1+, r7 e23a: 73 20 jnz $+232 ;abs 0xe322 e23c: 25 64 addc @r4, r5 e23e: 20 6e addc @r14, r0 e240: 6f 77 subc.b @r7, r15 e242: 20 25 jz $+578 ;abs 0xe484 e244: 64 1b .word 0x1b64; ???? e246: 5b 33 jn $-328 ;abs 0xe0fe e248: 30 6d addc @r13+, r0 e24a: 00 1b .word 0x1b00; ???? e24c: 5b 33 jn $-328 ;abs 0xe104 e24e: 32 6d addc @r13+, r2 e250: 47 4e mov.b r14, r7 e252: 44 3a jl $-886 ;abs 0xdedc e254: 25 73 subc #2, r5 ;r3 As==10 e256: 20 63 addc #2, r0 ;r3 As==10 e258: 68 61 addc.b @r1, r8 e25a: 6e 20 jnz $+222 ;abs 0xe338 e25c: 69 73 subc.b #2, r9 ;r3 As==10 e25e: 20 25 jz $+578 ;abs 0xe4a0 e260: 64 1b .word 0x1b64; ???? e262: 5b 33 jn $-328 ;abs 0xe11a e264: 30 6d addc @r13+, r0 e266: 00 74 subc r4, r0 e268: 65 6d addc.b @r13, r5 e26a: 70 00 .word 0x0070; ???? e26c: 1b 5b 33 32 add 12851(r11),r11 ;0x3233(r11) e270: 6d 47 mov.b @r7, r13 e272: 4e 44 mov.b r4, r14 e274: 3a 25 jz $+630 ;abs 0xe4ea e276: 73 20 jnz $+232 ;abs 0xe35e e278: 43 68 .word 0x6843; ???? Illegal as 2-op instr e27a: 69 70 subc.b @r0, r9 e27c: 20 25 jz $+578 ;abs 0xe4be e27e: 64 2c jc $+202 ;abs 0xe348 e280: 25 64 addc @r4, r5 e282: 20 2d jc $+578 ;abs 0xe4c4 e284: 20 41 br @r1 e286: 6d 70 subc.b @r0, r13 e288: 20 25 jz $+578 ;abs 0xe4ca e28a: 64 1b .word 0x1b64; ???? e28c: 5b 33 jn $-328 ;abs 0xe144 e28e: 30 6d addc @r13+, r0 e290: 00 72 subc r2, r0 e292: 61 74 subc.b @r4, r1 e294: 65 00 .word 0x0065; ???? e296: 1b 5b 33 32 add 12851(r11),r11 ;0x3233(r11) e29a: 6d 47 mov.b @r7, r13 e29c: 4e 44 mov.b r4, r14 e29e: 3a 25 jz $+630 ;abs 0xe514 e2a0: 73 20 jnz $+232 ;abs 0xe388 e2a2: 72 61 addc.b @r1+, r2 e2a4: 74 65 addc.b @r5+, r4 e2a6: 20 69 addc @r9, r0 e2a8: 73 20 jnz $+232 ;abs 0xe390 e2aa: 25 64 addc @r4, r5 e2ac: 1b 5b 33 30 add 12339(r11),r11 ;0x3033(r11) e2b0: 6d 00 .word 0x006d; ???? e2b2: 1b 5b 33 32 add 12851(r11),r11 ;0x3233(r11) e2b6: 6d 47 mov.b @r7, r13 e2b8: 4e 44 mov.b r4, r14 e2ba: 3a 25 jz $+630 ;abs 0xe530 e2bc: 73 20 jnz $+232 ;abs 0xe3a4 e2be: 72 61 addc.b @r1+, r2 e2c0: 74 65 addc.b @r5+, r4 e2c2: 20 69 addc @r9, r0 e2c4: 73 20 jnz $+232 ;abs 0xe3ac e2c6: 6e 6f addc.b @r15, r14 e2c8: 77 20 jnz $+240 ;abs 0xe3b8 e2ca: 25 64 addc @r4, r5 e2cc: 1b 5b 33 30 add 12339(r11),r11 ;0x3033(r11) e2d0: 6d 00 .word 0x006d; ???? e2d2: 47 4e mov.b r14, r7 e2d4: 44 3a jl $-886 ;abs 0xdf5e e2d6: 47 54 add.b r4, r7 e2d8: 58 20 jnz $+178 ;abs 0xe38a e2da: 70 6f addc.b @r15+, r0 e2dc: 6e 67 addc.b @r7, r14 e2de: 21 00 .word 0x0021; ???? 0000e2e0
: /** Main function. */ int main(void) { e2e0: 31 40 c0 02 mov #704, r1 ;#0x02c0 e2e4: 04 41 mov r1, r4 unsigned int rate=12,i=0; e2e6: 38 40 0c 00 mov #12, r8 ;#0x000c unsigned char loop,cnt=0, length, chan=P2_CHANNR; e2ea: 76 40 32 00 mov.b #50, r6 ;#0x0032 unsigned char interchip[64]; unsigned int power=P2_PATABLE, tsample, amp_tsample=1023, tmpflag=0; e2ee: 35 40 c3 00 mov #195, r5 ;#0x00c3 e2f2: 3b 40 ff 03 mov #1023, r11 ;#0x03ff e2f6: 09 43 clr r9 int temp; sys_init(); e2f8: b0 12 82 e0 call #0xe082 init_UART_SPI(); e2fc: b0 12 20 e1 call #0xe120 init_adc(); e300: b0 12 f8 e0 call #0xe0f8 memset(interchip, 0, 64); e304: 3e 40 40 00 mov #64, r14 ;#0x0040 e308: 0f 44 mov r4, r15 e30a: cf 43 00 00 mov.b #0, 0(r15) ;r3 As==00, 0x0000(r15) e30e: 1f 53 inc r15 e310: 1e 83 dec r14 e312: fb 23 jnz $-8 ;abs 0xe30a P3OUT &= ~CSn; //power on reset, strobe CSn e314: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 delay(0x00FF); e318: 3f 40 ff 00 mov #255, r15 ;#0x00ff e31c: b0 12 54 e0 call #0xe054 P3OUT |= CSn; e320: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 delay(0xFFFF); e324: 3f 43 mov #-1, r15 ;r3 As==11 e326: b0 12 54 e0 call #0xe054 if(CCXX_SPI_RDREG(CCxxx0_CHANNR) == 0) //is this is not zero then the chip has already been programmed and we have rebooted. Don't reprogram chip as it will cut the link! e32a: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e32e: b0 12 5a ea call #0xea5a e332: 4f 93 tst.b r15 e334: cd 21 jnz $+924 ;abs 0xe6d0 { //values straight from RF_STUDIO CCXX_SPI_STROBE(CCxxx0_SRES); //reset chip e336: 7f 40 30 00 mov.b #48, r15 ;#0x0030 e33a: b0 12 24 ea call #0xea24 //delay(0xFFF); CCXX_WRITE_SPI_RF_SETTINGS(12); e33e: 3f 40 0c 00 mov #12, r15 ;#0x000c e342: b0 12 16 e7 call #0xe716 CCXX_SPI_WRREG(CCxxx0_CHANNR, P2_CHANNR); // Channel number. e346: 7e 40 32 00 mov.b #50, r14 ;#0x0032 e34a: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e34e: b0 12 b6 ea call #0xeab6 rate = 384; else if(chan == 0x2D) rate = 2500; chan = CCXX_SPI_RDREG(CCxxx0_CHANNR); } CCXX_SPI_STROBE(CCxxx0_SIDLE); //flush the buffer, all bytes sent e352: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e356: b0 12 24 ea call #0xea24 do{ i = CCXX_SPI_RDREG(CCxxx0_MARCSTATE);//wait for IDLE e35a: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e35e: b0 12 5a ea call #0xea5a e362: 4a 4f mov.b r15, r10 e364: 8a 11 sxt r10 }while(i != 1); e366: 1a 93 cmp #1, r10 ;r3 As==01 e368: f8 23 jnz $-14 ;abs 0xe35a P3OUT ^= LED_RED; e36a: f2 e0 10 00 xor.b #16, &0x0019 ;#0x0010 e36e: 19 00 delay(0xFF); //lil bit O delay e370: 3f 40 ff 00 mov #255, r15 ;#0x00ff e374: b0 12 54 e0 call #0xe054 P3OUT ^= LED_RED; e378: f2 e0 10 00 xor.b #16, &0x0019 ;#0x0010 e37c: 19 00 flags=0; e37e: 82 43 0a 02 mov #0, &0x020a ;r3 As==00 P2IFG=0x00; e382: c2 43 2b 00 mov.b #0, &0x002b ;r3 As==00 P1IFG=0x00; e386: c2 43 23 00 mov.b #0, &0x0023 ;r3 As==00 eint(); e38a: 32 d2 eint while (1) //main loop, never ends... { loop=0; e38c: 47 43 clr.b r7 //if we wake up we know that an event happened, so lets check the flags if((flags & ARBITER_RDY) == ARBITER_RDY) //Arbiter has something to say e38e: a2 b3 0a 02 bit #2, &0x020a ;r3 As==10 e392: 5d 24 jz $+188 ;abs 0xe44e { dint(); e394: 32 c2 dint loop = 1; e396: 57 43 mov.b #1, r7 ;r3 As==01 P3OUT |= LED_RED; e398: f2 d0 10 00 bis.b #16, &0x0019 ;#0x0010 e39c: 19 00 memset(interchip, 0, 64); e39e: 3e 40 40 00 mov #64, r14 ;#0x0040 e3a2: 0f 44 mov r4, r15 e3a4: cf 43 00 00 mov.b #0, 0(r15) ;r3 As==00, 0x0000(r15) e3a8: 1f 53 inc r15 e3aa: 1e 83 dec r14 e3ac: fb 23 jnz $-8 ;abs 0xe3a4 status = 0; e3ae: c2 43 0c 02 mov.b #0, &0x020c ;r3 As==00 length = get_string(interchip); e3b2: 0f 44 mov r4, r15 e3b4: b0 12 6a eb call #0xeb6a e3b8: 4a 4f mov.b r15, r10 P1IFG &= ~ARB_RX; e3ba: e2 c3 23 00 bic.b #2, &0x0023 ;r3 As==10 if(!memcmp(CALLSIGN,interchip,3)) e3be: 3d 40 03 00 mov #3, r13 ;#0x0003 e3c2: 0e 44 mov r4, r14 e3c4: 3f 40 4a e1 mov #-7862, r15 ;#0xe14a e3c8: b0 12 a6 f4 call #0xf4a6 e3cc: 0f 93 tst r15 e3ce: 75 21 jnz $+748 ;abs 0xe6ba { P3OUT |= LED_GRN; e3d0: f2 d0 20 00 bis.b #32, &0x0019 ;#0x0020 e3d4: 19 00 if(strstr( interchip, "reset" ) != NULL) e3d6: 3e 40 4e e1 mov #-7858, r14 ;#0xe14e e3da: 0f 44 mov r4, r15 e3dc: b0 12 d6 f4 call #0xf4d6 e3e0: 0f 93 tst r15 e3e2: 67 21 jnz $+720 ;abs 0xe6b2 { WDTCTL = WDTCNTCL|WDTPW; while(1); //wait for timeout } else if(strstr( interchip, "power" ) != NULL) //interval is in the string! e3e4: 3e 40 54 e1 mov #-7852, r14 ;#0xe154 e3e8: 0f 44 mov r4, r15 e3ea: b0 12 d6 f4 call #0xf4d6 e3ee: 0f 93 tst r15 e3f0: 8e 24 jz $+286 ;abs 0xe50e { length = atoi(strchr(interchip, '=' )+1); //The new interval should follow the equals sign e3f2: 3e 40 3d 00 mov #61, r14 ;#0x003d e3f6: 0f 44 mov r4, r15 e3f8: b0 12 68 f4 call #0xf468 e3fc: 1f 53 inc r15 e3fe: b0 12 08 ed call #0xed08 if(length > 0) e402: 4f 93 tst.b r15 e404: 79 24 jz $+244 ;abs 0xe4f8 { power = length; e406: 45 4f mov.b r15, r5 CCXX_SPI_WRREG(CCxxx0_PATABLE, power); e408: 4e 45 mov.b r5, r14 e40a: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e40e: b0 12 b6 ea call #0xeab6 length = snprintf(interchip,63,"\e[32mGND:%s power is now %d\e[30m",CALLSIGN,power); e412: 05 12 push r5 e414: 30 12 4a e1 push #-7862 ;#0xe14a e418: 30 12 5a e1 push #-7846 ;#0xe15a e41c: 30 12 3f 00 push #63 ;#0x003f e420: 04 12 push r4 e422: b0 12 dc ed call #0xeddc e426: 31 50 0a 00 add #10, r1 ;#0x000a } else length = snprintf(interchip,63,"\e[32mGND:%s power is (%d/195)\e[30m",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_PATABLE)); P2OUT |= TX_EN; e42a: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING(interchip,length); e42e: 4e 4f mov.b r15, r14 e430: 0f 44 mov r4, r15 e432: b0 12 ce e9 call #0xe9ce e436: 0b 4f mov r15, r11 } else { P2OUT |= TX_EN; amp_tsample = TX_STRING("GND:GTX pong!",13); P2OUT &= ~TX_EN; e438: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 } P3OUT &= ~LED_GRN; e43c: f2 f0 df ff and.b #-33, &0x0019 ;#0xffdf e440: 19 00 P2OUT |= TX_EN; amp_tsample = TX_STRING(interchip,length-1); P2OUT &= ~TX_EN; } flags &= ~ARBITER_RDY; e442: a2 c3 0a 02 bic #2, &0x020a ;r3 As==10 P3OUT &= ~LED_RED; e446: f2 f0 ef ff and.b #-17, &0x0019 ;#0xffef e44a: 19 00 eint(); e44c: 32 d2 eint } //193 90 C //227 80 C //295 70 C if(amp_tsample < 200) //amp is over 90 degrees!! e44e: 3b 90 c8 00 cmp #200, r11 ;#0x00c8 e452: 1c 2c jc $+58 ;abs 0xe48c { if(tmpflag < 3) e454: 39 90 03 00 cmp #3, r9 ;#0x0003 e458: 14 2c jc $+42 ;abs 0xe482 { tmpflag = 3; e45a: 39 40 03 00 mov #3, r9 ;#0x0003 P2OUT |= TX_EN; e45e: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING("GND:GTX Warning 90C+ amp disabled",33); e462: 7e 40 21 00 mov.b #33, r14 ;#0x0021 e466: 3f 40 7b e1 mov #-7813, r15 ;#0xe17b e46a: b0 12 ce e9 call #0xe9ce e46e: 0b 4f mov r15, r11 P2OUT &= ~TX_EN; e470: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 CCXX_SPI_WRREG(CCxxx0_PATABLE, power); //restore power but remove tx enable e474: 4e 45 mov.b r5, r14 e476: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e47a: b0 12 b6 ea call #0xeab6 P2DIR &= ~TX_EN; //change TX_ENABLE to an input to protect amplifier e47e: f2 c2 2a 00 bic.b #8, &0x002a ;r2 As==11 P2OUT |= TX_EN; amp_tsample = TX_STRING("GND:GTX Temp below 70C power restored",37); P2OUT &= ~TX_EN; } } if(loop == 0) e482: 47 93 tst.b r7 e484: 83 23 jnz $-248 ;abs 0xe38c LPM3; e486: 32 d0 d0 00 bis #208, r2 ;#0x00d0 e48a: 80 3f jmp $-254 ;abs 0xe38c P2OUT &= ~TX_EN; CCXX_SPI_WRREG(CCxxx0_PATABLE, power); //restore power but remove tx enable P2DIR &= ~TX_EN; //change TX_ENABLE to an input to protect amplifier } } else if(amp_tsample < 250) //amp is over 80 degrees!! e48c: 3b 90 fa 00 cmp #250, r11 ;#0x00fa e490: 15 2c jc $+44 ;abs 0xe4bc { if(tmpflag < 2) e492: 29 93 cmp #2, r9 ;r3 As==10 e494: f6 2f jc $-18 ;abs 0xe482 { tmpflag = 2; e496: 29 43 mov #2, r9 ;r3 As==10 CCXX_SPI_WRREG(CCxxx0_PATABLE, 96); //set output power to 0dbm e498: 7e 40 60 00 mov.b #96, r14 ;#0x0060 e49c: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e4a0: b0 12 b6 ea call #0xeab6 P2OUT |= TX_EN; e4a4: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING("GND:GTX Warning 80C+ TX power halved!",37); e4a8: 7e 40 25 00 mov.b #37, r14 ;#0x0025 e4ac: 3f 40 9d e1 mov #-7779, r15 ;#0xe19d e4b0: b0 12 ce e9 call #0xe9ce e4b4: 0b 4f mov r15, r11 P2DIR |= TX_EN; //restore TX_ENABLE tmpflag = 0; CCXX_SPI_WRREG(CCxxx0_PATABLE, power); //restore power P2OUT |= TX_EN; amp_tsample = TX_STRING("GND:GTX Temp below 70C power restored",37); P2OUT &= ~TX_EN; e4b6: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 e4ba: e3 3f jmp $-56 ;abs 0xe482 P2OUT |= TX_EN; amp_tsample = TX_STRING("GND:GTX Warning 80C+ TX power halved!",37); P2OUT &= ~TX_EN; } } else if(amp_tsample < 313) //amp is over 70 degrees!! e4bc: 3b 90 39 01 cmp #313, r11 ;#0x0139 e4c0: 0a 2c jc $+22 ;abs 0xe4d6 { if(tmpflag < 1) e4c2: 09 93 tst r9 e4c4: de 23 jnz $-66 ;abs 0xe482 { tmpflag = 1; e4c6: 19 43 mov #1, r9 ;r3 As==01 P2OUT |= TX_EN; e4c8: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING("GND:GTX Warning 70C+!",21); e4cc: 7e 40 15 00 mov.b #21, r14 ;#0x0015 e4d0: 3f 40 c3 e1 mov #-7741, r15 ;#0xe1c3 P2OUT &= ~TX_EN; e4d4: ed 3f jmp $-36 ;abs 0xe4b0 } } else //amp is looking better, restore power { if(tmpflag > 0) e4d6: 09 93 tst r9 e4d8: d4 27 jz $-86 ;abs 0xe482 { P2DIR |= TX_EN; //restore TX_ENABLE e4da: f2 d2 2a 00 bis.b #8, &0x002a ;r2 As==11 tmpflag = 0; e4de: 09 43 clr r9 CCXX_SPI_WRREG(CCxxx0_PATABLE, power); //restore power e4e0: 4e 45 mov.b r5, r14 e4e2: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e4e6: b0 12 b6 ea call #0xeab6 P2OUT |= TX_EN; e4ea: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING("GND:GTX Temp below 70C power restored",37); e4ee: 7e 40 25 00 mov.b #37, r14 ;#0x0025 e4f2: 3f 40 d9 e1 mov #-7719, r15 ;#0xe1d9 e4f6: dc 3f jmp $-70 ;abs 0xe4b0 power = length; CCXX_SPI_WRREG(CCxxx0_PATABLE, power); length = snprintf(interchip,63,"\e[32mGND:%s power is now %d\e[30m",CALLSIGN,power); } else length = snprintf(interchip,63,"\e[32mGND:%s power is (%d/195)\e[30m",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_PATABLE)); e4f8: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e4fc: b0 12 5a ea call #0xea5a e500: 7f f3 and.b #-1, r15 ;r3 As==11 e502: 0f 12 push r15 e504: 30 12 4a e1 push #-7862 ;#0xe14a e508: 30 12 ff e1 push #-7681 ;#0xe1ff e50c: 87 3f jmp $-240 ;abs 0xe41c P2OUT |= TX_EN; amp_tsample = TX_STRING(interchip,length); P2OUT &= ~TX_EN; } else if(strstr( interchip, "chan" ) != NULL) //interval is in the string! e50e: 3e 40 22 e2 mov #-7646, r14 ;#0xe222 e512: 0f 44 mov r4, r15 e514: b0 12 d6 f4 call #0xf4d6 e518: 0f 93 tst r15 e51a: 48 24 jz $+146 ;abs 0xe5ac { i = atoi(strchr(interchip, '=' )+1); //The new interval should follow the equals sign e51c: 3e 40 3d 00 mov #61, r14 ;#0x003d e520: 0f 44 mov r4, r15 e522: b0 12 68 f4 call #0xf468 e526: 1f 53 inc r15 e528: b0 12 08 ed call #0xed08 e52c: 0a 4f mov r15, r10 if(i > 0) e52e: 0f 93 tst r15 e530: 22 24 jz $+70 ;abs 0xe576 P2OUT |= TX_EN; TX_STRING(interchip,length); P2OUT &= ~TX_EN;*/ length = snprintf(interchip,63,"\e[32mGND:%s chan was %d now %d\e[30m",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_CHANNR),i); e532: 0f 12 push r15 e534: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e538: b0 12 5a ea call #0xea5a e53c: 7f f3 and.b #-1, r15 ;r3 As==11 e53e: 0f 12 push r15 e540: 30 12 4a e1 push #-7862 ;#0xe14a e544: 30 12 27 e2 push #-7641 ;#0xe227 e548: 30 12 3f 00 push #63 ;#0x003f e54c: 04 12 push r4 e54e: b0 12 dc ed call #0xeddc chan=i; e552: 46 4a mov.b r10, r6 P2OUT |= TX_EN; e554: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING(interchip,length); e558: 4e 4f mov.b r15, r14 e55a: 0f 44 mov r4, r15 e55c: b0 12 ce e9 call #0xe9ce e560: 0b 4f mov r15, r11 P2OUT &= ~TX_EN; e562: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 CCXX_SPI_WRREG(CCxxx0_CHANNR, i); e566: 4e 4a mov.b r10, r14 e568: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e56c: b0 12 b6 ea call #0xeab6 e570: 31 50 0c 00 add #12, r1 ;#0x000c e574: 63 3f jmp $-312 ;abs 0xe43c } else { length = snprintf(interchip,63,"\e[32mGND:%s chan is %d\e[30m",CALLSIGN,(unsigned char)CCXX_SPI_RDREG(CCxxx0_CHANNR)); e576: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e57a: b0 12 5a ea call #0xea5a e57e: 7f f3 and.b #-1, r15 ;r3 As==11 e580: 0f 12 push r15 e582: 30 12 4a e1 push #-7862 ;#0xe14a e586: 30 12 4b e2 push #-7605 ;#0xe24b e58a: 30 12 3f 00 push #63 ;#0x003f e58e: 04 12 push r4 e590: b0 12 dc ed call #0xeddc } else { //memset(interchip, 0, 64); length = snprintf(interchip,63,"\e[32mGND:%s rate is %d\e[30m",CALLSIGN,rate); P2OUT |= TX_EN; e594: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING(interchip,length); e598: 4e 4f mov.b r15, r14 e59a: 0f 44 mov r4, r15 e59c: b0 12 ce e9 call #0xe9ce e5a0: 0b 4f mov r15, r11 P2OUT &= ~TX_EN; e5a2: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 e5a6: 31 50 0a 00 add #10, r1 ;#0x000a e5aa: 48 3f jmp $-366 ;abs 0xe43c amp_tsample = TX_STRING(interchip,length); P2OUT &= ~TX_EN; } } else if(strstr( interchip, "temp" ) != NULL) //interval is in the string! e5ac: 3e 40 67 e2 mov #-7577, r14 ;#0xe267 e5b0: 0f 44 mov r4, r15 e5b2: b0 12 d6 f4 call #0xf4d6 e5b6: 0f 93 tst r15 e5b8: 27 24 jz $+80 ;abs 0xe608 { tsample = sample_adc(INCH_TEMP); e5ba: 3f 40 00 a0 mov #-24576,r15 ;#0xa000 e5be: b0 12 06 e1 call #0xe106 //amp_tsample = sample_adc(INCH_A1); //temp = ((tsample/1023.0)*1.5 - 0.949) * 179; //tipart = (temp)*100; //integer part, not imaginary part temp = (tsample*21/8) - (52660/31); e5c2: 0a 4f mov r15, r10 e5c4: 3c 40 15 00 mov #21, r12 ;#0x0015 e5c8: b0 12 54 f5 call #0xf554 e5cc: 12 c3 clrc e5ce: 0e 10 rrc r14 e5d0: 0e 11 rra r14 e5d2: 0e 11 rra r14 e5d4: 3e 50 5e f9 add #-1698, r14 ;#0xf95e //temp = (tsample*21/8) - 1699; length = snprintf(interchip,63,"\e[32mGND:%s Chip %d,%d - Amp %d\e[30m",CALLSIGN,temp,tsample,amp_tsample); e5d8: 0b 12 push r11 e5da: 0f 12 push r15 e5dc: 0e 12 push r14 e5de: 30 12 4a e1 push #-7862 ;#0xe14a e5e2: 30 12 6c e2 push #-7572 ;#0xe26c e5e6: 30 12 3f 00 push #63 ;#0x003f e5ea: 04 12 push r4 e5ec: b0 12 dc ed call #0xeddc P2OUT |= TX_EN; e5f0: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING(interchip,length); e5f4: 4e 4f mov.b r15, r14 e5f6: 0f 44 mov r4, r15 e5f8: b0 12 ce e9 call #0xe9ce e5fc: 0b 4f mov r15, r11 P2OUT &= ~TX_EN; e5fe: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 e602: 31 50 0e 00 add #14, r1 ;#0x000e e606: 1a 3f jmp $-458 ;abs 0xe43c } else if(strstr( interchip, "rate" ) != NULL) //interval is in the string! e608: 3e 40 91 e2 mov #-7535, r14 ;#0xe291 e60c: 0f 44 mov r4, r15 e60e: b0 12 d6 f4 call #0xf4d6 e612: 0f 93 tst r15 e614: 47 24 jz $+144 ;abs 0xe6a4 { i = atoi(strchr(interchip, '=' )+1); //The new interval should follow the equals sign e616: 3e 40 3d 00 mov #61, r14 ;#0x003d e61a: 0f 44 mov r4, r15 e61c: b0 12 68 f4 call #0xf468 e620: 1f 53 inc r15 e622: b0 12 08 ed call #0xed08 e626: 0a 4f mov r15, r10 if(i == 12 || i == 384 || i == 2500) e628: 3f 90 0c 00 cmp #12, r15 ;#0x000c e62c: 0c 24 jz $+26 ;abs 0xe646 e62e: 3f 90 80 01 cmp #384, r15 ;#0x0180 e632: 09 24 jz $+20 ;abs 0xe646 e634: 3f 90 c4 09 cmp #2500, r15 ;#0x09c4 e638: 06 24 jz $+14 ;abs 0xe646 }while(i != 1); } else { //memset(interchip, 0, 64); length = snprintf(interchip,63,"\e[32mGND:%s rate is %d\e[30m",CALLSIGN,rate); e63a: 08 12 push r8 e63c: 30 12 4a e1 push #-7862 ;#0xe14a e640: 30 12 96 e2 push #-7530 ;#0xe296 e644: a2 3f jmp $-186 ;abs 0xe58a else if(strstr( interchip, "rate" ) != NULL) //interval is in the string! { i = atoi(strchr(interchip, '=' )+1); //The new interval should follow the equals sign if(i == 12 || i == 384 || i == 2500) { rate=i; e646: 08 4a mov r10, r8 length = snprintf(interchip,63,"\e[32mGND:%s rate is now %d\e[30m",CALLSIGN,i); e648: 0a 12 push r10 e64a: 30 12 4a e1 push #-7862 ;#0xe14a e64e: 30 12 b2 e2 push #-7502 ;#0xe2b2 e652: 30 12 3f 00 push #63 ;#0x003f e656: 04 12 push r4 e658: b0 12 dc ed call #0xeddc P2OUT |= TX_EN; e65c: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING(interchip,length); e660: 4e 4f mov.b r15, r14 e662: 0f 44 mov r4, r15 e664: b0 12 ce e9 call #0xe9ce e668: 0b 4f mov r15, r11 P2OUT &= ~TX_EN; e66a: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 CCXX_SPI_STROBE(CCxxx0_SRES); //reset chip e66e: 7f 40 30 00 mov.b #48, r15 ;#0x0030 e672: b0 12 24 ea call #0xea24 //delay(0xFFF); CCXX_WRITE_SPI_RF_SETTINGS(i); e676: 0f 4a mov r10, r15 e678: b0 12 16 e7 call #0xe716 CCXX_SPI_WRREG(CCxxx0_CHANNR, chan); // Channel number. e67c: 4e 46 mov.b r6, r14 e67e: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e682: b0 12 b6 ea call #0xeab6 CCXX_SPI_STROBE(CCxxx0_SIDLE); //flush the buffer, all bytes sent e686: 7f 40 36 00 mov.b #54, r15 ;#0x0036 e68a: b0 12 24 ea call #0xea24 do{ e68e: 31 50 0a 00 add #10, r1 ;#0x000a i = CCXX_SPI_RDREG(CCxxx0_MARCSTATE);//wait for IDLE e692: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e696: b0 12 5a ea call #0xea5a e69a: 4a 4f mov.b r15, r10 e69c: 8a 11 sxt r10 }while(i != 1); e69e: 1a 93 cmp #1, r10 ;r3 As==01 e6a0: f8 23 jnz $-14 ;abs 0xe692 e6a2: cc 3e jmp $-614 ;abs 0xe43c P2OUT &= ~TX_EN; } } else { P2OUT |= TX_EN; e6a4: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING("GND:GTX pong!",13); e6a8: 7e 40 0d 00 mov.b #13, r14 ;#0x000d e6ac: 3f 40 d2 e2 mov #-7470, r15 ;#0xe2d2 e6b0: c0 3e jmp $-638 ;abs 0xe432 if(!memcmp(CALLSIGN,interchip,3)) { P3OUT |= LED_GRN; if(strstr( interchip, "reset" ) != NULL) { WDTCTL = WDTCNTCL|WDTPW; e6b2: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 e6b6: 20 01 while(1); //wait for timeout e6b8: ff 3f jmp $+0 ;abs 0xe6b8 P3OUT &= ~LED_GRN; } else { //pass the string onwards! P2OUT |= TX_EN; e6ba: f2 d2 29 00 bis.b #8, &0x0029 ;r2 As==11 amp_tsample = TX_STRING(interchip,length-1); e6be: 7a 53 add.b #-1, r10 ;r3 As==11 e6c0: 4e 4a mov.b r10, r14 e6c2: 0f 44 mov r4, r15 e6c4: b0 12 ce e9 call #0xe9ce e6c8: 0b 4f mov r15, r11 P2OUT &= ~TX_EN; e6ca: f2 c2 29 00 bic.b #8, &0x0029 ;r2 As==11 e6ce: b9 3e jmp $-652 ;abs 0xe442 CCXX_WRITE_SPI_RF_SETTINGS(12); CCXX_SPI_WRREG(CCxxx0_CHANNR, P2_CHANNR); // Channel number. } else { chan = CCXX_SPI_RDREG(CCxxx0_MDMCFG4); e6d0: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e6d4: b0 12 5a ea call #0xea5a if(chan == 0xF5) e6d8: 7f 90 f5 ff cmp.b #-11, r15 ;#0xfff5 e6dc: 09 24 jz $+20 ;abs 0xe6f0 rate = 12; else if(chan == 0xF6) e6de: 7f 90 f6 ff cmp.b #-10, r15 ;#0xfff6 e6e2: 12 24 jz $+38 ;abs 0xe708 rate = 24; else if(chan == 0xCA) e6e4: 7f 90 ca ff cmp.b #-54, r15 ;#0xffca e6e8: 0c 24 jz $+26 ;abs 0xe702 rate = 384; else if(chan == 0x2D) e6ea: 7f 90 2d 00 cmp.b #45, r15 ;#0x002d e6ee: 06 24 jz $+14 ;abs 0xe6fc rate = 2500; chan = CCXX_SPI_RDREG(CCxxx0_CHANNR); e6f0: 7f 40 0a 00 mov.b #10, r15 ;#0x000a e6f4: b0 12 5a ea call #0xea5a e6f8: 46 4f mov.b r15, r6 e6fa: 2b 3e jmp $-936 ;abs 0xe352 else if(chan == 0xF6) rate = 24; else if(chan == 0xCA) rate = 384; else if(chan == 0x2D) rate = 2500; e6fc: 38 40 c4 09 mov #2500, r8 ;#0x09c4 e700: f7 3f jmp $-16 ;abs 0xe6f0 if(chan == 0xF5) rate = 12; else if(chan == 0xF6) rate = 24; else if(chan == 0xCA) rate = 384; e702: 38 40 80 01 mov #384, r8 ;#0x0180 e706: f4 3f jmp $-22 ;abs 0xe6f0 { chan = CCXX_SPI_RDREG(CCxxx0_MDMCFG4); if(chan == 0xF5) rate = 12; else if(chan == 0xF6) rate = 24; e708: 38 40 18 00 mov #24, r8 ;#0x0018 e70c: f1 3f jmp $-28 ;abs 0xe6f0 } } if(loop == 0) LPM3; } } e70e: 31 50 40 00 add #64, r1 ;#0x0040 e712: 30 40 94 f5 br #0xf594 0000e716 : void CCXX_WRITE_SPI_RF_SETTINGS(int datarate) { e716: 0b 12 push r11 e718: 0b 4f mov r15, r11 // Write register settings CCXX_SPI_WRREG(CCxxx0_IOCFG0, P2_IOCFG0); // GDO0 output pin config. e71a: 7e 40 06 00 mov.b #6, r14 ;#0x0006 e71e: 6f 43 mov.b #2, r15 ;r3 As==10 e720: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_PKTLEN, P2_PKTLEN); // Packet length. e724: 7e 43 mov.b #-1, r14 ;r3 As==11 e726: 7f 40 06 00 mov.b #6, r15 ;#0x0006 e72a: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_PATABLE, P2_PATABLE); // GDO0 output pin config. e72e: 7e 40 c3 ff mov.b #-61, r14 ;#0xffc3 e732: 7f 40 3e 00 mov.b #62, r15 ;#0x003e e736: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_PKTCTRL0, P2_PKTCTRL0); // Packet automation control. e73a: 7e 40 05 00 mov.b #5, r14 ;#0x0005 e73e: 7f 42 mov.b #8, r15 ;r2 As==11 e740: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_ADDR, P2_ADDR); // Device address. e744: 5e 43 mov.b #1, r14 ;r3 As==01 e746: 7f 40 09 00 mov.b #9, r15 ;#0x0009 e74a: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FSCTRL0, P2_FSCTRL0); // Freq synthesizer control. e74e: 4e 43 clr.b r14 e750: 7f 40 0c 00 mov.b #12, r15 ;#0x000c e754: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FREQ2, P2_FREQ2); // Freq control word, high byte e758: 7e 40 10 00 mov.b #16, r14 ;#0x0010 e75c: 7f 40 0d 00 mov.b #13, r15 ;#0x000d e760: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FREQ1, P2_FREQ1); // Freq control word, mid byte. e764: 7e 40 27 00 mov.b #39, r14 ;#0x0027 e768: 7f 40 0e 00 mov.b #14, r15 ;#0x000e e76c: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FREQ0, P2_FREQ0); // Freq control word, low byte. e770: 7e 40 62 00 mov.b #98, r14 ;#0x0062 e774: 7f 40 0f 00 mov.b #15, r15 ;#0x000f e778: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG2, P2_MDMCFG2); // Modem configuration. e77c: 7e 40 13 00 mov.b #19, r14 ;#0x0013 e780: 7f 40 12 00 mov.b #18, r15 ;#0x0012 e784: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG1, P2_MDMCFG1); // Modem configuration. e788: 7e 40 22 00 mov.b #34, r14 ;#0x0022 e78c: 7f 40 13 00 mov.b #19, r15 ;#0x0013 e790: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG0, P2_MDMCFG0); // Modem configuration. e794: 7e 40 f8 ff mov.b #-8, r14 ;#0xfff8 e798: 7f 40 14 00 mov.b #20, r15 ;#0x0014 e79c: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MCSM1 , P2_MCSM1 ); //MainRadio Cntrl State Machine e7a0: 4e 43 clr.b r14 e7a2: 7f 40 17 00 mov.b #23, r15 ;#0x0017 e7a6: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MCSM0 , P2_MCSM0 ); //MainRadio Cntrl State Machine e7aa: 7e 40 18 00 mov.b #24, r14 ;#0x0018 e7ae: 7f 40 18 00 mov.b #24, r15 ;#0x0018 e7b2: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FREND0, P2_FREND0); // Front end RX configuration. e7b6: 7e 40 10 00 mov.b #16, r14 ;#0x0010 e7ba: 7f 40 22 00 mov.b #34, r15 ;#0x0022 e7be: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FSCAL2, P2_FSCAL2); // Frequency synthesizer cal. e7c2: 7e 40 2a 00 mov.b #42, r14 ;#0x002a e7c6: 7f 40 24 00 mov.b #36, r15 ;#0x0024 e7ca: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FSCAL1, P2_FSCAL1); // Frequency synthesizer cal. e7ce: 4e 43 clr.b r14 e7d0: 7f 40 25 00 mov.b #37, r15 ;#0x0025 e7d4: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FSCAL0, P2_FSCAL0); // Frequency synthesizer cal. e7d8: 7e 40 1f 00 mov.b #31, r14 ;#0x001f e7dc: 7f 40 26 00 mov.b #38, r15 ;#0x0026 e7e0: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FSTEST, P2_FSTEST); // Frequency synthesizer cal. e7e4: 7e 40 59 00 mov.b #89, r14 ;#0x0059 e7e8: 7f 40 29 00 mov.b #41, r15 ;#0x0029 e7ec: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_TEST0, P2_TEST0); // Various test settings. e7f0: 7e 40 0b 00 mov.b #11, r14 ;#0x000b e7f4: 7f 40 2e 00 mov.b #46, r15 ;#0x002e e7f8: b0 12 b6 ea call #0xeab6 if(datarate == 12) e7fc: 3b 90 0c 00 cmp #12, r11 ;#0x000c e800: b7 24 jz $+368 ;abs 0xe970 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_1200); // Various test settings. } else if(datarate == 384) e802: 3b 90 80 01 cmp #384, r11 ;#0x0180 e806: 5d 24 jz $+188 ;abs 0xe8c2 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_38k4); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_38k4); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_38k4); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_38k4); // Various test settings. } else if(datarate == 2500) e808: 3b 90 c4 09 cmp #2500, r11 ;#0x09c4 e80c: de 20 jnz $+446 ;abs 0xe9ca { CCXX_SPI_WRREG(CCxxx0_FSCTRL1, FSCTRL1_250k); // Freq synthesizer control. e80e: 7e 40 0c 00 mov.b #12, r14 ;#0x000c e812: 7f 40 0b 00 mov.b #11, r15 ;#0x000b e816: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG4, MDMCFG4_250k); // Modem configuration. e81a: 7e 40 2d 00 mov.b #45, r14 ;#0x002d e81e: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e822: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG3, MDMCFG3_250k); // Modem configuration. e826: 7e 40 3b 00 mov.b #59, r14 ;#0x003b e82a: 7f 40 11 00 mov.b #17, r15 ;#0x0011 e82e: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_DEVIATN, DEVIATN_250k); // Modem dev (when FSK mod en e832: 7e 40 62 00 mov.b #98, r14 ;#0x0062 e836: 7f 40 15 00 mov.b #21, r15 ;#0x0015 e83a: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FREND1, FREND1_250k); // Front end RX configuration. e83e: 7e 40 b6 ff mov.b #-74, r14 ;#0xffb6 e842: 7f 40 21 00 mov.b #33, r15 ;#0x0021 e846: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FOCCFG, FOCCFG_250k); // Freq offset compensation e84a: 7e 40 1d 00 mov.b #29, r14 ;#0x001d e84e: 7f 40 19 00 mov.b #25, r15 ;#0x0019 e852: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_BSCFG, BSCFG_250k); // bit sync config e856: 7e 40 1c 00 mov.b #28, r14 ;#0x001c e85a: 7f 40 1a 00 mov.b #26, r15 ;#0x001a e85e: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_AGCCTRL2, AGCCTRL2_250k); // AGC control e862: 7e 40 c7 ff mov.b #-57, r14 ;#0xffc7 e866: 7f 40 1b 00 mov.b #27, r15 ;#0x001b e86a: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_AGCCTRL1, AGCCTRL1_250k); // AGC control e86e: 4e 43 clr.b r14 e870: 7f 40 1c 00 mov.b #28, r15 ;#0x001c e874: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_AGCCTRL0, AGCCTRL0_250k); // AGC control e878: 7e 40 b0 ff mov.b #-80, r14 ;#0xffb0 e87c: 7f 40 1d 00 mov.b #29, r15 ;#0x001d e880: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_250k); // Frequency synthesizer cal. e884: 7e 40 ea ff mov.b #-22, r14 ;#0xffea e888: 7f 40 23 00 mov.b #35, r15 ;#0x0023 e88c: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_250k); // Various test settings. e890: 7e 40 88 ff mov.b #-120, r14 ;#0xff88 e894: 7f 40 2c 00 mov.b #44, r15 ;#0x002c e898: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_250k); // Various test settings. e89c: 7e 40 31 00 mov.b #49, r14 ;#0x0031 e8a0: 7f 40 2d 00 mov.b #45, r15 ;#0x002d e8a4: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_250k); // Various test settings. e8a8: 7e 40 88 ff mov.b #-120, r14 ;#0xff88 e8ac: 7f 40 2c 00 mov.b #44, r15 ;#0x002c e8b0: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_250k); // Various test settings. e8b4: 7e 40 07 00 mov.b #7, r14 ;#0x0007 e8b8: 7f 40 03 00 mov.b #3, r15 ;#0x0003 e8bc: b0 12 b6 ea call #0xeab6 e8c0: 84 3c jmp $+266 ;abs 0xe9ca CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_1200); // Various test settings. } else if(datarate == 384) { CCXX_SPI_WRREG(CCxxx0_FSCTRL1, FSCTRL1_38k4); // Freq synthesizer control. e8c2: 7e 40 06 00 mov.b #6, r14 ;#0x0006 e8c6: 7f 40 0b 00 mov.b #11, r15 ;#0x000b e8ca: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG4, MDMCFG4_38k4); // Modem configuration. e8ce: 7e 40 ca ff mov.b #-54, r14 ;#0xffca e8d2: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e8d6: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG3, MDMCFG3_38k4); // Modem configuration. e8da: 7e 40 83 ff mov.b #-125, r14 ;#0xff83 e8de: 7f 40 11 00 mov.b #17, r15 ;#0x0011 e8e2: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_DEVIATN, DEVIATN_38k4); // Modem dev (when FSK mod en e8e6: 7e 40 34 00 mov.b #52, r14 ;#0x0034 e8ea: 7f 40 15 00 mov.b #21, r15 ;#0x0015 e8ee: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FREND1, FREND1_38k4); // Front end RX configuration. e8f2: 7e 40 56 00 mov.b #86, r14 ;#0x0056 e8f6: 7f 40 21 00 mov.b #33, r15 ;#0x0021 e8fa: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FOCCFG, FOCCFG_38k4); // Freq offset compensation e8fe: 7e 40 16 00 mov.b #22, r14 ;#0x0016 e902: 7f 40 19 00 mov.b #25, r15 ;#0x0019 e906: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_BSCFG, BSCFG_38k4); // bit sync config e90a: 7e 40 6c 00 mov.b #108, r14 ;#0x006c e90e: 7f 40 1a 00 mov.b #26, r15 ;#0x001a e912: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_AGCCTRL2, AGCCTRL2_38k4); // AGC control e916: 7e 40 43 00 mov.b #67, r14 ;#0x0043 e91a: 7f 40 1b 00 mov.b #27, r15 ;#0x001b e91e: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_AGCCTRL1, AGCCTRL1_38k4); // AGC control e922: 7e 40 40 00 mov.b #64, r14 ;#0x0040 e926: 7f 40 1c 00 mov.b #28, r15 ;#0x001c e92a: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_AGCCTRL0, AGCCTRL0_38k4); // AGC control e92e: 7e 40 91 ff mov.b #-111, r14 ;#0xff91 e932: 7f 40 1d 00 mov.b #29, r15 ;#0x001d e936: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_38k4); // Frequency synthesizer cal. e93a: 7e 40 e9 ff mov.b #-23, r14 ;#0xffe9 e93e: 7f 40 23 00 mov.b #35, r15 ;#0x0023 e942: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_38k4); // Various test settings. e946: 7e 40 81 ff mov.b #-127, r14 ;#0xff81 e94a: 7f 40 2c 00 mov.b #44, r15 ;#0x002c e94e: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_38k4); // Various test settings. e952: 7e 40 35 00 mov.b #53, r14 ;#0x0035 e956: 7f 40 2d 00 mov.b #45, r15 ;#0x002d e95a: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_38k4); // Various test settings. e95e: 7e 40 81 ff mov.b #-127, r14 ;#0xff81 e962: 7f 40 2c 00 mov.b #44, r15 ;#0x002c e966: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_38k4); // Various test settings. e96a: 7e 40 47 00 mov.b #71, r14 ;#0x0047 e96e: a4 3f jmp $-182 ;abs 0xe8b8 CCXX_SPI_WRREG(CCxxx0_TEST0, P2_TEST0); // Various test settings. if(datarate == 12) { CCXX_SPI_WRREG(CCxxx0_FSCTRL1, FSCTRL1_1200); // Freq synthesizer control. e970: 7e 40 06 00 mov.b #6, r14 ;#0x0006 e974: 7f 40 0b 00 mov.b #11, r15 ;#0x000b e978: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG4, MDMCFG4_1200); // Modem configuration. e97c: 7e 40 f5 ff mov.b #-11, r14 ;#0xfff5 e980: 7f 40 10 00 mov.b #16, r15 ;#0x0010 e984: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_MDMCFG3, MDMCFG3_1200); // Modem configuration. e988: 7e 40 83 ff mov.b #-125, r14 ;#0xff83 e98c: 7f 40 11 00 mov.b #17, r15 ;#0x0011 e990: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_DEVIATN, DEVIATN_1200); // Modem dev (when FSK mod en e994: 7e 40 15 00 mov.b #21, r14 ;#0x0015 e998: 7f 40 15 00 mov.b #21, r15 ;#0x0015 e99c: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FREND1, FREND1_1200); // Front end RX configuration. e9a0: 7e 40 56 00 mov.b #86, r14 ;#0x0056 e9a4: 7f 40 21 00 mov.b #33, r15 ;#0x0021 e9a8: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_FOCCFG, FOCCFG_1200); // Freq offset compensation e9ac: 7e 40 16 00 mov.b #22, r14 ;#0x0016 e9b0: 7f 40 19 00 mov.b #25, r15 ;#0x0019 e9b4: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_BSCFG, BSCFG_1200); // bit sync config e9b8: 7e 40 6c 00 mov.b #108, r14 ;#0x006c e9bc: 7f 40 1a 00 mov.b #26, r15 ;#0x001a e9c0: b0 12 b6 ea call #0xeab6 CCXX_SPI_WRREG(CCxxx0_AGCCTRL2, AGCCTRL2_1200); // AGC control e9c4: 7e 40 03 00 mov.b #3, r14 ;#0x0003 CCXX_SPI_WRREG(CCxxx0_AGCCTRL0, AGCCTRL0_1200); // AGC control CCXX_SPI_WRREG(CCxxx0_FSCAL3, FSCAL3_1200); // Frequency synthesizer cal. CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST1, TEST1_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_1200); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_1200); // Various test settings. e9c8: a8 3f jmp $-174 ;abs 0xe91a CCXX_SPI_WRREG(CCxxx0_TEST2, TEST2_250k); // Various test settings. CCXX_SPI_WRREG(CCxxx0_FIFOTHR, FIFOTHR_250k); // Various test settings. } } e9ca: 3b 41 pop r11 e9cc: 30 41 ret 0000e9ce : /** Transmit a string of bytes. */ unsigned int TX_STRING(unsigned char *txstring, unsigned char length) { e9ce: 0b 12 push r11 e9d0: 0a 12 push r10 e9d2: 0a 4f mov r15, r10 e9d4: 4b 4e mov.b r14, r11 unsigned int amp_tsample; //length += 3; do{ //CCXX_SPI_STROBE(CCxxx0_SIDLE);//Idle CCXX_SPI_STROBE(CCxxx0_SNOP) ; //wait for Idle e9d6: 7f 40 3d 00 mov.b #61, r15 ;#0x003d e9da: b0 12 24 ea call #0xea24 }while((status & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //wait for idle e9de: f2 b0 70 00 bit.b #112, &0x020c ;#0x0070 e9e2: 0c 02 e9e4: f8 23 jnz $-14 ;abs 0xe9d6 { if(i < length) CCXX_SPI_WRREG(CCxxx0_TXFIFO, txstring[i]);//Write data to FIFO }*/ CCXX_SPI_BURST_WRREG(CCxxx0_TXFIFO_BURST, txstring, length); e9e6: 4d 4b mov.b r11, r13 e9e8: 0e 4a mov r10, r14 e9ea: 7f 40 7f 00 mov.b #127, r15 ;#0x007f e9ee: b0 12 fe ea call #0xeafe CCXX_SPI_STROBE(CCxxx0_STX); // send tx strobe and TX begins, returns to 15 or 31 when complete (depending on MCSM1) e9f2: 7f 40 35 00 mov.b #53, r15 ;#0x0035 e9f6: b0 12 24 ea call #0xea24 //Sample the temperature of the chip amp_tsample = sample_adc(INCH_A1); e9fa: 3f 40 00 10 mov #4096, r15 ;#0x1000 e9fe: b0 12 06 e1 call #0xe106 ea02: 0b 4f mov r15, r11 do { CCXX_SPI_STROBE(CCxxx0_SNOP) ; //(wait for 15, idle)read status byte.... ea04: 7f 40 3d 00 mov.b #61, r15 ;#0x003d ea08: b0 12 24 ea call #0xea24 if(status == 31) //fast RX mode yay ea0c: 5f 42 0c 02 mov.b &0x020c,r15 ea10: 7f 90 1f 00 cmp.b #31, r15 ;#0x001f ea14: 03 24 jz $+8 ;abs 0xea1c break; }while((status & CCxxx0_STAT_ADDR) != CCxxx0_STAT_IDLE); //(15)31 for return to TX on complete, see MCSM1 ea16: 7f f0 70 00 and.b #112, r15 ;#0x0070 ea1a: f4 23 jnz $-22 ;abs 0xea04 return amp_tsample; } ea1c: 0f 4b mov r11, r15 ea1e: 3a 41 pop r10 ea20: 3b 41 pop r11 ea22: 30 41 ret 0000ea24 : #include "hardware.h" /** Strobe a command to the CCXX */ void CCXX_SPI_STROBE(char reg) { ea24: 4e 4f mov.b r15, r14 status=0; ea26: c2 43 0c 02 mov.b #0, &0x020c ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip ea2a: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low ea2e: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 ea32: fd 23 jnz $-4 ;abs 0xea2e P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ea34: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e ea38: 1b 00 IFG2 &= ~URXIFG0; ea3a: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; ea3e: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); ea42: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 ea46: fd 27 jz $-4 ;abs 0xea42 status = U0RXBUF; ea48: d2 42 76 00 mov.b &0x0076,&0x020c ea4c: 0c 02 P3OUT |= CSn; //pull CSn high, we're done with the transfer ea4e: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode ea52: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 ea56: 1b 00 } ea58: 30 41 ret 0000ea5a : /** Read a register from the CCXX */ char CCXX_SPI_RDREG(char reg) { ea5a: 4e 4f mov.b r15, r14 char rx=0; if(reg >= 0x30) ea5c: 7f 90 30 00 cmp.b #48, r15 ;#0x0030 ea60: 1e 38 jl $+62 ;abs 0xea9e reg |= 0xC0; ea62: 7e d0 c0 ff bis.b #-64, r14 ;#0xffc0 else reg |= 0x80; status=0; ea66: c2 43 0c 02 mov.b #0, &0x020c ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip ea6a: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low ea6e: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 ea72: fd 23 jnz $-4 ;abs 0xea6e P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ea74: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e ea78: 1b 00 IFG2 &= ~URXIFG0; ea7a: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; ea7e: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); ea82: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 ea86: fd 27 jz $-4 ;abs 0xea82 status = U0RXBUF; ea88: d2 42 76 00 mov.b &0x0076,&0x020c ea8c: 0c 02 IFG2 &= ~URXIFG0; ea8e: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; ea92: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); ea96: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 ea9a: fd 27 jz $-4 ;abs 0xea96 ea9c: 03 3c jmp $+8 ;abs 0xeaa4 { char rx=0; if(reg >= 0x30) reg |= 0xC0; else reg |= 0x80; ea9e: 7e d0 80 ff bis.b #-128, r14 ;#0xff80 eaa2: e1 3f jmp $-60 ;abs 0xea66 status = U0RXBUF; IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; eaa4: 5f 42 76 00 mov.b &0x0076,r15 P3OUT |= CSn; //pull CSn high, we're done with the transfer eaa8: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode eaac: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 eab0: 1b 00 return rx; eab2: 8f 11 sxt r15 } eab4: 30 41 ret 0000eab6 : /** Write a register to the CCXX */ void CCXX_SPI_WRREG(char reg, char byte) { eab6: 4d 4f mov.b r15, r13 unsigned int dummy; status=0; eab8: c2 43 0c 02 mov.b #0, &0x020c ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip eabc: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low eac0: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 eac4: fd 23 jnz $-4 ;abs 0xeac0 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high eac6: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e eaca: 1b 00 IFG2 &= ~URXIFG0; eacc: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; ead0: c2 4d 77 00 mov.b r13, &0x0077 while (!(IFG2 & URXIFG0)); ead4: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 ead8: fd 27 jz $-4 ;abs 0xead4 status = U0RXBUF; eada: d2 42 76 00 mov.b &0x0076,&0x020c eade: 0c 02 IFG2 &= ~URXIFG0; eae0: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = byte; eae4: c2 4e 77 00 mov.b r14, &0x0077 while (!(IFG2 & URXIFG0)); eae8: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 eaec: fd 27 jz $-4 ;abs 0xeae8 dummy = U0RXBUF; eaee: 5f 42 76 00 mov.b &0x0076,r15 P3OUT |= CSn; //pull CSn high, we're done with the transfer eaf2: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode eaf6: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 eafa: 1b 00 } eafc: 30 41 ret 0000eafe : /** Write many bytes to the CCXX */ void CCXX_SPI_BURST_WRREG(char reg, char *buf, char length) { eafe: 4c 4f mov.b r15, r12 unsigned char dummy; unsigned int index; status=0; eb00: c2 43 0c 02 mov.b #0, &0x020c ;r3 As==00 P3OUT &= ~CSn; //pull CSn low to activate chip eb04: d2 c3 19 00 bic.b #1, &0x0019 ;r3 As==01 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low eb08: e2 b2 18 00 bit.b #4, &0x0018 ;r2 As==10 eb0c: fd 23 jnz $-4 ;abs 0xeb08 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high eb0e: f2 d0 0e 00 bis.b #14, &0x001b ;#0x000e eb12: 1b 00 IFG2 &= ~URXIFG0; eb14: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = reg; eb18: c2 4c 77 00 mov.b r12, &0x0077 while (!(IFG2 & URXIFG0)); eb1c: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 eb20: fd 27 jz $-4 ;abs 0xeb1c status = U0RXBUF; eb22: d2 42 76 00 mov.b &0x0076,&0x020c eb26: 0c 02 IFG2 &= ~URXIFG0; eb28: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = length; eb2c: c2 4d 77 00 mov.b r13, &0x0077 while (!(IFG2 & URXIFG0)); eb30: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 eb34: fd 27 jz $-4 ;abs 0xeb30 dummy = U0RXBUF; eb36: 5f 42 76 00 mov.b &0x0076,r15 for(index = 0; index < length; index++) eb3a: 0c 43 clr r12 eb3c: 8d 11 sxt r13 eb3e: 0c 9d cmp r13, r12 eb40: 0e 2c jc $+30 ;abs 0xeb5e { IFG2 &= ~URXIFG0; eb42: d2 c3 03 00 bic.b #1, &0x0003 ;r3 As==01 U0TXBUF = buf[index]; eb46: 0f 4e mov r14, r15 eb48: 0f 5c add r12, r15 eb4a: e2 4f 77 00 mov.b @r15, &0x0077 while (!(IFG2 & URXIFG0)); eb4e: d2 b3 03 00 bit.b #1, &0x0003 ;r3 As==01 eb52: fd 27 jz $-4 ;abs 0xeb4e dummy = U0RXBUF; eb54: 5f 42 76 00 mov.b &0x0076,r15 IFG2 &= ~URXIFG0; U0TXBUF = length; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; for(index = 0; index < length; index++) eb58: 1c 53 inc r12 eb5a: 0c 9d cmp r13, r12 eb5c: f2 2b jnc $-26 ;abs 0xeb42 U0TXBUF = buf[index]; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; } P3OUT |= CSn; //pull CSn high, we're done with the transfer eb5e: d2 d3 19 00 bis.b #1, &0x0019 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode eb62: f2 f0 f1 ff and.b #-15, &0x001b ;#0xfff1 eb66: 1b 00 } eb68: 30 41 ret 0000eb6a : /** Strobe a command to the CCXX */ void CCXX_SPI_STROBE(char reg) { status=0; eb6a: 0b 12 push r11 eb6c: 0a 12 push r10 eb6e: 09 12 push r9 eb70: 0a 4f mov r15, r10 P3OUT &= ~CSn; //pull CSn low to activate chip eb72: 4d 43 clr.b r13 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low eb74: 0b 43 clr r11 eb76: 0c 43 clr r12 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high eb78: e2 c2 22 00 bic.b #4, &0x0022 ;r2 As==10 IFG2 &= ~URXIFG0; U0TXBUF = reg; eb7c: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 eb80: 0b 24 jz $+24 ;abs 0xeb98 while (!(IFG2 & URXIFG0)); status = U0RXBUF; eb82: 1b 53 inc r11 eb84: 0c 63 adc r12 eb86: 3b 90 20 a1 cmp #-24288,r11 ;#0xa120 eb8a: 03 20 jnz $+8 ;abs 0xeb92 eb8c: 3c 90 07 00 cmp #7, r12 ;#0x0007 eb90: 40 24 jz $+130 ;abs 0xec12 eb92: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 eb96: f5 23 jnz $-20 ;abs 0xeb82 P3OUT |= CSn; //pull CSn high, we're done with the transfer P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode } eb98: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 /** eb9c: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 eba0: 20 01 Read a register from the CCXX eba2: 7e 42 mov.b #8, r14 ;r2 As==11 */ char CCXX_SPI_RDREG(char reg) { eba4: 4d 5d rla.b r13 char rx=0; eba6: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 ebaa: fd 23 jnz $-4 ;abs 0xeba6 if(reg >= 0x30) ebac: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ebb0: 4f 43 clr.b r15 ebb2: 4f 63 adc.b r15 ebb4: 4d df bis.b r15, r13 reg |= 0xC0; ebb6: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 else ebba: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 ebbe: fd 27 jz $-4 ;abs 0xebba reg |= 0x80; ebc0: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode } /** Read a register from the CCXX ebc4: 7e 53 add.b #-1, r14 ;r3 As==11 ebc6: ee 23 jnz $-34 ;abs 0xeba4 reg |= 0xC0; else reg |= 0x80; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip ebc8: 49 4d mov.b r13, r9 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low ebca: 0c 43 clr r12 ebcc: 4f 4d mov.b r13, r15 ebce: 3f 53 add #-1, r15 ;r3 As==11 ebd0: 0c 9f cmp r15, r12 ebd2: 23 2c jc $+72 ;abs 0xec1a ebd4: 0b 4f mov r15, r11 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ebd6: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ebda: 20 01 ebdc: 7e 42 mov.b #8, r14 ;r2 As==11 IFG2 &= ~URXIFG0; U0TXBUF = reg; ebde: 4d 5d rla.b r13 while (!(IFG2 & URXIFG0)); ebe0: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 ebe4: fd 23 jnz $-4 ;abs 0xebe0 status = U0RXBUF; ebe6: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ebea: 4f 43 clr.b r15 ebec: 4f 63 adc.b r15 ebee: 4d df bis.b r15, r13 ebf0: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 IFG2 &= ~URXIFG0; ebf4: e2 b2 20 00 bit.b #4, &0x0020 ;r2 As==10 ebf8: fd 27 jz $-4 ;abs 0xebf4 U0TXBUF = reg; ebfa: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 P3OUT &= ~CSn; //pull CSn low to activate chip while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ebfe: 7e 53 add.b #-1, r14 ;r3 As==11 ec00: ee 23 jnz $-34 ;abs 0xebde status = U0RXBUF; IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; ec02: 0f 4a mov r10, r15 ec04: 0f 5c add r12, r15 ec06: cf 4d 00 00 mov.b r13, 0(r15) ;0x0000(r15) reg |= 0x80; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low ec0a: 1c 53 inc r12 ec0c: 0c 9b cmp r11, r12 ec0e: e3 2b jnc $-56 ;abs 0xebd6 ec10: 04 3c jmp $+10 ;abs 0xec1a IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); status = U0RXBUF; P3OUT |= CSn; //pull CSn high, we're done with the transfer ec12: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ec16: 20 01 ec18: bc 3f jmp $-134 ;abs 0xeb92 IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); rx = U0RXBUF; P3OUT |= CSn; //pull CSn high, we're done with the transfer ec1a: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode return rx; ec1e: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 ec22: 20 01 } ec24: 4f 49 mov.b r9, r15 ec26: 8f 11 sxt r15 ec28: 39 41 pop r9 ec2a: 3a 41 pop r10 ec2c: 3b 41 pop r11 ec2e: 30 41 ret 0000ec30 : /** Write a register to the CCXX */ void CCXX_SPI_WRREG(char reg, char byte) ec30: 0b 12 push r11 ec32: 0a 12 push r10 ec34: 0a 4f mov r15, r10 { unsigned int dummy; ec36: 0c 43 clr r12 ec38: 0d 43 clr r13 status=0; P3OUT &= ~CSn; //pull CSn low to activate chip ec3a: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ec3e: 02 20 jnz $+6 ;abs 0xec44 ec40: 0f 43 clr r15 ec42: 5f 3c jmp $+192 ;abs 0xed02 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ec44: e2 d2 22 00 bis.b #4, &0x0022 ;r2 As==10 ec48: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 IFG2 &= ~URXIFG0; U0TXBUF = reg; ec4c: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ec50: 0b 24 jz $+24 ;abs 0xec68 while (!(IFG2 & URXIFG0)); status = U0RXBUF; ec52: 1c 53 inc r12 ec54: 0d 63 adc r13 ec56: 3c 90 20 a1 cmp #-24288,r12 ;#0xa120 ec5a: 03 20 jnz $+8 ;abs 0xec62 ec5c: 3d 90 07 00 cmp #7, r13 ;#0x0007 ec60: 4c 24 jz $+154 ;abs 0xecfa ec62: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ec66: f5 23 jnz $-20 ;abs 0xec52 IFG2 &= ~URXIFG0; U0TXBUF = byte; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; ec68: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ec6c: 20 01 P3OUT |= CSn; //pull CSn high, we're done with the transfer ec6e: 4d 4e mov.b r14, r13 P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode ec70: 7c 42 mov.b #8, r12 ;r2 As==11 } ec72: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ec76: fd 23 jnz $-4 ;abs 0xec72 ec78: 4f 4d mov.b r13, r15 ec7a: 4f 5f rla.b r15 ec7c: 4f 43 clr.b r15 ec7e: 4f 6f rlc.b r15 ec80: c2 df 21 00 bis.b r15, &0x0021 /** ec84: e2 c2 21 00 bic.b #4, &0x0021 ;r2 As==10 Write many bytes to the CCXX ec88: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ec8c: fd 27 jz $-4 ;abs 0xec88 */ ec8e: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 void CCXX_SPI_BURST_WRREG(char reg, char *buf, char length) ec92: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 { ec96: 4d 5d rla.b r13 U0TXBUF = byte; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; P3OUT |= CSn; //pull CSn high, we're done with the transfer P3SEL &= ~UART0_SPI_MODULES; //take the pins back out of SPI mode ec98: 7c 53 add.b #-1, r12 ;r3 As==11 ec9a: eb 23 jnz $-40 ;abs 0xec72 unsigned char dummy; unsigned int index; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip ec9c: 4b 4e mov.b r14, r11 ec9e: 0e 43 clr r14 eca0: 1b 93 cmp #1, r11 ;r3 As==01 eca2: 21 24 jz $+68 ;abs 0xece6 while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low eca4: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 eca8: 20 01 P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ecaa: 0f 4a mov r10, r15 ecac: 0f 5e add r14, r15 ecae: 6d 4f mov.b @r15, r13 ecb0: 7c 42 mov.b #8, r12 ;r2 As==11 IFG2 &= ~URXIFG0; U0TXBUF = reg; ecb2: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 ecb6: fd 23 jnz $-4 ;abs 0xecb2 while (!(IFG2 & URXIFG0)); ecb8: 4f 4d mov.b r13, r15 ecba: 4f 5f rla.b r15 ecbc: 4f 43 clr.b r15 ecbe: 4f 6f rlc.b r15 ecc0: c2 df 21 00 bis.b r15, &0x0021 status = U0RXBUF; ecc4: e2 c2 21 00 bic.b #4, &0x0021 ;r2 As==10 ecc8: e2 b3 20 00 bit.b #2, &0x0020 ;r3 As==10 eccc: fd 27 jz $-4 ;abs 0xecc8 IFG2 &= ~URXIFG0; ecce: e2 d2 21 00 bis.b #4, &0x0021 ;r2 As==10 U0TXBUF = length; ecd2: d2 c3 21 00 bic.b #1, &0x0021 ;r3 As==01 while (!(IFG2 & URXIFG0)); ecd6: 4d 5d rla.b r13 P3OUT &= ~CSn; //pull CSn low to activate chip while(P3IN & SOMI); //wait for the CCXX good signal, wait for SOMI to drop low P3SEL |= UART0_SPI_MODULES; //this will bring the clock edge high ecd8: 7c 53 add.b #-1, r12 ;r3 As==11 ecda: eb 23 jnz $-40 ;abs 0xecb2 unsigned char dummy; unsigned int index; status=0; P3OUT &= ~CSn; //pull CSn low to activate chip ecdc: 1e 53 inc r14 ecde: 0f 4b mov r11, r15 ece0: 3f 53 add #-1, r15 ;r3 As==11 ece2: 0e 9f cmp r15, r14 ece4: df 2b jnc $-64 ;abs 0xeca4 U0TXBUF = length; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; for(index = 0; index < length; index++) { ece6: e2 c2 22 00 bic.b #4, &0x0022 ;r2 As==10 IFG2 &= ~URXIFG0; ecea: f2 d0 05 00 bis.b #5, &0x0021 ;#0x0005 ecee: 21 00 U0TXBUF = buf[index]; ecf0: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 ecf4: 20 01 while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; ecf6: 1f 43 mov #1, r15 ;r3 As==01 ecf8: 04 3c jmp $+10 ;abs 0xed02 IFG2 &= ~URXIFG0; U0TXBUF = reg; while (!(IFG2 & URXIFG0)); status = U0RXBUF; IFG2 &= ~URXIFG0; ecfa: b2 40 08 5a mov #23048, &0x0120 ;#0x5a08 ecfe: 20 01 ed00: b0 3f jmp $-158 ;abs 0xec62 { IFG2 &= ~URXIFG0; U0TXBUF = buf[index]; while (!(IFG2 & URXIFG0)); dummy = U0RXBUF; } ed02: 3a 41 pop r10 ed04: 3b 41 pop r11 ed06: 30 41 ret 0000ed08 : ed08: 0b 12 push r11 ed0a: 0a 12 push r10 ed0c: 0c 4f mov r15, r12 ed0e: 0a 43 clr r10 ed10: 0b 43 clr r11 ed12: 6d 4f mov.b @r15, r13 ed14: 7d 90 20 00 cmp.b #32, r13 ;#0x0020 ed18: 49 24 jz $+148 ;abs 0xedac ed1a: 7d 90 09 00 cmp.b #9, r13 ;#0x0009 ed1e: 46 24 jz $+142 ;abs 0xedac ed20: 7d 90 0a 00 cmp.b #10, r13 ;#0x000a ed24: 43 24 jz $+136 ;abs 0xedac ed26: 7d 90 0c 00 cmp.b #12, r13 ;#0x000c ed2a: 40 24 jz $+130 ;abs 0xedac ed2c: 7d 90 0d 00 cmp.b #13, r13 ;#0x000d ed30: 3d 24 jz $+124 ;abs 0xedac ed32: 7d 90 0b 00 cmp.b #11, r13 ;#0x000b ed36: 3a 24 jz $+118 ;abs 0xedac ed38: 7d 90 2d 00 cmp.b #45, r13 ;#0x002d ed3c: 35 24 jz $+108 ;abs 0xeda8 ed3e: 7d 90 2b 00 cmp.b #43, r13 ;#0x002b ed42: 2f 24 jz $+96 ;abs 0xeda2 ed44: 4f 4d mov.b r13, r15 ed46: 8f 11 sxt r15 ed48: 0e 43 clr r14 ed4a: 3f 50 d0 ff add #-48, r15 ;#0xffd0 ed4e: 3f 90 0a 00 cmp #10, r15 ;#0x000a ed52: 01 2c jc $+4 ;abs 0xed56 ed54: 1e 43 mov #1, r14 ;r3 As==01 ed56: 0e 93 tst r14 ed58: 02 20 jnz $+6 ;abs 0xed5e ed5a: 0f 43 clr r15 ed5c: 3c 3c jmp $+122 ;abs 0xedd6 ed5e: 4f 4d mov.b r13, r15 ed60: 8f 11 sxt r15 ed62: 0b 5f add r15, r11 ed64: 3b 50 d0 ff add #-48, r11 ;#0xffd0 ed68: 1c 53 inc r12 ed6a: 6f 4c mov.b @r12, r15 ed6c: 4d 4f mov.b r15, r13 ed6e: 8f 11 sxt r15 ed70: 0e 43 clr r14 ed72: 3f 50 d0 ff add #-48, r15 ;#0xffd0 ed76: 3f 90 0a 00 cmp #10, r15 ;#0x000a ed7a: 01 2c jc $+4 ;abs 0xed7e ed7c: 1e 43 mov #1, r14 ;r3 As==01 ed7e: 0e 93 tst r14 ed80: 0a 24 jz $+22 ;abs 0xed96 ed82: 0f 4b mov r11, r15 ed84: 0f 5f rla r15 ed86: 0f 5f rla r15 ed88: 0e 4b mov r11, r14 ed8a: 0e 5e rla r14 ed8c: 0b 4f mov r15, r11 ed8e: 0b 5e add r14, r11 ed90: 0b 5e add r14, r11 ed92: 0b 5e add r14, r11 ed94: e4 3f jmp $-54 ;abs 0xed5e ed96: 0a 93 tst r10 ed98: 02 24 jz $+6 ;abs 0xed9e ed9a: 3b e3 inv r11 ed9c: 1b 53 inc r11 ed9e: 0f 4b mov r11, r15 eda0: 1a 3c jmp $+54 ;abs 0xedd6 eda2: 1c 53 inc r12 eda4: 6d 4c mov.b @r12, r13 eda6: ce 3f jmp $-98 ;abs 0xed44 eda8: 1a 43 mov #1, r10 ;r3 As==01 edaa: fb 3f jmp $-8 ;abs 0xeda2 edac: 1c 53 inc r12 edae: 6d 4c mov.b @r12, r13 edb0: 7d 90 20 00 cmp.b #32, r13 ;#0x0020 edb4: fb 27 jz $-8 ;abs 0xedac edb6: 7d 90 09 00 cmp.b #9, r13 ;#0x0009 edba: f8 27 jz $-14 ;abs 0xedac edbc: 7d 90 0a 00 cmp.b #10, r13 ;#0x000a edc0: f5 27 jz $-20 ;abs 0xedac edc2: 7d 90 0c 00 cmp.b #12, r13 ;#0x000c edc6: f2 27 jz $-26 ;abs 0xedac edc8: 7d 90 0d 00 cmp.b #13, r13 ;#0x000d edcc: ef 27 jz $-32 ;abs 0xedac edce: 7d 90 0b 00 cmp.b #11, r13 ;#0x000b edd2: ec 27 jz $-38 ;abs 0xedac edd4: b1 3f jmp $-156 ;abs 0xed38 edd6: 3a 41 pop r10 edd8: 3b 41 pop r11 edda: 30 41 ret 0000eddc : eddc: 0b 12 push r11 edde: 0a 12 push r10 ede0: 3f 40 06 00 mov #6, r15 ;#0x0006 ede4: 0f 51 add r1, r15 ede6: 2a 4f mov @r15, r10 ede8: 1b 4f 02 00 mov 2(r15), r11 ;0x0002(r15) edec: 1e 4f 04 00 mov 4(r15), r14 ;0x0004(r15) edf0: 3f 50 06 00 add #6, r15 ;#0x0006 edf4: 0c 4f mov r15, r12 edf6: 0d 4e mov r14, r13 edf8: 0e 4b mov r11, r14 edfa: 0f 4a mov r10, r15 edfc: b0 12 26 ee call #0xee26 ee00: 3a 41 pop r10 ee02: 3b 41 pop r11 ee04: 30 41 ret 0000ee06 : ee06: 0e 4f mov r15, r14 ee08: a2 93 06 02 cmp #2, &0x0206 ;r3 As==10 ee0c: 0a 28 jnc $+22 ;abs 0xee22 ee0e: 1f 42 04 02 mov &0x0204,r15 ee12: cf 4e 00 00 mov.b r14, 0(r15) ;0x0000(r15) ee16: 92 53 04 02 inc &0x0204 ee1a: b2 53 06 02 add #-1, &0x0206 ;r3 As==11 ee1e: 4f 4e mov.b r14, r15 ee20: 30 41 ret ee22: 3f 43 mov #-1, r15 ;r3 As==11 ee24: 30 41 ret 0000ee26 : ee26: 0b 12 push r11 ee28: 0a 12 push r10 ee2a: 0b 4f mov r15, r11 ee2c: 0a 4d mov r13, r10 ee2e: 82 4b 04 02 mov r11, &0x0204 ee32: 82 4e 06 02 mov r14, &0x0206 ee36: 0d 4c mov r12, r13 ee38: 0e 4a mov r10, r14 ee3a: 3f 40 06 ee mov #-4602, r15 ;#0xee06 ee3e: b0 12 b2 ee call #0xeeb2 ee42: 0b 5f add r15, r11 ee44: cb 43 00 00 mov.b #0, 0(r11) ;r3 As==00, 0x0000(r11) ee48: 3a 41 pop r10 ee4a: 3b 41 pop r11 ee4c: 30 41 ret 0000ee4e : ee4e: 0b 12 push r11 ee50: 0a 12 push r10 ee52: 0a 4f mov r15, r10 ee54: 0b 4e mov r14, r11 ee56: 0e 93 tst r14 ee58: 02 20 jnz $+6 ;abs 0xee5e ee5a: 1f 43 mov #1, r15 ;r3 As==01 ee5c: 0d 3c jmp $+28 ;abs 0xee78 ee5e: 6f 4a mov.b @r10, r15 ee60: 8f 11 sxt r15 ee62: 1a 53 inc r10 ee64: 92 12 08 02 call &0x0208 ee68: 0f 93 tst r15 ee6a: 05 38 jl $+12 ;abs 0xee76 ee6c: 92 53 02 02 inc &0x0202 ee70: 3b 53 add #-1, r11 ;r3 As==11 ee72: f5 23 jnz $-20 ;abs 0xee5e ee74: f2 3f jmp $-26 ;abs 0xee5a ee76: 3f 43 mov #-1, r15 ;r3 As==11 ee78: 3a 41 pop r10 ee7a: 3b 41 pop r11 ee7c: 30 41 ret 0000ee7e <__write_pad>: ee7e: 0b 12 push r11 ee80: 0a 12 push r10 ee82: 09 12 push r9 ee84: 49 4f mov.b r15, r9 ee86: 4b 4e mov.b r14, r11 ee88: 5e 93 cmp.b #1, r14 ;r3 As==01 ee8a: 0c 38 jl $+26 ;abs 0xeea4 ee8c: 4a 4f mov.b r15, r10 ee8e: 8a 11 sxt r10 ee90: 0f 4a mov r10, r15 ee92: 92 12 08 02 call &0x0208 ee96: 0f 93 tst r15 ee98: 07 38 jl $+16 ;abs 0xeea8 ee9a: 92 53 02 02 inc &0x0202 ee9e: 7b 53 add.b #-1, r11 ;r3 As==11 eea0: 5b 93 cmp.b #1, r11 ;r3 As==01 eea2: f6 37 jge $-18 ;abs 0xee90 eea4: 4f 49 mov.b r9, r15 eea6: 01 3c jmp $+4 ;abs 0xeeaa eea8: 3f 43 mov #-1, r15 ;r3 As==11 eeaa: 39 41 pop r9 eeac: 3a 41 pop r10 eeae: 3b 41 pop r11 eeb0: 30 41 ret 0000eeb2 : eeb2: 0b 12 push r11 eeb4: 0a 12 push r10 eeb6: 09 12 push r9 eeb8: 08 12 push r8 eeba: 07 12 push r7 eebc: 06 12 push r6 eebe: 05 12 push r5 eec0: 04 12 push r4 eec2: 31 80 3c 00 sub #60, r1 ;#0x003c eec6: 05 4d mov r13, r5 eec8: 81 43 30 00 mov #0, 48(r1) ;r3 As==00, 0x0030(r1) eecc: 81 43 32 00 mov #0, 50(r1) ;r3 As==00, 0x0032(r1) eed0: 82 43 02 02 mov #0, &0x0202 ;r3 As==00 eed4: 82 4f 08 02 mov r15, &0x0208 eed8: 06 4e mov r14, r6 eeda: 0f 46 mov r6, r15 eedc: 67 46 mov.b @r6, r7 eede: 47 93 tst.b r7 eee0: 0a 24 jz $+22 ;abs 0xeef6 eee2: 77 90 25 00 cmp.b #37, r7 ;#0x0025 eee6: 07 24 jz $+16 ;abs 0xeef6 eee8: 16 53 inc r6 eeea: 67 46 mov.b @r6, r7 eeec: 47 93 tst.b r7 eeee: 03 24 jz $+8 ;abs 0xeef6 eef0: 77 90 25 00 cmp.b #37, r7 ;#0x0025 eef4: f9 23 jnz $-12 ;abs 0xeee8 eef6: 0d 46 mov r6, r13 eef8: 0d 8f sub r15, r13 eefa: 02 24 jz $+6 ;abs 0xef00 eefc: 30 40 40 f4 br #0xf440 ef00: 47 93 tst.b r7 ef02: 02 20 jnz $+6 ;abs 0xef08 ef04: 30 40 4e f4 br #0xf44e ef08: 16 53 inc r6 ef0a: c1 43 2e 00 mov.b #0, 46(r1) ;r3 As==00, 0x002e(r1) ef0e: c1 43 35 00 mov.b #0, 53(r1) ;r3 As==00, 0x0035(r1) ef12: c1 43 2f 00 mov.b #0, 47(r1) ;r3 As==00, 0x002f(r1) ef16: 7b 43 mov.b #-1, r11 ;r3 As==11 ef18: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) ef1c: 67 46 mov.b @r6, r7 ef1e: 16 53 inc r6 ef20: 77 90 75 00 cmp.b #117, r7 ;#0x0075 ef24: 02 20 jnz $+6 ;abs 0xef2a ef26: 30 40 1a f4 br #0xf41a ef2a: 4f 47 mov.b r7, r15 ef2c: 7f d0 20 00 bis.b #32, r15 ;#0x0020 ef30: 7f 90 78 00 cmp.b #120, r15 ;#0x0078 ef34: 02 20 jnz $+6 ;abs 0xef3a ef36: 30 40 1a f4 br #0xf41a ef3a: 77 90 20 00 cmp.b #32, r7 ;#0x0020 ef3e: 02 20 jnz $+6 ;abs 0xef44 ef40: 30 40 06 f4 br #0xf406 ef44: 77 90 23 00 cmp.b #35, r7 ;#0x0023 ef48: 02 20 jnz $+6 ;abs 0xef4e ef4a: 30 40 fe f3 br #0xf3fe ef4e: 77 90 2a 00 cmp.b #42, r7 ;#0x002a ef52: 02 20 jnz $+6 ;abs 0xef58 ef54: 30 40 e2 f3 br #0xf3e2 ef58: 77 90 2d 00 cmp.b #45, r7 ;#0x002d ef5c: 02 20 jnz $+6 ;abs 0xef62 ef5e: 30 40 d2 f3 br #0xf3d2 ef62: 77 90 2b 00 cmp.b #43, r7 ;#0x002b ef66: 02 20 jnz $+6 ;abs 0xef6c ef68: 30 40 c8 f3 br #0xf3c8 ef6c: 77 90 2e 00 cmp.b #46, r7 ;#0x002e ef70: 02 20 jnz $+6 ;abs 0xef76 ef72: 30 40 62 f3 br #0xf362 ef76: 77 90 30 00 cmp.b #48, r7 ;#0x0030 ef7a: 02 20 jnz $+6 ;abs 0xef80 ef7c: 30 40 4c f3 br #0xf34c ef80: 4f 47 mov.b r7, r15 ef82: 7f 50 cf ff add.b #-49, r15 ;#0xffcf ef86: 7f 90 09 00 cmp.b #9, r15 ;#0x0009 ef8a: 1a 2c jc $+54 ;abs 0xefc0 ef8c: 0d 43 clr r13 ef8e: 0f 4d mov r13, r15 ef90: 0f 5f rla r15 ef92: 0f 5f rla r15 ef94: 0e 4d mov r13, r14 ef96: 0e 5e rla r14 ef98: 0d 4f mov r15, r13 ef9a: 0d 5e add r14, r13 ef9c: 0d 5e add r14, r13 ef9e: 0d 5e add r14, r13 efa0: 4f 47 mov.b r7, r15 efa2: 8f 11 sxt r15 efa4: 0d 5f add r15, r13 efa6: 3d 50 d0 ff add #-48, r13 ;#0xffd0 efaa: 67 46 mov.b @r6, r7 efac: 16 53 inc r6 efae: 4f 47 mov.b r7, r15 efb0: 7f 50 d0 ff add.b #-48, r15 ;#0xffd0 efb4: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a efb8: ea 2b jnc $-42 ;abs 0xef8e efba: c1 4d 2f 00 mov.b r13, 47(r1) ;0x002f(r1) efbe: b0 3f jmp $-158 ;abs 0xef20 efc0: 77 90 68 00 cmp.b #104, r7 ;#0x0068 efc4: bf 25 jz $+896 ;abs 0xf344 efc6: 77 90 6c 00 cmp.b #108, r7 ;#0x006c efca: 03 20 jnz $+8 ;abs 0xefd2 efcc: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) efd0: a5 3f jmp $-180 ;abs 0xef1c efd2: 77 90 63 00 cmp.b #99, r7 ;#0x0063 efd6: af 25 jz $+864 ;abs 0xf336 efd8: 77 90 44 00 cmp.b #68, r7 ;#0x0044 efdc: a9 25 jz $+852 ;abs 0xf330 efde: 77 90 64 00 cmp.b #100, r7 ;#0x0064 efe2: 7a 25 jz $+758 ;abs 0xf2d8 efe4: 77 90 69 00 cmp.b #105, r7 ;#0x0069 efe8: 77 25 jz $+752 ;abs 0xf2d8 efea: 77 90 4f 00 cmp.b #79, r7 ;#0x004f efee: 71 25 jz $+740 ;abs 0xf2d2 eff0: 77 90 6f 00 cmp.b #111, r7 ;#0x006f eff4: 6b 25 jz $+728 ;abs 0xf2cc eff6: 77 90 70 00 cmp.b #112, r7 ;#0x0070 effa: 59 25 jz $+692 ;abs 0xf2ae effc: 77 90 73 00 cmp.b #115, r7 ;#0x0073 f000: 1a 25 jz $+566 ;abs 0xf236 f002: 77 90 55 00 cmp.b #85, r7 ;#0x0055 f006: 14 25 jz $+554 ;abs 0xf230 f008: 77 90 75 00 cmp.b #117, r7 ;#0x0075 f00c: 0d 25 jz $+540 ;abs 0xf228 f00e: 77 90 58 00 cmp.b #88, r7 ;#0x0058 f012: 8a 24 jz $+278 ;abs 0xf128 f014: 77 90 78 00 cmp.b #120, r7 ;#0x0078 f018: 87 24 jz $+272 ;abs 0xf128 f01a: 47 93 tst.b r7 f01c: 02 20 jnz $+6 ;abs 0xf022 f01e: 30 40 4e f4 br #0xf44e f022: 81 41 2c 00 mov r1, 44(r1) ;0x002c(r1) f026: c1 47 00 00 mov.b r7, 0(r1) ;0x0000(r1) f02a: 59 43 mov.b #1, r9 ;r3 As==01 f02c: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) f030: 4b 49 mov.b r9, r11 f032: 5a 41 35 00 mov.b 53(r1), r10 ;0x0035(r1) f036: 4a 89 sub.b r9, r10 f038: 75 30 jn $+236 ;abs 0xf124 f03a: 5e 41 2a 00 mov.b 42(r1), r14 ;0x002a(r1) f03e: 4e 93 tst.b r14 f040: 6b 24 jz $+216 ;abs 0xf118 f042: 5b 53 inc.b r11 f044: 4b 5a add.b r10, r11 f046: 58 41 2e 00 mov.b 46(r1), r8 ;0x002e(r1) f04a: 78 f0 30 00 and.b #48, r8 ;#0x0030 f04e: 13 20 jnz $+40 ;abs 0xf076 f050: 5d 41 2f 00 mov.b 47(r1), r13 ;0x002f(r1) f054: 8d 11 sxt r13 f056: 4f 4b mov.b r11, r15 f058: 8f 11 sxt r15 f05a: 0d 8f sub r15, r13 f05c: 1d 93 cmp #1, r13 ;r3 As==01 f05e: 0b 38 jl $+24 ;abs 0xf076 f060: 4e 4d mov.b r13, r14 f062: 7f 40 20 00 mov.b #32, r15 ;#0x0020 f066: b0 12 7e ee call #0xee7e f06a: 0f 93 tst r15 f06c: 02 34 jge $+6 ;abs 0xf072 f06e: 30 40 4e f4 br #0xf44e f072: 5e 41 2a 00 mov.b 42(r1), r14 ;0x002a(r1) f076: 4e 93 tst.b r14 f078: 4a 20 jnz $+150 ;abs 0xf10e f07a: f1 b0 40 00 bit.b #64, 46(r1) ;#0x0040, 0x002e(r1) f07e: 2e 00 f080: 0f 24 jz $+32 ;abs 0xf0a0 f082: f1 40 30 00 mov.b #48, 40(r1) ;#0x0030, 0x0028(r1) f086: 28 00 f088: c1 47 29 00 mov.b r7, 41(r1) ;0x0029(r1) f08c: 2e 43 mov #2, r14 ;r3 As==10 f08e: 0f 41 mov r1, r15 f090: 3f 50 28 00 add #40, r15 ;#0x0028 f094: b0 12 4e ee call #0xee4e f098: 0f 93 tst r15 f09a: 02 34 jge $+6 ;abs 0xf0a0 f09c: 30 40 4e f4 br #0xf44e f0a0: 78 90 20 00 cmp.b #32, r8 ;#0x0020 f0a4: 24 24 jz $+74 ;abs 0xf0ee f0a6: 4e 4a mov.b r10, r14 f0a8: 7f 40 30 00 mov.b #48, r15 ;#0x0030 f0ac: b0 12 7e ee call #0xee7e f0b0: 0f 93 tst r15 f0b2: cd 39 jl $+924 ;abs 0xf44e f0b4: 4f 49 mov.b r9, r15 f0b6: 8f 11 sxt r15 f0b8: 0e 4f mov r15, r14 f0ba: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f0be: b0 12 4e ee call #0xee4e f0c2: 0f 93 tst r15 f0c4: c4 39 jl $+906 ;abs 0xf44e f0c6: f1 b0 10 00 bit.b #16, 46(r1) ;#0x0010, 0x002e(r1) f0ca: 2e 00 f0cc: 06 27 jz $-498 ;abs 0xeeda f0ce: 5d 41 2f 00 mov.b 47(r1), r13 ;0x002f(r1) f0d2: 8d 11 sxt r13 f0d4: 4f 4b mov.b r11, r15 f0d6: 8f 11 sxt r15 f0d8: 0d 8f sub r15, r13 f0da: 1d 93 cmp #1, r13 ;r3 As==01 f0dc: fe 3a jl $-514 ;abs 0xeeda f0de: 4e 4d mov.b r13, r14 f0e0: 7f 40 20 00 mov.b #32, r15 ;#0x0020 f0e4: b0 12 7e ee call #0xee7e f0e8: 0f 93 tst r15 f0ea: f7 36 jge $-528 ;abs 0xeeda f0ec: b0 3d jmp $+866 ;abs 0xf44e f0ee: 5d 41 2f 00 mov.b 47(r1), r13 ;0x002f(r1) f0f2: 8d 11 sxt r13 f0f4: 4f 4b mov.b r11, r15 f0f6: 8f 11 sxt r15 f0f8: 0d 8f sub r15, r13 f0fa: 1d 93 cmp #1, r13 ;r3 As==01 f0fc: d4 3b jl $-86 ;abs 0xf0a6 f0fe: 4e 4d mov.b r13, r14 f100: 7f 40 30 00 mov.b #48, r15 ;#0x0030 f104: b0 12 7e ee call #0xee7e f108: 0f 93 tst r15 f10a: cd 37 jge $-100 ;abs 0xf0a6 f10c: a0 3d jmp $+834 ;abs 0xf44e f10e: 1e 43 mov #1, r14 ;r3 As==01 f110: 0f 41 mov r1, r15 f112: 3f 50 2a 00 add #42, r15 ;#0x002a f116: be 3f jmp $-130 ;abs 0xf094 f118: f1 b0 40 00 bit.b #64, 46(r1) ;#0x0040, 0x002e(r1) f11c: 2e 00 f11e: 92 27 jz $-218 ;abs 0xf044 f120: 6b 53 incd.b r11 f122: 90 3f jmp $-222 ;abs 0xf044 f124: 4a 43 clr.b r10 f126: 89 3f jmp $-236 ;abs 0xf03a f128: f1 40 10 00 mov.b #16, 52(r1) ;#0x0010, 0x0034(r1) f12c: 34 00 f12e: f1 b2 2e 00 bit.b #8, 46(r1) ;r2 As==11, 0x002e(r1) f132: 09 24 jz $+20 ;abs 0xf146 f134: 81 93 30 00 tst 48(r1) ;0x0030(r1) f138: 03 20 jnz $+8 ;abs 0xf140 f13a: 81 93 32 00 tst 50(r1) ;0x0032(r1) f13e: 03 24 jz $+8 ;abs 0xf146 f140: f1 d0 40 00 bis.b #64, 46(r1) ;#0x0040, 0x002e(r1) f144: 2e 00 f146: c1 43 2a 00 mov.b #0, 42(r1) ;r3 As==00, 0x002a(r1) f14a: c1 4b 35 00 mov.b r11, 53(r1) ;0x0035(r1) f14e: 4b 93 tst.b r11 f150: 03 38 jl $+8 ;abs 0xf158 f152: f1 f0 df ff and.b #-33, 46(r1) ;#0xffdf, 0x002e(r1) f156: 2e 00 f158: 0f 41 mov r1, r15 f15a: 3f 50 28 00 add #40, r15 ;#0x0028 f15e: 81 4f 2c 00 mov r15, 44(r1) ;0x002c(r1) f162: 81 93 30 00 tst 48(r1) ;0x0030(r1) f166: 06 20 jnz $+14 ;abs 0xf174 f168: 81 93 32 00 tst 50(r1) ;0x0032(r1) f16c: 03 20 jnz $+8 ;abs 0xf174 f16e: c1 93 35 00 tst.b 53(r1) ;0x0035(r1) f172: 3e 24 jz $+126 ;abs 0xf1f0 f174: d1 41 34 00 mov.b 52(r1), 56(r1) ;0x0034(r1), 0x0038(r1) f178: 38 00 f17a: c1 43 39 00 mov.b #0, 57(r1) ;r3 As==00, 0x0039(r1) f17e: 81 43 3a 00 mov #0, 58(r1) ;r3 As==00, 0x003a(r1) f182: c1 43 36 00 mov.b #0, 54(r1) ;r3 As==00, 0x0036(r1) f186: 1e 41 30 00 mov 48(r1), r14 ;0x0030(r1) f18a: 1f 41 32 00 mov 50(r1), r15 ;0x0032(r1) f18e: 1e 81 38 00 sub 56(r1), r14 ;0x0038(r1) f192: 1f 71 3a 00 subc 58(r1), r15 ;0x003a(r1) f196: 02 28 jnc $+6 ;abs 0xf19c f198: d1 43 36 00 mov.b #1, 54(r1) ;r3 As==01, 0x0036(r1) f19c: 1c 41 30 00 mov 48(r1), r12 ;0x0030(r1) f1a0: 1d 41 32 00 mov 50(r1), r13 ;0x0032(r1) f1a4: 1a 41 38 00 mov 56(r1), r10 ;0x0038(r1) f1a8: 1b 41 3a 00 mov 58(r1), r11 ;0x003a(r1) f1ac: b0 12 6a f5 call #0xf56a f1b0: 44 4e mov.b r14, r4 f1b2: 7e 90 0a 00 cmp.b #10, r14 ;#0x000a f1b6: 30 2c jc $+98 ;abs 0xf218 f1b8: 74 50 30 00 add.b #48, r4 ;#0x0030 f1bc: b1 53 2c 00 add #-1, 44(r1) ;r3 As==11, 0x002c(r1) f1c0: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f1c4: cf 44 00 00 mov.b r4, 0(r15) ;0x0000(r15) f1c8: 1c 41 30 00 mov 48(r1), r12 ;0x0030(r1) f1cc: 1d 41 32 00 mov 50(r1), r13 ;0x0032(r1) f1d0: 1a 41 38 00 mov 56(r1), r10 ;0x0038(r1) f1d4: 1b 41 3a 00 mov 58(r1), r11 ;0x003a(r1) f1d8: b0 12 6a f5 call #0xf56a f1dc: 81 4c 30 00 mov r12, 48(r1) ;0x0030(r1) f1e0: 81 4d 32 00 mov r13, 50(r1) ;0x0032(r1) f1e4: c1 93 36 00 tst.b 54(r1) ;0x0036(r1) f1e8: cc 23 jnz $-102 ;abs 0xf182 f1ea: f1 92 34 00 cmp.b #8, 52(r1) ;r2 As==11, 0x0034(r1) f1ee: 06 24 jz $+14 ;abs 0xf1fc f1f0: 49 41 mov.b r1, r9 f1f2: 59 81 2c 00 sub.b 44(r1), r9 ;0x002c(r1) f1f6: 79 50 28 00 add.b #40, r9 ;#0x0028 f1fa: 1a 3f jmp $-458 ;abs 0xf030 f1fc: f1 b2 2e 00 bit.b #8, 46(r1) ;r2 As==11, 0x002e(r1) f200: f7 27 jz $-16 ;abs 0xf1f0 f202: 74 90 30 00 cmp.b #48, r4 ;#0x0030 f206: f4 27 jz $-22 ;abs 0xf1f0 f208: b1 53 2c 00 add #-1, 44(r1) ;r3 As==11, 0x002c(r1) f20c: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f210: ff 40 30 00 mov.b #48, 0(r15) ;#0x0030, 0x0000(r15) f214: 00 00 f216: ec 3f jmp $-38 ;abs 0xf1f0 f218: 74 50 57 00 add.b #87, r4 ;#0x0057 f21c: 77 90 58 00 cmp.b #88, r7 ;#0x0058 f220: cd 23 jnz $-100 ;abs 0xf1bc f222: 74 f0 df ff and.b #-33, r4 ;#0xffdf f226: ca 3f jmp $-106 ;abs 0xf1bc f228: f1 40 0a 00 mov.b #10, 52(r1) ;#0x000a, 0x0034(r1) f22c: 34 00 f22e: 8b 3f jmp $-232 ;abs 0xf146 f230: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f234: f9 3f jmp $-12 ;abs 0xf228 f236: 0f 45 mov r5, r15 f238: 25 53 incd r5 f23a: a1 4f 2c 00 mov @r15, 44(r1) ;0x002c(r1) f23e: 81 93 2c 00 tst 44(r1) ;0x002c(r1) f242: 1e 24 jz $+62 ;abs 0xf280 f244: 4b 93 tst.b r11 f246: 11 38 jl $+36 ;abs 0xf26a f248: 4f 4b mov.b r11, r15 f24a: 8f 11 sxt r15 f24c: 0d 4f mov r15, r13 f24e: 0e 43 clr r14 f250: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f254: b0 12 82 f4 call #0xf482 f258: 0f 93 tst r15 f25a: 05 24 jz $+12 ;abs 0xf266 f25c: 49 4f mov.b r15, r9 f25e: 59 81 2c 00 sub.b 44(r1), r9 ;0x002c(r1) f262: 4b 99 cmp.b r9, r11 f264: e3 36 jge $-568 ;abs 0xf02c f266: 49 4b mov.b r11, r9 f268: e1 3e jmp $-572 ;abs 0xf02c f26a: 1f 41 2c 00 mov 44(r1), r15 ;0x002c(r1) f26e: 1f 83 dec r15 f270: 1f 53 inc r15 f272: cf 93 00 00 tst.b 0(r15) ;0x0000(r15) f276: fc 23 jnz $-6 ;abs 0xf270 f278: 49 4f mov.b r15, r9 f27a: 59 81 2c 00 sub.b 44(r1), r9 ;0x002c(r1) f27e: d6 3e jmp $-594 ;abs 0xf02c f280: 81 41 2c 00 mov r1, 44(r1) ;0x002c(r1) f284: f1 40 28 00 mov.b #40, 0(r1) ;#0x0028, 0x0000(r1) f288: 00 00 f28a: f1 40 6e 00 mov.b #110, 1(r1) ;#0x006e, 0x0001(r1) f28e: 01 00 f290: f1 40 75 00 mov.b #117, 2(r1) ;#0x0075, 0x0002(r1) f294: 02 00 f296: f1 40 6c 00 mov.b #108, 3(r1) ;#0x006c, 0x0003(r1) f29a: 03 00 f29c: f1 40 6c 00 mov.b #108, 4(r1) ;#0x006c, 0x0004(r1) f2a0: 04 00 f2a2: f1 40 29 00 mov.b #41, 5(r1) ;#0x0029, 0x0005(r1) f2a6: 05 00 f2a8: c1 43 06 00 mov.b #0, 6(r1) ;r3 As==00, 0x0006(r1) f2ac: cb 3f jmp $-104 ;abs 0xf244 f2ae: 0f 45 mov r5, r15 f2b0: 25 53 incd r5 f2b2: a1 4f 30 00 mov @r15, 48(r1) ;0x0030(r1) f2b6: 81 43 32 00 mov #0, 50(r1) ;r3 As==00, 0x0032(r1) f2ba: f1 40 10 00 mov.b #16, 52(r1) ;#0x0010, 0x0034(r1) f2be: 34 00 f2c0: f1 d0 40 00 bis.b #64, 46(r1) ;#0x0040, 0x002e(r1) f2c4: 2e 00 f2c6: 77 40 78 00 mov.b #120, r7 ;#0x0078 f2ca: 3d 3f jmp $-388 ;abs 0xf146 f2cc: f1 42 34 00 mov.b #8, 52(r1) ;r2 As==11, 0x0034(r1) f2d0: 3a 3f jmp $-394 ;abs 0xf146 f2d2: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f2d6: fa 3f jmp $-10 ;abs 0xf2cc f2d8: d1 b3 2e 00 bit.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f2dc: 19 24 jz $+52 ;abs 0xf310 f2de: 0f 45 mov r5, r15 f2e0: 25 52 add #4, r5 ;r2 As==10 f2e2: b1 4f 30 00 mov @r15+, 48(r1) ;0x0030(r1) f2e6: b1 4f 32 00 mov @r15+, 50(r1) ;0x0032(r1) f2ea: 81 93 32 00 tst 50(r1) ;0x0032(r1) f2ee: 04 38 jl $+10 ;abs 0xf2f8 f2f0: f1 40 0a 00 mov.b #10, 52(r1) ;#0x000a, 0x0034(r1) f2f4: 34 00 f2f6: 29 3f jmp $-428 ;abs 0xf14a f2f8: b1 e3 30 00 xor #-1, 48(r1) ;r3 As==11, 0x0030(r1) f2fc: b1 e3 32 00 xor #-1, 50(r1) ;r3 As==11, 0x0032(r1) f300: 91 53 30 00 inc 48(r1) ;0x0030(r1) f304: 81 63 32 00 adc 50(r1) ;0x0032(r1) f308: f1 40 2d 00 mov.b #45, 42(r1) ;#0x002d, 0x002a(r1) f30c: 2a 00 f30e: f0 3f jmp $-30 ;abs 0xf2f0 f310: 0f 45 mov r5, r15 f312: 25 53 incd r5 f314: a1 4f 30 00 mov @r15, 48(r1) ;0x0030(r1) f318: 91 41 30 00 mov 48(r1), 50(r1) ;0x0030(r1), 0x0032(r1) f31c: 32 00 f31e: 91 51 32 00 rla 50(r1) ;0x0032(r1) f322: 32 00 f324: 91 71 32 00 subc 50(r1), 50(r1) ;0x0032(r1), 0x0032(r1) f328: 32 00 f32a: b1 e3 32 00 xor #-1, 50(r1) ;r3 As==11, 0x0032(r1) f32e: dd 3f jmp $-68 ;abs 0xf2ea f330: d1 d3 2e 00 bis.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f334: d1 3f jmp $-92 ;abs 0xf2d8 f336: 81 41 2c 00 mov r1, 44(r1) ;0x002c(r1) f33a: 0f 45 mov r5, r15 f33c: 25 53 incd r5 f33e: e1 4f 00 00 mov.b @r15, 0(r1) ;0x0000(r1) f342: 73 3e jmp $-792 ;abs 0xf02a f344: e1 d2 2e 00 bis.b #4, 46(r1) ;r2 As==10, 0x002e(r1) f348: 30 40 1c ef br #0xef1c f34c: f1 b0 10 00 bit.b #16, 46(r1) ;#0x0010, 0x002e(r1) f350: 2e 00 f352: 02 24 jz $+6 ;abs 0xf358 f354: 30 40 1c ef br #0xef1c f358: f1 d0 20 00 bis.b #32, 46(r1) ;#0x0020, 0x002e(r1) f35c: 2e 00 f35e: 30 40 1c ef br #0xef1c f362: 67 46 mov.b @r6, r7 f364: 16 53 inc r6 f366: 77 90 2a 00 cmp.b #42, r7 ;#0x002a f36a: 24 24 jz $+74 ;abs 0xf3b4 f36c: 0d 43 clr r13 f36e: 4f 47 mov.b r7, r15 f370: 7f 50 d0 ff add.b #-48, r15 ;#0xffd0 f374: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a f378: 16 2c jc $+46 ;abs 0xf3a6 f37a: 0f 4d mov r13, r15 f37c: 0f 5f rla r15 f37e: 0f 5f rla r15 f380: 0e 4d mov r13, r14 f382: 0e 5e rla r14 f384: 0d 4f mov r15, r13 f386: 0d 5e add r14, r13 f388: 0d 5e add r14, r13 f38a: 0d 5e add r14, r13 f38c: 4f 47 mov.b r7, r15 f38e: 8f 11 sxt r15 f390: 0d 5f add r15, r13 f392: 3d 50 d0 ff add #-48, r13 ;#0xffd0 f396: 67 46 mov.b @r6, r7 f398: 16 53 inc r6 f39a: 4f 47 mov.b r7, r15 f39c: 7f 50 d0 ff add.b #-48, r15 ;#0xffd0 f3a0: 7f 90 0a 00 cmp.b #10, r15 ;#0x000a f3a4: ea 2b jnc $-42 ;abs 0xf37a f3a6: 0f 4d mov r13, r15 f3a8: 3d 93 cmp #-1, r13 ;r3 As==11 f3aa: 01 34 jge $+4 ;abs 0xf3ae f3ac: 3f 43 mov #-1, r15 ;r3 As==11 f3ae: 4b 4f mov.b r15, r11 f3b0: 30 40 20 ef br #0xef20 f3b4: 0f 45 mov r5, r15 f3b6: 25 53 incd r5 f3b8: 2d 4f mov @r15, r13 f3ba: 0f 4d mov r13, r15 f3bc: 3d 93 cmp #-1, r13 ;r3 As==11 f3be: 01 34 jge $+4 ;abs 0xf3c2 f3c0: 3f 43 mov #-1, r15 ;r3 As==11 f3c2: 4b 4f mov.b r15, r11 f3c4: 30 40 1c ef br #0xef1c f3c8: f1 40 2b 00 mov.b #43, 42(r1) ;#0x002b, 0x002a(r1) f3cc: 2a 00 f3ce: 30 40 1c ef br #0xef1c f3d2: f1 d0 10 00 bis.b #16, 46(r1) ;#0x0010, 0x002e(r1) f3d6: 2e 00 f3d8: f1 f0 df ff and.b #-33, 46(r1) ;#0xffdf, 0x002e(r1) f3dc: 2e 00 f3de: 30 40 1c ef br #0xef1c f3e2: 0f 45 mov r5, r15 f3e4: 25 53 incd r5 f3e6: e1 4f 2f 00 mov.b @r15, 47(r1) ;0x002f(r1) f3ea: c1 93 2f 00 tst.b 47(r1) ;0x002f(r1) f3ee: 02 38 jl $+6 ;abs 0xf3f4 f3f0: 30 40 1c ef br #0xef1c f3f4: f1 e3 2f 00 xor.b #-1, 47(r1) ;r3 As==11, 0x002f(r1) f3f8: d1 53 2f 00 inc.b 47(r1) ;0x002f(r1) f3fc: ea 3f jmp $-42 ;abs 0xf3d2 f3fe: f1 d2 2e 00 bis.b #8, 46(r1) ;r2 As==11, 0x002e(r1) f402: 30 40 1c ef br #0xef1c f406: c1 93 2a 00 tst.b 42(r1) ;0x002a(r1) f40a: 02 24 jz $+6 ;abs 0xf410 f40c: 30 40 1c ef br #0xef1c f410: f1 40 20 00 mov.b #32, 42(r1) ;#0x0020, 0x002a(r1) f414: 2a 00 f416: 30 40 1c ef br #0xef1c f41a: d1 b3 2e 00 bit.b #1, 46(r1) ;r3 As==01, 0x002e(r1) f41e: 08 24 jz $+18 ;abs 0xf430 f420: 0f 45 mov r5, r15 f422: 25 52 add #4, r5 ;r2 As==10 f424: b1 4f 30 00 mov @r15+, 48(r1) ;0x0030(r1) f428: b1 4f 32 00 mov @r15+, 50(r1) ;0x0032(r1) f42c: 30 40 3a ef br #0xef3a f430: 0f 45 mov r5, r15 f432: 25 53 incd r5 f434: a1 4f 30 00 mov @r15, 48(r1) ;0x0030(r1) f438: 81 43 32 00 mov #0, 50(r1) ;r3 As==00, 0x0032(r1) f43c: 30 40 3a ef br #0xef3a f440: 0e 4d mov r13, r14 f442: b0 12 4e ee call #0xee4e f446: 0f 93 tst r15 f448: 02 38 jl $+6 ;abs 0xf44e f44a: 30 40 00 ef br #0xef00 f44e: 1f 42 02 02 mov &0x0202,r15 f452: 31 50 3c 00 add #60, r1 ;#0x003c f456: 34 41 pop r4 f458: 35 41 pop r5 f45a: 36 41 pop r6 f45c: 37 41 pop r7 f45e: 38 41 pop r8 f460: 39 41 pop r9 f462: 3a 41 pop r10 f464: 3b 41 pop r11 f466: 30 41 ret 0000f468 : f468: 0d 4f mov r15, r13 f46a: 0f 4e mov r14, r15 f46c: 6e 4d mov.b @r13, r14 f46e: 4e 9f cmp.b r15, r14 f470: 06 24 jz $+14 ;abs 0xf47e f472: 4e 93 tst.b r14 f474: 02 24 jz $+6 ;abs 0xf47a f476: 1d 53 inc r13 f478: f9 3f jmp $-12 ;abs 0xf46c f47a: 0f 43 clr r15 f47c: 30 41 ret f47e: 0f 4d mov r13, r15 f480: 30 41 ret 0000f482 : f482: 0b 12 push r11 f484: 0b 4f mov r15, r11 f486: 4c 4e mov.b r14, r12 f488: 0d 93 tst r13 f48a: 07 24 jz $+16 ;abs 0xf49a f48c: 0e 4b mov r11, r14 f48e: 6f 4e mov.b @r14, r15 f490: 1e 53 inc r14 f492: 4f 9c cmp.b r12, r15 f494: 04 24 jz $+10 ;abs 0xf49e f496: 3d 53 add #-1, r13 ;r3 As==11 f498: fa 23 jnz $-10 ;abs 0xf48e f49a: 0f 43 clr r15 f49c: 02 3c jmp $+6 ;abs 0xf4a2 f49e: 0f 4e mov r14, r15 f4a0: 3f 53 add #-1, r15 ;r3 As==11 f4a2: 3b 41 pop r11 f4a4: 30 41 ret 0000f4a6 : f4a6: 0b 12 push r11 f4a8: 0b 4d mov r13, r11 f4aa: 0d 93 tst r13 f4ac: 0a 24 jz $+22 ;abs 0xf4c2 f4ae: 0c 4f mov r15, r12 f4b0: 0d 4e mov r14, r13 f4b2: 6e 4d mov.b @r13, r14 f4b4: 1d 53 inc r13 f4b6: 6f 4c mov.b @r12, r15 f4b8: 1c 53 inc r12 f4ba: 4f 9e cmp.b r14, r15 f4bc: 04 20 jnz $+10 ;abs 0xf4c6 f4be: 3b 53 add #-1, r11 ;r3 As==11 f4c0: f8 23 jnz $-14 ;abs 0xf4b2 f4c2: 0c 43 clr r12 f4c4: 05 3c jmp $+12 ;abs 0xf4d0 f4c6: 5c 4c ff ff mov.b -1(r12),r12 ;0xffff(r12) f4ca: 5f 4d ff ff mov.b -1(r13),r15 ;0xffff(r13) f4ce: 0c 8f sub r15, r12 f4d0: 0f 4c mov r12, r15 f4d2: 3b 41 pop r11 f4d4: 30 41 ret 0000f4d6 : f4d6: 0b 12 push r11 f4d8: 0a 12 push r10 f4da: 09 12 push r9 f4dc: 08 12 push r8 f4de: 0b 4f mov r15, r11 f4e0: 0a 4e mov r14, r10 f4e2: 69 4e mov.b @r14, r9 f4e4: 1a 53 inc r10 f4e6: 49 93 tst.b r9 f4e8: 15 24 jz $+44 ;abs 0xf514 f4ea: 08 4a mov r10, r8 f4ec: 18 83 dec r8 f4ee: 18 53 inc r8 f4f0: c8 93 00 00 tst.b 0(r8) ;0x0000(r8) f4f4: fc 23 jnz $-6 ;abs 0xf4ee f4f6: 08 8a sub r10, r8 f4f8: 6f 4b mov.b @r11, r15 f4fa: 1b 53 inc r11 f4fc: 4f 93 tst.b r15 f4fe: 0c 24 jz $+26 ;abs 0xf518 f500: 4f 99 cmp.b r9, r15 f502: fa 23 jnz $-10 ;abs 0xf4f8 f504: 0d 48 mov r8, r13 f506: 0e 4a mov r10, r14 f508: 0f 4b mov r11, r15 f50a: b0 12 24 f5 call #0xf524 f50e: 0f 93 tst r15 f510: f3 23 jnz $-24 ;abs 0xf4f8 f512: 3b 53 add #-1, r11 ;r3 As==11 f514: 0f 4b mov r11, r15 f516: 01 3c jmp $+4 ;abs 0xf51a f518: 0f 43 clr r15 f51a: 38 41 pop r8 f51c: 39 41 pop r9 f51e: 3a 41 pop r10 f520: 3b 41 pop r11 f522: 30 41 ret 0000f524 : f524: 0b 12 push r11 f526: 0b 4f mov r15, r11 f528: 0d 93 tst r13 f52a: 02 20 jnz $+6 ;abs 0xf530 f52c: 0d 43 clr r13 f52e: 0f 3c jmp $+32 ;abs 0xf54e f530: 6f 4e mov.b @r14, r15 f532: 1e 53 inc r14 f534: 6c 4b mov.b @r11, r12 f536: 4c 9f cmp.b r15, r12 f538: 06 20 jnz $+14 ;abs 0xf546 f53a: 1b 53 inc r11 f53c: 4c 93 tst.b r12 f53e: f6 27 jz $-18 ;abs 0xf52c f540: 3d 53 add #-1, r13 ;r3 As==11 f542: f6 23 jnz $-18 ;abs 0xf530 f544: f3 3f jmp $-24 ;abs 0xf52c f546: 4d 4c mov.b r12, r13 f548: 5f 4e ff ff mov.b -1(r14),r15 ;0xffff(r14) f54c: 0d 8f sub r15, r13 f54e: 0f 4d mov r13, r15 f550: 3b 41 pop r11 f552: 30 41 ret 0000f554 <__mulhi3>: f554: 0e 43 clr r14 f556: 0a 93 tst r10 f558: 07 24 jz $+16 ;abs 0xf568 f55a: 12 c3 clrc f55c: 0c 10 rrc r12 f55e: 01 28 jnc $+4 ;abs 0xf562 f560: 0e 5a add r10, r14 f562: 0a 5a rla r10 f564: 0c 93 tst r12 f566: f7 23 jnz $-16 ;abs 0xf556 f568: 30 41 ret 0000f56a <__udivmodsi4>: f56a: 0f ef xor r15, r15 f56c: 0e ee xor r14, r14 f56e: 39 40 21 00 mov #33, r9 ;#0x0021 f572: 0a 3c jmp $+22 ;abs 0xf588 f574: 08 10 rrc r8 f576: 0e 6e rlc r14 f578: 0f 6f rlc r15 f57a: 0f 9b cmp r11, r15 f57c: 05 28 jnc $+12 ;abs 0xf588 f57e: 02 20 jnz $+6 ;abs 0xf584 f580: 0e 9a cmp r10, r14 f582: 02 28 jnc $+6 ;abs 0xf588 f584: 0e 8a sub r10, r14 f586: 0f 7b subc r11, r15 f588: 0c 6c rlc r12 f58a: 0d 6d rlc r13 f58c: 08 68 rlc r8 f58e: 19 83 dec r9 f590: f1 23 jnz $-28 ;abs 0xf574 f592: 30 41 ret 0000f594 <__stop_progExec__>: f594: ff 3f jmp $+0 ;abs 0xf594 Disassembly of section .vectors: 0000ffe0 : ffe0: 30 e0 30 e0 36 e0 30 e0 30 e0 30 e0 30 e0 30 e0 0.0.6.0.0.0.0.0. fff0: 30 e0 30 e0 30 e0 30 e0 30 e0 30 e0 30 e0 00 e0 0.0.0.0.0.0.0...