rf_mon.elf: file format elf32-msp430 SYMBOL TABLE: 0000f800 l d .text 00000000 .text 00000200 l d .data 00000000 .data 00000204 l d .bss 00000000 .bss 00000206 l d .noinit 00000000 .noinit 0000ffe0 l d .vectors 00000000 .vectors 00000000 l d .debug_aranges 00000000 .debug_aranges 00000000 l d .debug_info 00000000 .debug_info 00000000 l d .debug_abbrev 00000000 .debug_abbrev 00000000 l d .debug_line 00000000 .debug_line 00000000 l d .debug_frame 00000000 .debug_frame 00000000 l d .debug_str 00000000 .debug_str 00000000 l d .debug_loc 00000000 .debug_loc 00000000 l d .debug_ranges 00000000 .debug_ranges 00000000 l df *ABS* 00000000 main.c 00000200 l O .data 00000002 next_sqr.1346 00000202 l O .data 00000002 sqr_step.1347 0000f888 l .text 00000000 __br_unexpected_ 0000007c g *ABS* 00000000 __USISR 00000057 g *ABS* 00000000 __BCSCTL1 00000174 g *ABS* 00000000 __TACCR1 00000004 g *ABS* 00000000 __data_size 0000f888 w .text 00000000 __isr_14 0000007a g *ABS* 00000000 __USICKCTL 00000128 g *ABS* 00000000 __FCTL1 00000024 g *ABS* 00000000 __P1IES 0000f888 w .text 00000000 __isr_4 00000002 g *ABS* 00000000 __IFG1 0000012e g *ABS* 00000000 __TAIV 00000000 g .vectors 00000000 _efartext 0000002b g *ABS* 00000000 __P2IFG 0000f918 g *ABS* 00000000 _etext 00000002 g *ABS* 00000000 __bss_size 00000078 g *ABS* 00000000 __USICTL 0000f800 w .text 00000000 __watchdog_support 0000f882 w .text 00000000 __stop_progExec__ 0000f88c g F .text 0000008a ta1_isr 0000002d g *ABS* 00000000 __P2IE 0000f888 w .text 00000000 __isr_11 00000025 g *ABS* 00000000 __P1IE 00000049 g *ABS* 00000000 __ADC10DTC1 0000f888 w .text 00000000 __isr_5 0000f918 g *ABS* 00000000 __data_load_start 0000f888 g .text 00000000 __dtors_end 00000053 g *ABS* 00000000 __BCSCTL3 000001bc g *ABS* 00000000 __ADC10SA 0000007a g *ABS* 00000000 __USICCTL 0000f888 w .text 00000000 __isr_2 00000160 g *ABS* 00000000 __TACTL 0000012c g *ABS* 00000000 __FCTL3 0000f888 w .text 00000000 __isr_10 0000002e g *ABS* 00000000 __P2SEL 00000023 g *ABS* 00000000 __P1IFG 0000004a g *ABS* 00000000 __ADC10AE0 00000172 g *ABS* 00000000 __TACCR0 00000056 g *ABS* 00000000 __DCOCTL 00000206 g O .noinit 00000002 __wdt_clear_value 0000f888 w .text 00000000 __isr_7 0000ffe0 g O .vectors 00000020 __ivtbl_16 00000028 g *ABS* 00000000 __P2IN 000001b4 g *ABS* 00000000 __ADC10MEM 0000f888 w .text 00000000 __isr_0 00000029 g *ABS* 00000000 __P2OUT 0000012a g *ABS* 00000000 __FCTL2 0000f828 w .text 00000000 __do_clear_bss 00000021 g *ABS* 00000000 __P1OUT 0000002c g *ABS* 00000000 __P2IES 00000026 g *ABS* 00000000 __P1SEL 00000079 g *ABS* 00000000 __USICTL1 00000027 g *ABS* 00000000 __P1REN 0000f916 w .text 00000000 _unexpected_ 0000f88c g .text 00000000 __isr_8 00000204 g O .bss 00000002 idx 0000f888 w .text 00000000 __isr_3 0000f800 w .text 00000000 _reset_vector__ 0000f888 g .text 00000000 __ctors_start 0000f888 w .text 00000000 __isr_12 0000f810 w .text 00000000 __do_copy_data 00000204 g .bss 00000000 __bss_start 0000f83e g F .text 00000044 main 0000f888 w .text 00000000 __isr_13 00000170 g *ABS* 00000000 __TAR 00000162 g *ABS* 00000000 __TACCTL0 00010000 g .vectors 00000000 _vectors_end 0000002a g *ABS* 00000000 __P2DIR 0000002f g *ABS* 00000000 __P2REN 0000007d g *ABS* 00000000 __USISRH 000001b0 g *ABS* 00000000 __ADC10CTL0 0000f888 w .text 00000000 __isr_9 000010fe g *ABS* 00000000 __CALDCO_1MHZ 0000f80c w .text 00000000 __init_stack 0000f888 g .text 00000000 __dtors_start 0000f888 w .text 00000000 __isr_6 0000f888 g .text 00000000 __ctors_end 00000280 g *ABS* 00000000 __stack 0000f888 w .text 00000000 __isr_1 00000204 g .data 00000000 _edata 00000208 g *ABS* 00000000 _end 0000007b g *ABS* 00000000 __USICNT 00000048 g *ABS* 00000000 __ADC10DTC0 000001b2 g *ABS* 00000000 __ADC10CTL1 00000058 g *ABS* 00000000 __BCSCTL2 0000f882 w .text 00000000 _endless_loop__ 00000022 g *ABS* 00000000 __P1DIR 00000164 g *ABS* 00000000 __TACCTL1 000010ff g *ABS* 00000000 __CALBC1_1MHZ 0000f810 w .text 00000000 __low_level_init 00000200 g .data 00000000 __data_start 00000120 g *ABS* 00000000 __WDTCTL 00000000 g *ABS* 00000000 __IE1 00000078 g *ABS* 00000000 __USICTL0 00000020 g *ABS* 00000000 __P1IN 0000007c g *ABS* 00000000 __USISRL Disassembly of section .text: 0000f800 <__watchdog_support>: f800: 55 42 20 01 mov.b &0x0120,r5 f804: 35 d0 08 5a bis #23048, r5 ;#0x5a08 f808: 82 45 06 02 mov r5, &0x0206 0000f80c <__init_stack>: f80c: 31 40 80 02 mov #640, r1 ;#0x0280 0000f810 <__do_copy_data>: f810: 3f 40 04 00 mov #4, r15 ;#0x0004 f814: 0f 93 tst r15 f816: 08 24 jz $+18 ;abs 0xf828 f818: 92 42 06 02 mov &0x0206,&0x0120 f81c: 20 01 f81e: 2f 83 decd r15 f820: 9f 4f 18 f9 mov -1768(r15),512(r15);0xf918(r15), 0x0200(r15) f824: 00 02 f826: f8 23 jnz $-14 ;abs 0xf818 0000f828 <__do_clear_bss>: f828: 3f 40 02 00 mov #2, r15 ;#0x0002 f82c: 0f 93 tst r15 f82e: 07 24 jz $+16 ;abs 0xf83e f830: 92 42 06 02 mov &0x0206,&0x0120 f834: 20 01 f836: 1f 83 dec r15 f838: cf 43 04 02 mov.b #0, 516(r15);r3 As==00, 0x0204(r15) f83c: f9 23 jnz $-12 ;abs 0xf830 0000f83e
: int idx = 0; // idx to PWM's duty cycle curve (= brightness) int main(void) { // Stop watchdog WDTCTL = WDTPW + WDTHOLD; f83e: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 f842: 20 01 // Set clock to 1 MHz DCOCTL= 0; f844: c2 43 56 00 mov.b #0, &0x0056 ;r3 As==00 BCSCTL1= CALBC1_1MHZ; f848: d2 42 ff 10 mov.b &0x10ff,&0x0057 f84c: 57 00 DCOCTL= CALDCO_1MHZ; f84e: d2 42 fe 10 mov.b &0x10fe,&0x0056 f852: 56 00 // SMCLK = 1 MHz / 8 = 125 KHz (SLAU144E p.5-15) BCSCTL2 |= DIVS_3; f854: f2 d0 06 00 bis.b #6, &0x0058 ;#0x0006 f858: 58 00 // Make P1.6 (green led) an output. SLAU144E p.8-3 P1DIR |= BIT6; f85a: f2 d0 40 00 bis.b #64, &0x0022 ;#0x0040 f85e: 22 00 // P1.6 = TA0.1 (timer A's output). SLAS694C p.41 P1SEL |= BIT6; f860: f2 d0 40 00 bis.b #64, &0x0026 ;#0x0040 f864: 26 00 // PWM period = 125 KHz / 625 = 200 Hz TACCR0 = 625; f866: b2 40 71 02 mov #625, &0x0172 ;#0x0271 f86a: 72 01 // Source Timer A from SMCLK (TASSEL_2), up mode (MC_1). // Up mode counts up to TACCR0. SLAU144E p.12-20 TACTL = TASSEL_2 | MC_1; f86c: b2 40 10 02 mov #528, &0x0160 ;#0x0210 f870: 60 01 // OUTMOD_7 = Reset/set output when the timer counts to TACCR1/TACCR0 // CCIE = Interrupt when timer counts to TACCR1 TACCTL1 = OUTMOD_7 | CCIE; f872: b2 40 f0 00 mov #240, &0x0164 ;#0x00f0 f876: 64 01 // Initial CCR1 (= brightness) TACCR1 = 0; f878: 82 43 74 01 mov #0, &0x0174 ;r3 As==00 // LPM0 (shut down the CPU) with interrupts enabled __bis_SR_register(CPUOFF | GIE); f87c: 32 d0 18 00 bis #24, r2 ;#0x0018 // Silly return to make gcc happy return 0; } f880: 0f 43 clr r15 0000f882 <__stop_progExec__>: f882: 32 d0 f0 00 bis #240, r2 ;#0x00f0 f886: fd 3f jmp $-4 ;abs 0xf882 0000f888 <__ctors_end>: f888: 30 40 16 f9 br #0xf916 0000f88c : // This will be called when timer counts to TACCR1. interrupt(TIMERA1_VECTOR) ta1_isr(void) { f88c: 0f 12 push r15 f88e: 0e 12 push r14 f890: 0d 12 push r13 f892: 0c 12 push r12 int new_ccr1 = 1; static unsigned int next_sqr = 1, sqr_step = 3; // Clear interrupt flag TACCTL1 &= ~CCIFG; f894: b2 f0 fe ff and #-2, &0x0164 ;#0xfffe f898: 64 01 new_ccr1 = (next_sqr >> 9) + 1; f89a: 1d 42 00 02 mov &0x0200,r13 f89e: 0f 4d mov r13, r15 f8a0: 8f 10 swpb r15 f8a2: 4f 4f mov.b r15, r15 f8a4: 12 c3 clrc f8a6: 0f 10 rrc r15 f8a8: 0e 4f mov r15, r14 f8aa: 1e 53 inc r14 if (!(idx++ & 1)) { // send each value twice. f8ac: 1c 42 04 02 mov &0x0204,r12 f8b0: 0f 4c mov r12, r15 f8b2: 1f 53 inc r15 f8b4: 82 4f 04 02 mov r15, &0x0204 f8b8: 1c f3 and #1, r12 ;r3 As==01 f8ba: 0b 20 jnz $+24 ;abs 0xf8d2 if (idx < 500) { f8bc: 3f 90 f4 01 cmp #500, r15 ;#0x01f4 f8c0: 13 34 jge $+40 ;abs 0xf8e8 next_sqr += sqr_step; f8c2: 1f 42 02 02 mov &0x0202,r15 f8c6: 0d 5f add r15, r13 f8c8: 82 4d 00 02 mov r13, &0x0200 sqr_step += 2; f8cc: 2f 53 incd r15 f8ce: 82 4f 02 02 mov r15, &0x0202 } } // Wait to set the new TACCR1 until TAR has gone past it, so that we // don't get interrupted again in this period. while (TAR <= new_ccr1) f8d2: 1f 42 70 01 mov &0x0170,r15 f8d6: 0e 9f cmp r15, r14 f8d8: fc 2f jc $-6 ;abs 0xf8d2 ; TACCR1 = new_ccr1; f8da: 82 4e 74 01 mov r14, &0x0174 } f8de: 3c 41 pop r12 f8e0: 3d 41 pop r13 f8e2: 3e 41 pop r14 f8e4: 3f 41 pop r15 f8e6: 00 13 reti if (!(idx++ & 1)) { // send each value twice. if (idx < 500) { next_sqr += sqr_step; sqr_step += 2; } else if (idx < 1000) { f8e8: 3f 90 e8 03 cmp #1000, r15 ;#0x03e8 f8ec: 0d 34 jge $+28 ;abs 0xf908 sqr_step -= 2; f8ee: 1f 42 02 02 mov &0x0202,r15 f8f2: 2f 83 decd r15 f8f4: 82 4f 02 02 mov r15, &0x0202 next_sqr -= sqr_step; f8f8: 0d 8f sub r15, r13 f8fa: 82 4d 00 02 mov r13, &0x0200 } } // Wait to set the new TACCR1 until TAR has gone past it, so that we // don't get interrupted again in this period. while (TAR <= new_ccr1) f8fe: 1f 42 70 01 mov &0x0170,r15 f902: 0e 9f cmp r15, r14 f904: e6 2f jc $-50 ;abs 0xf8d2 f906: e9 3f jmp $-44 ;abs 0xf8da sqr_step += 2; } else if (idx < 1000) { sqr_step -= 2; next_sqr -= sqr_step; } else { idx = 0; f908: 82 43 04 02 mov #0, &0x0204 ;r3 As==00 } } // Wait to set the new TACCR1 until TAR has gone past it, so that we // don't get interrupted again in this period. while (TAR <= new_ccr1) f90c: 1f 42 70 01 mov &0x0170,r15 f910: 0e 9f cmp r15, r14 f912: df 2f jc $-64 ;abs 0xf8d2 f914: e2 3f jmp $-58 ;abs 0xf8da 0000f916 <_unexpected_>: f916: 00 13 reti Disassembly of section .vectors: 0000ffe0 <__ivtbl_16>: ffe0: 88 f8 88 f8 88 f8 88 f8 88 f8 88 f8 88 f8 88 f8 ................ fff0: 8c f8 88 f8 88 f8 88 f8 88 f8 88 f8 88 f8 00 f8 ................